From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.gentoo.org (woodpecker.gentoo.org [140.211.166.183]) by sourceware.org (Postfix) with ESMTP id 87BE93857C7C for ; Sat, 5 Nov 2022 13:33:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 87BE93857C7C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gentoo.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gentoo.org Received: by smtp.gentoo.org (Postfix, from userid 559) id 395B43412D2; Sat, 5 Nov 2022 13:33:49 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH 20/26] sim: frv: invert sim_cpu storage Date: Sat, 5 Nov 2022 20:32:52 +0700 Message-Id: <20221105133258.23409-21-vapier@gentoo.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221105133258.23409-1-vapier@gentoo.org> References: <20221101151158.24916-1-vapier@gentoo.org> <20221105133258.23409-1-vapier@gentoo.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The cpu.h change is in generated cgen code, but that has been sent upstream too, so the next regen should include it automatically. --- sim/frv/cpu.h | 2 +- sim/frv/sim-if.c | 2 +- sim/frv/sim-main.h | 37 ++++++++++++++++--------------------- 3 files changed, 18 insertions(+), 23 deletions(-) diff --git a/sim/frv/cpu.h b/sim/frv/cpu.h index 902c6d4ae48d..d2409131b659 100644 --- a/sim/frv/cpu.h +++ b/sim/frv/cpu.h @@ -158,7 +158,7 @@ frvbf_h_spr_set_handler (current_cpu, (index), (x));\ #define GET_H_CCCR(a1) CPU (h_cccr)[a1] #define SET_H_CCCR(a1, x) (CPU (h_cccr)[a1] = (x)) } hardware; -#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) +#define CPU_CGEN_HW(cpu) (& FRV_SIM_CPU (cpu)->cpu_data.hardware) } FRVBF_CPU_DATA; /* Virtual regs. */ diff --git a/sim/frv/sim-if.c b/sim/frv/sim-if.c index a7a3bb6a296b..f0487f5732ff 100644 --- a/sim/frv/sim-if.c +++ b/sim/frv/sim-if.c @@ -65,7 +65,7 @@ sim_open (SIM_OPEN_KIND kind, host_callback *callback, bfd *abfd, current_target_byte_order = BFD_ENDIAN_BIG; /* The cpu data is kept in a separately allocated chunk of memory. */ - if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) + if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct frv_sim_cpu)) != SIM_RC_OK) { free_state (sd); return 0; diff --git a/sim/frv/sim-main.h b/sim/frv/sim-main.h index 01ef0b680b90..3e40bd52ab38 100644 --- a/sim/frv/sim-main.h +++ b/sim/frv/sim-main.h @@ -22,6 +22,8 @@ along with this program. If not, see . */ /* Main header for the frv. */ +#define SIM_HAVE_COMMON_SIM_CPU + /* This is a global setting. Different cpu families can't mix-n-match -scache and -pbb. However some cpu families may use -simple while others use one of -scache/-pbb. ???? */ @@ -51,15 +53,7 @@ void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia); extern void frv_sim_close (SIM_DESC sd, int quitting); #define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__) -/* The _sim_cpu struct. */ - -struct _sim_cpu { - /* sim/common cpu base. */ - sim_cpu_base base; - - /* Static parts of cgen. */ - CGEN_CPU cgen_cpu; - +struct frv_sim_cpu { /* CPU specific parts go here. Note that in files that don't need to access these pieces WANT_CPU_FOO won't be defined and thus these parts won't appear. This is ok in the @@ -72,40 +66,41 @@ struct _sim_cpu { /* Control information for registers */ FRV_REGISTER_CONTROL register_control; -#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control) +#define CPU_REGISTER_CONTROL(cpu) (& FRV_SIM_CPU (cpu)->register_control) FRV_VLIW vliw; -#define CPU_VLIW(cpu) (& (cpu)->vliw) +#define CPU_VLIW(cpu) (& FRV_SIM_CPU (cpu)->vliw) FRV_CACHE insn_cache; -#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache) +#define CPU_INSN_CACHE(cpu) (& FRV_SIM_CPU (cpu)->insn_cache) FRV_CACHE data_cache; -#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache) +#define CPU_DATA_CACHE(cpu) (& FRV_SIM_CPU (cpu)->data_cache) FRV_PROFILE_STATE profile_state; -#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state) +#define CPU_PROFILE_STATE(cpu) (& FRV_SIM_CPU (cpu)->profile_state) int debug_state; -#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state) +#define CPU_DEBUG_STATE(cpu) (FRV_SIM_CPU (cpu)->debug_state) SI load_address; -#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address) +#define CPU_LOAD_ADDRESS(cpu) (FRV_SIM_CPU (cpu)->load_address) SI load_length; -#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length) +#define CPU_LOAD_LENGTH(cpu) (FRV_SIM_CPU (cpu)->load_length) SI load_flag; -#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag) -#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag) +#define CPU_LOAD_SIGNED(cpu) (FRV_SIM_CPU (cpu)->load_flag) +#define CPU_LOAD_LOCK(cpu) (FRV_SIM_CPU (cpu)->load_flag) SI store_flag; -#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag) +#define CPU_RSTR_INVALIDATE(cpu) (FRV_SIM_CPU (cpu)->store_flag) unsigned long elf_flags; -#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags) +#define CPU_ELF_FLAGS(cpu) (FRV_SIM_CPU (cpu)->elf_flags) #endif /* defined (WANT_CPU_FRVBF) */ }; +#define FRV_SIM_CPU(cpu) ((struct frv_sim_cpu *) CPU_ARCH_DATA (cpu)) /* Misc. */ -- 2.38.1