From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by sourceware.org (Postfix) with ESMTPS id 8E9203854579 for ; Fri, 18 Nov 2022 15:53:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8E9203854579 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AICAhgR015712; Fri, 18 Nov 2022 16:53:45 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=selector1; bh=3cJKgZ+/HHm3+xoYXtFUnnRq0iN+4f/MuKxwAnK+skU=; b=Au9L+okWWeIde/R+JYQDOzp4RwiWZtmhrj97z6bWSUhA7NC88jGXkodJa83F0N/RjEfA 50Tv4v2dImGRghHmbY3yagYvUb5rGOiWiyReOa7XpkqM5jr1FlqejOdKrIN51l1w8NF7 YsRWCPFE5irfh4c48VcQ9J5kjXfuyESktb2tfJ84R5eweKthaxixaIbaNtPFDkLASibr iNE/FtYvoF6DjZKQWjXlBQkA89yNNOQxrTcRNoaWIQJ0iXRr2giYEGjQRMoOKXDPnFVC k+8BCgHAQ+Hl8D8rp+x1d2nHZOx3Tp3jMSSXzALGe6T19yqBYOfQWaZU7bp9EAiT4Zpq /w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3kx0ph4t0a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 18 Nov 2022 16:53:45 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 577D110003A; Fri, 18 Nov 2022 16:53:41 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 50CEA23C68D; Fri, 18 Nov 2022 16:53:41 +0100 (CET) Received: from jkgcxl0002.jkg.st.com (10.210.54.218) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Fri, 18 Nov 2022 16:53:40 +0100 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: , , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= , Yvan Roux Subject: [PATCH v2 4/4] gdb/arm: Use new dwarf2 function cache Date: Fri, 18 Nov 2022 16:52:53 +0100 Message-ID: <20221118155252.113476-5-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221118155252.113476-1-torbjorn.svensson@foss.st.com> References: <20221118155252.113476-1-torbjorn.svensson@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.210.54.218] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-18_04,2022-11-18_01,2022-06-22_01 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This patch resolves the performance issue reported in pr/29738 by caching the values for the stack pointers for the inner frame. By doing so, the impact can be reduced to checking the state and returning the appropriate value. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 96 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 64 insertions(+), 32 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index c011b2aa973..59cd0964d96 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3953,6 +3953,18 @@ struct frame_base arm_normal_base = { arm_normal_frame_base }; +struct arm_dwarf2_prev_register_cache +{ + /* Cached value of the coresponding stack pointer for the inner frame. */ + CORE_ADDR sp; + CORE_ADDR msp; + CORE_ADDR msp_s; + CORE_ADDR msp_ns; + CORE_ADDR psp; + CORE_ADDR psp_s; + CORE_ADDR psp_ns; +}; + static struct value * arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, int regnum) @@ -3961,6 +3973,48 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, arm_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); CORE_ADDR lr; ULONGEST cpsr; + struct arm_dwarf2_prev_register_cache *cache + = (struct arm_dwarf2_prev_register_cache *) dwarf2_frame_get_fn_data ( + this_frame, this_cache, arm_dwarf2_prev_register); + + if (!cache) + { + const unsigned int size = sizeof (struct arm_dwarf2_prev_register_cache); + cache = (struct arm_dwarf2_prev_register_cache *) + dwarf2_frame_allocate_fn_data (this_frame, this_cache, + arm_dwarf2_prev_register, size); + + if (tdep->have_sec_ext) + { + cache->sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + cache->msp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_s_regnum); + cache->msp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_ns_regnum); + cache->psp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_s_regnum); + cache->psp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_ns_regnum); + } + else if (tdep->is_m) + { + cache->sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + cache->msp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_regnum); + cache->psp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_regnum); + } + } if (regnum == ARM_PC_REGNUM) { @@ -4000,33 +4054,18 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, if (tdep->have_sec_ext) { - CORE_ADDR sp - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - CORE_ADDR msp_s - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_s_regnum); - CORE_ADDR msp_ns - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_ns_regnum); - CORE_ADDR psp_s - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_s_regnum); - CORE_ADDR psp_ns - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_ns_regnum); - bool is_msp = (regnum == tdep->m_profile_msp_regnum) - && (msp_s == sp || msp_ns == sp); + && (cache->msp_s == cache->sp || cache->msp_ns == cache->sp); bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum) - && (msp_s == sp); + && (cache->msp_s == cache->sp); bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum) - && (msp_ns == sp); + && (cache->msp_ns == cache->sp); bool is_psp = (regnum == tdep->m_profile_psp_regnum) - && (psp_s == sp || psp_ns == sp); + && (cache->psp_s == cache->sp || cache->psp_ns == cache->sp); bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum) - && (psp_s == sp); + && (cache->psp_s == cache->sp); bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum) - && (psp_ns == sp); + && (cache->psp_ns == cache->sp); override_with_sp_value = is_msp || is_msp_s || is_msp_ns || is_psp || is_psp_s || is_psp_ns; @@ -4034,17 +4073,10 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, } else if (tdep->is_m) { - CORE_ADDR sp - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - CORE_ADDR msp - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_regnum); - CORE_ADDR psp - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_regnum); - - bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp == msp); - bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp == psp); + bool is_msp = (regnum == tdep->m_profile_msp_regnum) + && (cache->sp == cache->msp); + bool is_psp = (regnum == tdep->m_profile_psp_regnum) + && (cache->sp == cache->psp); override_with_sp_value = is_msp || is_psp; } -- 2.25.1