From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id BA5D33858C52 for ; Wed, 23 Nov 2022 12:17:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BA5D33858C52 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2AN94eix028958; Wed, 23 Nov 2022 13:17:49 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : mime-version : content-type : content-transfer-encoding; s=selector1; bh=BbO+CfkFfANGEfrxl4aQjnmyM0THXhv8FP8tSh/Bp/w=; b=QgrBMUB7VvQ4OH7DPLqYjgKN7JyQ4efvK0931CES1xMEM7Pv+CH0UageePWqoXH91nIq DNadJhpWbPBDRnvYbE6gcIZDglWEigOX3YiYupG4tBa8yEjw+paFTg3ee8oqWK0I0iPo E5EDOocAYdl+CEIIK/JsJu5sMtD52jg1lIYzzB5LLj95glBdePZl1H9wKvML9JLL3pjN ewrc28HT/+7xVgEvwm4txaUNaeDRQgHXa82Cf1lwJEuSl/Pavs53+FcO0x5fgzwOL27R oQv6UYtYHh5OQORvE2IpgRtsrKvANxl1qEbOVAcCTGcbKAs7a2et4R/cSOtOS8tK2y4+ aw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3kxrax8n9b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Nov 2022 13:17:48 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 127C410002A; Wed, 23 Nov 2022 13:17:43 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E0A8921ED4A; Wed, 23 Nov 2022 13:17:43 +0100 (CET) Received: from jkgcxl0002.jkg.st.com (10.210.54.218) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.6; Wed, 23 Nov 2022 13:17:40 +0100 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= Subject: [PATCH v2] gdb/arm: Include FType bit in EXC_RETURN pattern on v8m Date: Wed, 23 Nov 2022 13:17:28 +0100 Message-ID: <20221123121728.2459860-1-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.210.54.218] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-11-23_06,2022-11-23_01,2022-06-22_01 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: For v8m, the EXC_RETURN pattern, without security extension, consists of FType, Mode and SPSEL. These are the same bits that are used in v7m. This patch extends the list of patterns to include also the FType bit and not just Mode and SPSEL bits for v8m targets without security extension. Signed-off-by: Torbjörn SVENSSON --- gdb/arm-tdep.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index a839f957440..f466b5938e4 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -828,13 +828,17 @@ arm_m_addr_is_lockup (CORE_ADDR addr) For more details see "B1.5.8 Exception return behavior" in both ARMv6-M and ARMv7-M Architecture Reference Manuals. - In the ARMv8-M Architecture Technical Reference also adds - for implementations without the Security Extension: + From ARMv8-M Architecture Technical Reference, D1.2.95 + FType, Mode and SPSEL bits are to be considerd when Security Extension is + not implemented. - EXC_RETURN Condition - 0xFFFFFFB0 Return to Handler mode. - 0xFFFFFFB8 Return to Thread mode using the main stack. - 0xFFFFFFBC Return to Thread mode using the process stack. */ + EXC_RETURN Return To Return Stack Frame Type + 0xFFFFFFA0 Handler mode Main Extended + 0xFFFFFFA8 Thread mode Main Extended + 0xFFFFFFAC Thread mode Process Extended + 0xFFFFFFB0 Handler mode Main Standard + 0xFFFFFFB8 Thread mode Main Standard + 0xFFFFFFBC Thread mode Process Standard */ static int arm_m_addr_is_magic (struct gdbarch *gdbarch, CORE_ADDR addr) @@ -859,6 +863,9 @@ arm_m_addr_is_magic (struct gdbarch *gdbarch, CORE_ADDR addr) switch (addr) { /* Values from ARMv8-M Architecture Technical Reference. */ + case 0xffffffa0: + case 0xffffffa8: + case 0xffffffac: case 0xffffffb0: case 0xffffffb8: case 0xffffffbc: -- 2.25.1