From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by sourceware.org (Postfix) with ESMTPS id BEF93382EF36 for ; Sat, 26 Nov 2022 02:05:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BEF93382EF36 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-142faa7a207so6970426fac.13 for ; Fri, 25 Nov 2022 18:05:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1TcQ2kD+hdzMiaerEbxrg2ui2DFGcnc4+RyccB86tEE=; b=JDCcT5dFdU/TndC4ccF3/e96WzqjRi5mUdYZXeufoGyXzBtY2CYFdqdbdz7v1BZVwJ EVjhh3N4dhVtBXsTOWMV06oZY6dUJtzqSU2oTyNgSUQ7ndKwDGzW6ZNu7aK7oeWMNy6I xCwpc98WIIMQS+aF6764Uun9UVIkRoYv7urqaKF3uF0kyPhADNBoTPCKioq8TE8uv3p1 3TgC558Ph6J5L6zw1lKN4oZNZqmECIWOF3iBC8nd2utO5CmRE3X7wBPml0ImU37dYqQb 8IghMONzIrj9wmRnfbccIKthi5MJrWrt84Bryiw5WUVFz6mh1+cTSC2M1wle2SkK/ft7 RdxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1TcQ2kD+hdzMiaerEbxrg2ui2DFGcnc4+RyccB86tEE=; b=grD4PRV2Y4h201qWBuTO+PODDtI5dGcpEIZejKuxOKqQqVbbiPkg6RUzi8NrjCRSRP 5ysRNiqliEsBXhS0yzDTX8jQrsYqJbEXwXIjDN8j8A7H/7QTTZII3/ridYWGrnHgFTM2 MPwSGOHdlGw9fuA6wm2voww5IW3hEylIEuSFWTaHQPaDvOf/Cmx2ZNN5xmkLYHyWDMfm aKMTZYQlA71U6mHIkDgdTFUQo83JSGKPyHewoDOAp68bKG3nPJVI7/87ZjLVqqDzQRWE Gou750jQ+bmYGCn7Nv5JTrra/i6hkoct3Bir0m3lYamIALkLtLQsAd4Hg28ycWtC89V+ Btgg== X-Gm-Message-State: ANoB5plugprUuBZTdaakvVaISIsJa698dSQW4i/bKnUD+BJMvSpea9s9 oDvpJIreePW950vH5gWSoMh9k/bUUh/Anw== X-Google-Smtp-Source: AA0mqf4ZSzR/PdMsXB276C/2aont2/lvd8hd1xsE/tAAGL0BtgZ4A8gA8C+mJmpPGLarnkf+NPkjSg== X-Received: by 2002:a05:6870:c687:b0:13b:cb39:3f80 with SMTP id cv7-20020a056870c68700b0013bcb393f80mr15318770oab.133.1669428327146; Fri, 25 Nov 2022 18:05:27 -0800 (PST) Received: from localhost ([2804:14d:7e39:8470:41ee:c7fc:c991:eee6]) by smtp.gmail.com with ESMTPSA id 67-20020a4a0946000000b0049ef7712ee5sm2136428ooa.11.2022.11.25.18.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 18:05:26 -0800 (PST) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Cc: Luis Machado , Thiago Jung Bauermann Subject: [PATCH v2 5/6] gdb/aarch64: Factor out most of the thread_architecture method Date: Sat, 26 Nov 2022 02:04:51 +0000 Message-Id: <20221126020452.1686509-6-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221126020452.1686509-1-thiago.bauermann@linaro.org> References: <20221126020452.1686509-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The same logic will be used by a subsequent commit when remotely debugging an aarch64-linux target. The code isn't changed, just moved around. --- gdb/aarch64-linux-nat.c | 28 ++-------------------------- gdb/aarch64-tdep.c | 35 +++++++++++++++++++++++++++++++++++ gdb/aarch64-tdep.h | 2 ++ 3 files changed, 39 insertions(+), 26 deletions(-) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index caefcb364852..ca230ea4fdb0 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -884,33 +884,9 @@ aarch64_linux_nat_target::thread_architecture (ptid_t ptid) /* Find the current gdbarch the same way as process_stratum_target. */ inferior *inf = find_inferior_ptid (this, ptid); gdb_assert (inf != NULL); - - /* If this is a 32-bit architecture, then this is ARM, not AArch64. - There's no SVE vectors here, so just return the inferior - architecture. */ - if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32) - return inf->gdbarch; - - /* Only return it if the current vector length matches the one in the tdep. */ - aarch64_gdbarch_tdep *tdep - = gdbarch_tdep (inf->gdbarch); uint64_t vq = aarch64_sve_get_vq (ptid.lwp ()); - if (vq == tdep->vq) - return inf->gdbarch; - - /* We reach here if the vector length for the thread is different from its - value at process start. Lookup gdbarch via info (potentially creating a - new one) by using a target description that corresponds to the new vq value - and the current architecture features. */ - - const struct target_desc *tdesc = gdbarch_target_desc (inf->gdbarch); - aarch64_features features = aarch64_features_from_target_desc (tdesc); - features.vq = vq; - - struct gdbarch_info info; - info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64); - info.target_desc = aarch64_read_description (features); - return gdbarch_find_by_info (info); + + return aarch64_update_gdbarch (inf->gdbarch, vq); } /* Implement the "supports_memory_tagging" target_ops method. */ diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 07330356fdcb..ffc128d91f60 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -3486,6 +3486,41 @@ aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum) || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)); } +/* Helper function for the "thread_architecture" target_ops method. + + Returns a new gdbarch that is equivalent to the given gdbarch, but with SVE + registers reflecting the given vq value. */ + +struct gdbarch * +aarch64_update_gdbarch (struct gdbarch *gdbarch, uint64_t vq) +{ + /* If this is a 32-bit architecture, then this is ARM, not AArch64. + There's no SVE vectors here, so just return the inferior + architecture. */ + if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) + return gdbarch; + + /* Only return it if the current vector length matches the one in the + tdep. */ + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + if (vq == tdep->vq) + return gdbarch; + + /* We reach here if the vector length for the thread is different from its + value at process start. Lookup gdbarch via info (potentially creating a + new one) by using a target description that corresponds to the new vq value + and the current architecture features. */ + + const struct target_desc *tdesc = gdbarch_target_desc (gdbarch); + aarch64_features features = aarch64_features_from_target_desc (tdesc); + features.vq = vq; + + struct gdbarch_info info; + info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64); + info.target_desc = aarch64_read_description (features); + return gdbarch_find_by_info (info); +} + /* Implement the stack_frame_destroyed_p gdbarch method. */ static int diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h index 55ccf2e777d2..80b9b3281a2d 100644 --- a/gdb/aarch64-tdep.h +++ b/gdb/aarch64-tdep.h @@ -143,4 +143,6 @@ void aarch64_displaced_step_fixup (struct gdbarch *gdbarch, bool aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch); +struct gdbarch *aarch64_update_gdbarch (struct gdbarch *gdbarch, uint64_t vq); + #endif /* aarch64-tdep.h */