From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by sourceware.org (Postfix) with ESMTPS id 371BC3858C00 for ; Thu, 19 Jan 2023 10:31:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 371BC3858C00 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30J9GReR002981; Thu, 19 Jan 2023 11:31:06 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=selector1; bh=sSsin/BNwez99gFV8juLY5GPKMA99y4wKezKIf82Om4=; b=mYviC2uoLzIYAoXP/UKYHndUfVQx2j3xLD28efw6NXpA8aGv2AKgdJwDCwlIWNMPEb17 fUYuQlxOGjRBEtt9qWghhbiTyhs6ezo8H8rR6pmdWzc4g/+5KeERJSussUN9I13tA3Ob RW3BnK3TbfGGK6t/g/z4YggbuoKkGE+AIhl2SEN1cypZpSsiWZOPcOLk/0+rKKYYKfOa 01KtzBkH0ca1PHN2QLtRROGM23DqzASJg6JNjH+DBkEEIni8wak7GPnvDrena5NwQG4N VG1uKq7oMZfRefI1giL9ZtSmq8WC3OmELruKp9h7TUOw7j0HV/Axk/xsN6QsiE7nQFtz Tg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3n7337gh7m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Jan 2023 11:31:06 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6D62C100040; Thu, 19 Jan 2023 11:31:05 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 649912122F4; Thu, 19 Jan 2023 11:31:05 +0100 (CET) Received: from jkgcxl0004.jkg.st.com (10.210.54.218) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.13; Thu, 19 Jan 2023 11:31:04 +0100 From: =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= To: CC: , , =?UTF-8?q?Torbj=C3=B6rn=20SVENSSON?= , Yvan Roux Subject: [PATCH v3 2/2] gdb/arm: Use new dwarf2 function cache Date: Thu, 19 Jan 2023 11:29:50 +0100 Message-ID: <20230119102948.3069226-2-torbjorn.svensson@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230119102948.3069226-1-torbjorn.svensson@foss.st.com> References: <20230119102948.3069226-1-torbjorn.svensson@foss.st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.210.54.218] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-19_07,2023-01-19_01,2022-06-22_01 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: v2 -> v3: No changes, just rebase. --- This patch resolves the performance issue reported in pr/29738 by caching the values for the stack pointers for the inner frame. By doing so, the impact can be reduced to checking the state and returning the appropriate value. Signed-off-by: Torbjörn SVENSSON Signed-off-by: Yvan Roux --- gdb/arm-tdep.c | 96 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 64 insertions(+), 32 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 51ec5236af1..be7219ca66e 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -3964,6 +3964,18 @@ struct frame_base arm_normal_base = { arm_normal_frame_base }; +struct arm_dwarf2_prev_register_cache +{ + /* Cached value of the coresponding stack pointer for the inner frame. */ + CORE_ADDR sp; + CORE_ADDR msp; + CORE_ADDR msp_s; + CORE_ADDR msp_ns; + CORE_ADDR psp; + CORE_ADDR psp_s; + CORE_ADDR psp_ns; +}; + static struct value * arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, int regnum) @@ -3972,6 +3984,48 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, arm_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); CORE_ADDR lr; ULONGEST cpsr; + struct arm_dwarf2_prev_register_cache *cache + = (struct arm_dwarf2_prev_register_cache *) dwarf2_frame_get_fn_data ( + this_frame, this_cache, arm_dwarf2_prev_register); + + if (!cache) + { + const unsigned int size = sizeof (struct arm_dwarf2_prev_register_cache); + cache = (struct arm_dwarf2_prev_register_cache *) + dwarf2_frame_allocate_fn_data (this_frame, this_cache, + arm_dwarf2_prev_register, size); + + if (tdep->have_sec_ext) + { + cache->sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + cache->msp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_s_regnum); + cache->msp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_ns_regnum); + cache->psp_s + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_s_regnum); + cache->psp_ns + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_ns_regnum); + } + else if (tdep->is_m) + { + cache->sp + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); + + cache->msp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_msp_regnum); + cache->psp + = get_frame_register_unsigned (this_frame, + tdep->m_profile_psp_regnum); + } + } if (regnum == ARM_PC_REGNUM) { @@ -4011,33 +4065,18 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, if (tdep->have_sec_ext) { - CORE_ADDR sp - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - CORE_ADDR msp_s - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_s_regnum); - CORE_ADDR msp_ns - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_ns_regnum); - CORE_ADDR psp_s - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_s_regnum); - CORE_ADDR psp_ns - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_ns_regnum); - bool is_msp = (regnum == tdep->m_profile_msp_regnum) - && (msp_s == sp || msp_ns == sp); + && (cache->msp_s == cache->sp || cache->msp_ns == cache->sp); bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum) - && (msp_s == sp); + && (cache->msp_s == cache->sp); bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum) - && (msp_ns == sp); + && (cache->msp_ns == cache->sp); bool is_psp = (regnum == tdep->m_profile_psp_regnum) - && (psp_s == sp || psp_ns == sp); + && (cache->psp_s == cache->sp || cache->psp_ns == cache->sp); bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum) - && (psp_s == sp); + && (cache->psp_s == cache->sp); bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum) - && (psp_ns == sp); + && (cache->psp_ns == cache->sp); override_with_sp_value = is_msp || is_msp_s || is_msp_ns || is_psp || is_psp_s || is_psp_ns; @@ -4045,17 +4084,10 @@ arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache, } else if (tdep->is_m) { - CORE_ADDR sp - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM); - CORE_ADDR msp - = get_frame_register_unsigned (this_frame, - tdep->m_profile_msp_regnum); - CORE_ADDR psp - = get_frame_register_unsigned (this_frame, - tdep->m_profile_psp_regnum); - - bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp == msp); - bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp == psp); + bool is_msp = (regnum == tdep->m_profile_msp_regnum) + && (cache->sp == cache->msp); + bool is_psp = (regnum == tdep->m_profile_psp_regnum) + && (cache->sp == cache->psp); override_with_sp_value = is_msp || is_psp; } -- 2.25.1