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Fri, 30 Jun 2023 13:46:31 +0000 From: Luis Machado To: Subject: [PATCH v3 01/16] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Date: Fri, 30 Jun 2023 14:46:01 +0100 Message-ID: <20230630134616.1238105-2-luis.machado@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230630134616.1238105-1-luis.machado@arm.com> References: <20230630134616.1238105-1-luis.machado@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT053:EE_|AS8PR08MB8566:EE_|DBAEUR03FT057:EE_|AS4PR08MB7807:EE_ X-MS-Office365-Filtering-Correlation-Id: 244030af-ed29-4c0c-3bba-08db79706f1f x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: m8qTBnzEAkQHbaTJDf4unBoAWE6bzGRTEV7r9NBRK05pZvuv0JHrNzEH+kGhUiyJW73dVVudoRHPw5/6HZ/sCTw7epEqY8A41lQf3diZlYFGF2v5fBqYOi3SInoxjjTFyYpqJw/KekejUj6SrASgpY74O3VjIh1K/wQOcpz5xP7WNpcP4Kra1tojZejuxkdd6Cl6ht69HhGfCFH6gyxqzSCLXOByWauDTiPapH3waPN3HlNIgh4OW/1PHPLJgUBtFhUGM1BWdAGv5w1EY3ThDNXkhtx1CB9Q+kfOruM9xUb8lvEnEMWe54yGRVfHRcUjP4rO5l2eKM9raHg+0/b770A4NQbFdFlC96bLgHHCpn687h+iAsu/3gicuFEiYoVSqI2q3AHpADPrq9+T0b3YSE7bFxy/HiHMrrwWPzGxi70VeSLZ2GTXqpZHzvTJRfu6rZCoefUW8VYcLkphdmD5Cof8FP2OhV4UvURn9k9lQO3CnAfJIb+VCArBR9GMDbx9QQXlvEmZ1GMfNTrcYN5JlWoh67k3lTtF2wlIkyid7sQtCHz8iuEcWksMEDVZK5WG0PgLE1G9OR8E9pA9IaINAJ0C6hj8vPFzcU74usI3Mp5NWKRhc7VJbau9gYG6zVZEhYVpn1lvEFFJHFmKZhmlsMUWF6kDQymNW9fV6c5rU7bkeSqV9n89TnD2s5+8caI4CGifUjAf/iPqJJlFhFsivfR1DNanyVmvLtTSG6SfmsbOSZgTYQ1869LScfeeX6lBxdxBP7OFPgJ94FxCRtXziA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199021)(40470700004)(46966006)(36840700001)(44832011)(5660300002)(6916009)(478600001)(70206006)(316002)(36756003)(70586007)(8936002)(8676002)(2906002)(6666004)(26005)(40460700003)(36860700001)(41300700001)(82310400005)(7696005)(186003)(40480700001)(426003)(336012)(47076005)(1076003)(356005)(86362001)(82740400003)(81166007)(83380400001)(2616005)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 13:46:41.0516 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 244030af-ed29-4c0c-3bba-08db79706f1f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT057.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB7807 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: I noticed we don't handle register reads/writes in the best way for native AArch64 Linux. Some registers are fetched/stored even if upper level code told us to fetch a particular register number. Fix this by being more strict about which registers we touch when reading/writing them in the native AArch64 Linux layer. There should be no user-visible changes due to this patch. Regression-tested on aarch64-linux Ubuntu 22.04/20.04. --- gdb/aarch64-linux-nat.c | 60 ++++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index ecb2eeb9540..62656a7347b 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -504,6 +504,7 @@ aarch64_fetch_registers (struct regcache *regcache, int regno) aarch64_gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + /* Do we need to fetch all registers? */ if (regno == -1) { fetch_gregs_from_thread (regcache); @@ -521,28 +522,28 @@ aarch64_fetch_registers (struct regcache *regcache, int regno) if (tdep->has_tls ()) fetch_tlsregs_from_thread (regcache); } + /* General purpose register? */ else if (regno < AARCH64_V0_REGNUM) fetch_gregs_from_thread (regcache); - else if (tdep->has_sve ()) + /* SVE register? */ + else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM) fetch_sveregs_from_thread (regcache); - else + /* FPSIMD register? */ + else if (regno < AARCH64_FPCR_REGNUM) fetch_fpregs_from_thread (regcache); - - if (tdep->has_pauth ()) - { - if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) - || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) - fetch_pauth_masks_from_thread (regcache); - } - - /* Fetch individual MTE registers. */ - if (tdep->has_mte () - && (regno == tdep->mte_reg_base)) + /* PAuth register? */ + else if (tdep->has_pauth () + && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) + || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))) + fetch_pauth_masks_from_thread (regcache); + /* MTE register? */ + else if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) fetch_mteregs_from_thread (regcache); - - if (tdep->has_tls () - && regno >= tdep->tls_regnum_base - && regno < tdep->tls_regnum_base + tdep->tls_register_count) + /* TLS register? */ + else if (tdep->has_tls () + && regno >= tdep->tls_regnum_base + && regno < tdep->tls_regnum_base + tdep->tls_register_count) fetch_tlsregs_from_thread (regcache); } @@ -592,6 +593,7 @@ aarch64_store_registers (struct regcache *regcache, int regno) aarch64_gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); + /* Do we need to store all registers? */ if (regno == -1) { store_gregs_to_thread (regcache); @@ -606,22 +608,26 @@ aarch64_store_registers (struct regcache *regcache, int regno) if (tdep->has_tls ()) store_tlsregs_to_thread (regcache); } + /* General purpose register? */ else if (regno < AARCH64_V0_REGNUM) store_gregs_to_thread (regcache); - else if (tdep->has_sve ()) + /* SVE register? */ + else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM) store_sveregs_to_thread (regcache); - else + /* FPSIMD register? */ + else if (regno < AARCH64_FPCR_REGNUM) store_fpregs_to_thread (regcache); - - /* Store MTE registers. */ - if (tdep->has_mte () - && (regno == tdep->mte_reg_base)) + /* MTE register? */ + else if (tdep->has_mte () + && (regno == tdep->mte_reg_base)) store_mteregs_to_thread (regcache); - - if (tdep->has_tls () - && regno >= tdep->tls_regnum_base - && regno < tdep->tls_regnum_base + tdep->tls_register_count) + /* TLS register? */ + else if (tdep->has_tls () + && regno >= tdep->tls_regnum_base + && regno < tdep->tls_regnum_base + tdep->tls_register_count) store_tlsregs_to_thread (regcache); + + /* PAuth registers are read-only. */ } /* A version of the "store_registers" target_ops method used when running -- 2.25.1