From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2053.outbound.protection.outlook.com [40.107.21.53]) by sourceware.org (Postfix) with ESMTPS id 139093858C2A for ; Tue, 22 Aug 2023 11:21:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 139093858C2A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zgzEUWO2tDKaJcw+6ydb2Pa8lNEN1bNcASzWrUi5FYU=; b=lcPsntLBZ26VbIibUqf0gxgXpER0OdHJdao2SLZCaNvVazjx9QhttEvU1o8SL7aXcoTEihaZQ06m71FkmfFL4k3HyPheda/7rWnngVqRxSSvnl7zb4i/orOIyrH/PD0XaZdOEZ59UXacPdu4ZAxLx2y5vtmYYmPQghJTtlRzfFs= Received: from DB7PR03CA0089.eurprd03.prod.outlook.com (2603:10a6:10:72::30) by AS8PR08MB7944.eurprd08.prod.outlook.com (2603:10a6:20b:541::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6699.24; Tue, 22 Aug 2023 11:21:47 +0000 Received: from DBAEUR03FT016.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:72:cafe::8) by DB7PR03CA0089.outlook.office365.com (2603:10a6:10:72::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6699.20 via Frontend Transport; Tue, 22 Aug 2023 11:21:46 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT016.mail.protection.outlook.com (100.127.142.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6723.15 via Frontend Transport; Tue, 22 Aug 2023 11:21:46 +0000 Received: ("Tessian outbound 169aaa6bf2b7:v175"); Tue, 22 Aug 2023 11:21:46 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 74e28d691b0c1170 X-CR-MTA-TID: 64aa7808 Received: from a8857f546e4e.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 03FF0D74-1175-42E7-9DFF-05F05A4C86C2.1; Tue, 22 Aug 2023 11:21:40 +0000 Received: from EUR02-DB5-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id a8857f546e4e.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 22 Aug 2023 11:21:40 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BKyBmvOPT2fhCzNwQZwsAKCMN2rnpm0tnD2STiEadjjHoKJBVeZ9y4WJGEWBmOb/Q1vHUCy94DyHD24rup1gG7Ttnfs8Jbz2YpWEDCwIIg08ZTXWgG4gNafE9Fn0yjnTANZhcsQJmg3AiM2yaeGvxgrVFt8aor8rcTPCmomXhcPqv32YYduERWo8vjRSjIGUwSTezZDCLu44dfjfdUoGTv6tNCFFmRSHhoEDNirJvvRNmJPwTGmD7IYhY+g+14jBoeXRbFfhX004M87v4Q7pDexAAh8YGA6UhswEzKDfVaQ/s46KM/auYgNpa8vBScWztUnMc5yzVhJ9PCyGdwV3MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zgzEUWO2tDKaJcw+6ydb2Pa8lNEN1bNcASzWrUi5FYU=; b=jhyobSz/ybCOPSUOKo+rsKqoYq8iPJmii+U+zkCUu4Azx7IP9AACiWwP9+7fi2TqMy6rRC+gVMS1hH4fuKLvclKZ9tvY/nVArg4ypwhUzdCqv/AIG4mE0Ztd6SBQNyVTa5fRenaotOYRxWoPZ8pjQB7eKPSmULnFle0QuNQJ8eMHPNNBUb9c2UrieivEKaiTFC+RRyldIQLH0qtneXlsuzjUvlYdlZ1Yku1AOxcylcCE34plZhD7Y3H6x2fHdTJarCxnFpelqni+EuhFJk2aOgHijSogx9f957xQK8Kmean3iTrIWIxgeVoNCtaslmf2GK/2I92o9eh+GnZ65JNEMg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zgzEUWO2tDKaJcw+6ydb2Pa8lNEN1bNcASzWrUi5FYU=; b=lcPsntLBZ26VbIibUqf0gxgXpER0OdHJdao2SLZCaNvVazjx9QhttEvU1o8SL7aXcoTEihaZQ06m71FkmfFL4k3HyPheda/7rWnngVqRxSSvnl7zb4i/orOIyrH/PD0XaZdOEZ59UXacPdu4ZAxLx2y5vtmYYmPQghJTtlRzfFs= Received: from AS9PR07CA0023.eurprd07.prod.outlook.com (2603:10a6:20b:46c::22) by AS8PR08MB6069.eurprd08.prod.outlook.com (2603:10a6:20b:29c::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6699.24; Tue, 22 Aug 2023 11:21:38 +0000 Received: from AM7EUR03FT027.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:46c:cafe::8e) by AS9PR07CA0023.outlook.office365.com (2603:10a6:20b:46c::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6699.15 via Frontend Transport; Tue, 22 Aug 2023 11:21:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by AM7EUR03FT027.mail.protection.outlook.com (100.127.140.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6723.15 via Frontend Transport; Tue, 22 Aug 2023 11:21:38 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 22 Aug 2023 11:21:37 +0000 Received: from e129171.cambridge.arm.com (10.1.34.58) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Tue, 22 Aug 2023 11:21:37 +0000 From: Luis Machado To: CC: Subject: [PATCH v4 08/16] [gdb/aarch64] sve: Fix signal frame z/v register restore Date: Tue, 22 Aug 2023 12:21:22 +0100 Message-ID: <20230822112130.1513216-9-luis.machado@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230822112130.1513216-1-luis.machado@arm.com> References: <20230822112130.1513216-1-luis.machado@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT027:EE_|AS8PR08MB6069:EE_|DBAEUR03FT016:EE_|AS8PR08MB7944:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f03fe29-2c44-4e4f-13bf-08dba301f8d2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: OMjwzi4+57ohuPiUDnhmDlNjuZK7fCXQ0aAbkI1l0sbbjrdOdcNdyKia1vBLNuPM7SEosAi2IbfDW7NPArRUtZX+FQiaDn6h92Ukpz8pGhz4MZd2kCLTt48h/gTcmV3hVqqPyLV18c30RSPmDj4HOq70yexEVqlIeqtt/04maGVZ+ZzH9Xb+JTErgGxm4tgwjw8rRmQ3ktK/de8TCf8XsadXlDbxgyeoN4GIepLRPx2mG/+RbjyneRonu3U74S4ThjMtwk4T1fnp9DYK1pFi/evrlVqiiohMWjE9KtTq6myWgvKvuOkOkodjEYNKEK9s+1ho9hej/B2veEG9HRrITCZLnOoWCPDe4TJ4V1dQaiS4dRdYAtY04l5KCvC5dFUhJg/ZSZqtEugKiUWupToZbRQuPGlHNBvSYM70m2z7BXtb1avN3IR+qAMknPFOu2yggTpGtkrPNy1nj6iMrZCn6qumvH9kU8iHM+POUBhnTSnrL8uWrInBEWHVuA/c2ZN2ch6S4hlNXVra+0vC4dRN+ks6bJXFHwFjDlEYSYflKeloAhKFfhrO2kX2+HZngYX+tYWOlFoUCxztTJN4vlEvl0c33SHiM2oVSmeX0tnZkf2+EgF3rv7qEDcdVv/l20BHFVEbMJPuDCTA0Uda8JLYl5PKscMQoBylhFXUpzYWzUv/B12RWUWGJ5dagJ3JzmreK4byBVk4IU+Gk8GkZCJa8VLAYw0N/H/IzW1sd2KfU2vYBgMPpfnQC2T8D6l+oWEGfV9j68S7GEGpYr02cgH7kg== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(396003)(39860400002)(346002)(1800799009)(186009)(451199024)(82310400011)(36840700001)(40470700004)(46966006)(6916009)(316002)(70586007)(70206006)(8676002)(8936002)(2616005)(4326008)(36756003)(40460700003)(41300700001)(1076003)(82740400003)(356005)(81166007)(478600001)(6666004)(40480700001)(83380400001)(2906002)(86362001)(47076005)(7696005)(36860700001)(336012)(44832011)(426003)(5660300002)(26005)(36900700001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6069 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 08b7e1dc-443e-4684-f93f-08dba301f41c X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FVgOonY1hwV9pOQY+SbbXfkAzIQqRRsZFdHcXo+9Qh3VhhIt+tgNIYMy5uegz6jaWuqpQaMU98u9gsCNuYosVc9udKkwnr6t5gsSvSBwalUAHmzL4gWhNZsxz4yeeO4kcf68zgV3L87zQ6xCtyhRBQ0i5A01u2/Kp1dcV5IgI9QdA0PDmK/laAW4uKTfPJhwc7C0MaWKQaqTLb6TJkWzmZjv5pDFdLwoJQWHf8HQwNYwizpvDwDXge6NG6G2uUlsmnj1ToshINVK7OaM+75+tyhH1+R29tEd9dQ9L8NDww67VSRJvpsyc1o8aRpIzhzLYa5RmzzEV0agTm9NT67V8ilaCCK+2hZ6nTyreYF6ixrW4AnW69q7jOylv930MxB/ZRc7UKF4geUfXIOrbI0aF1UYIbQqFR8fykWTyKTM4TtISR/OttwOd3AohN5uoqyXrgQs603VvHPJQBXnKTPVIhiIZG2pGtPCRKutcT8GSdQyTzHF72orU9Wb4FQf6xM9xIfhpI7n26atJEq7O4QTJ/Cwxk2EH9vDloe+76wnthC4xNrgXaXAdsFWcBr9qENCA4xtL8E8GKZiCMg7cLIXvJS5NtCoriy2n9ddEeqdf2eOaimZHWZMQwioxQGv8sx8nBa2t3dRNQkZUreZfVScGmVUc+Noe9ryvwPz1f6JdtqF6AyoooD2NW5iKMOdf+GGusy0iOLIX1nY40W721ooLfTqxMsaQRpiCtUpX1R5Wp5rg05Ex4e3/2MVepDtYrb9 X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(396003)(39860400002)(346002)(1800799009)(186009)(451199024)(82310400011)(36840700001)(40470700004)(46966006)(6916009)(316002)(70586007)(70206006)(8676002)(8936002)(2616005)(107886003)(4326008)(36756003)(40460700003)(41300700001)(1076003)(82740400003)(81166007)(478600001)(6666004)(40480700001)(83380400001)(2906002)(86362001)(47076005)(7696005)(36860700001)(336012)(44832011)(426003)(5660300002)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 11:21:46.7712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f03fe29-2c44-4e4f-13bf-08dba301f8d2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB7944 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: While doing some SME work, I ran into the situation where the Z register contents restored from a signal frame are incorrect if the signal frame only contains fpsimd state and no sve state. This happens because we only restore the v register values in that case, and don't do anything for the z registers. Fix this by initializing the z registers to 0 and then copying over the overlapping part of the v registers to the z registers. While at it, refactor the code a bit to simplify it and make it smaller. Regression-tested on aarch64-linux Ubuntu 22.04/20.04. --- gdb/aarch64-linux-tdep.c | 107 +++++++++++++++++++++++---------------- 1 file changed, 62 insertions(+), 45 deletions(-) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index b183a3c9a38..bdd5cb05c10 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -196,14 +196,13 @@ read_aarch64_ctx (CORE_ADDR ctx_addr, enum bfd_endian byte_order, /* Given CACHE, use the trad_frame* functions to restore the FPSIMD registers from a signal frame. - VREG_NUM is the number of the V register being restored, OFFSET is the - address containing the register value, BYTE_ORDER is the endianness and - HAS_SVE tells us if we have a valid SVE context or not. */ + FPSIMD_CONTEXT is the address of the signal frame context containing FPSIMD + data. */ static void -aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, - int vreg_num, CORE_ADDR offset, - enum bfd_endian byte_order, bool has_sve) +aarch64_linux_restore_vregs (struct gdbarch *gdbarch, + struct trad_frame_cache *cache, + CORE_ADDR fpsimd_context) { /* WARNING: SIMD state is laid out in memory in target-endian format. @@ -215,11 +214,22 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, 2 - If the target is little endian, then SIMD state is little endian, so no byteswap is needed. */ - if (byte_order == BFD_ENDIAN_BIG) + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + int num_regs = gdbarch_num_regs (gdbarch); + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + for (int i = 0; i < 32; i++) { + CORE_ADDR offset = (fpsimd_context + AARCH64_FPSIMD_V0_OFFSET + + (i * AARCH64_FPSIMD_VREG_SIZE)); + gdb_byte buf[V_REGISTER_SIZE]; - if (target_read_memory (offset, buf, V_REGISTER_SIZE) != 0) + /* Read the contents of the V register. */ + if (target_read_memory (offset, buf, V_REGISTER_SIZE)) + error (_("Failed to read fpsimd register from signal context.")); + + if (byte_order == BFD_ENDIAN_BIG) { size_t size = V_REGISTER_SIZE/2; @@ -234,50 +244,66 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, store_unsigned_integer (buf + size , size, BFD_ENDIAN_LITTLE, u64); /* Now we can store the correct bytes for the V register. */ - trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + vreg_num, + trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + i, {buf, V_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_Q0_REGNUM - + vreg_num, {buf, Q_REGISTER_SIZE}); + + i, {buf, Q_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_D0_REGNUM - + vreg_num, {buf, D_REGISTER_SIZE}); + + i, {buf, D_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_S0_REGNUM - + vreg_num, {buf, S_REGISTER_SIZE}); + + i, {buf, S_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_H0_REGNUM - + vreg_num, {buf, H_REGISTER_SIZE}); + + i, {buf, H_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_B0_REGNUM - + vreg_num, {buf, B_REGISTER_SIZE}); + + i, {buf, B_REGISTER_SIZE}); - if (has_sve) + if (tdep->has_sve ()) trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_SVE_V0_REGNUM - + vreg_num, {buf, V_REGISTER_SIZE}); + + i, {buf, V_REGISTER_SIZE}); } - return; - } + else + { + /* Little endian, just point at the address containing the register + value. */ + trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + i, offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + i, + offset); - /* Little endian, just point at the address containing the register - value. */ - trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + vreg_num, offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + vreg_num, - offset); - - if (has_sve) - trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM - + vreg_num, offset); + if (tdep->has_sve ()) + trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM + + i, offset); + } + if (tdep->has_sve ()) + { + /* If SVE is supported for this target, zero out the Z + registers then copy the first 16 bytes of each of the V + registers to the associated Z register. Otherwise the Z + registers will contain uninitialized data. */ + std::vector z_buffer (tdep->vq * 16); + + /* We have already handled the endianness swap above, so we don't need + to worry about it here. */ + memcpy (z_buffer.data (), buf, V_REGISTER_SIZE); + trad_frame_set_reg_value_bytes (cache, + AARCH64_SVE_Z0_REGNUM + i, + z_buffer); + } + } } /* Implement the "init" method of struct tramp_frame. */ @@ -432,16 +458,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self, /* If there was no SVE section then set up the V registers. */ if (sve_regs == 0) - { - for (int i = 0; i < 32; i++) - { - CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET - + (i * AARCH64_FPSIMD_VREG_SIZE)); - - aarch64_linux_restore_vreg (this_cache, num_regs, i, offset, - byte_order, tdep->has_sve ()); - } - } + aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd); } trad_frame_set_id (this_cache, frame_id_build (sp, func)); -- 2.25.1