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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2023 11:21:57.5823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51ea05cd-26ba-4a7a-a3d6-08dba301ff4f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT026.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9339 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: v2: - Updated to use the new naming/organization of the test support files. -- Reusing the SME tests, this patch introduces additional tests to exercise reading/writing ZT0, availability of the register set, signal context reading for ZT0 and also core file generation. --- gdb/testsuite/gdb.arch/aarch64-sme-core.c | 32 ++++++++++- .../gdb.arch/aarch64-sme-core.exp.tcl | 2 +- .../aarch64-sme-regs-available.exp.tcl | 17 ++++++ .../gdb.arch/aarch64-sme-regs-sigframe.c | 32 ++++++++++- .../aarch64-sme-regs-sigframe.exp.tcl | 13 ++++- .../aarch64-sme-regs-unavailable.exp.tcl | 12 +++++ gdb/testsuite/gdb.arch/aarch64-sme-sanity.c | 32 ++++++++++- gdb/testsuite/lib/aarch64-scalable.exp | 44 +++++++++++++++ gdb/testsuite/lib/aarch64.exp | 53 +++++++++++++++++++ 9 files changed, 229 insertions(+), 8 deletions(-) diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core.c b/gdb/testsuite/gdb.arch/aarch64-sme-core.c index d71d18ebd3b..fcb14670e0d 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-core.c +++ b/gdb/testsuite/gdb.arch/aarch64-sme-core.c @@ -35,6 +35,11 @@ #define HWCAP2_SME (1 << 23) #endif +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + #ifndef PR_SVE_SET_VL #define PR_SVE_SET_VL 50 #define PR_SVE_GET_VL 51 @@ -145,6 +150,27 @@ initialize_za_state () __asm __volatile ("bne loop"); } +static void +initialize_zt_state () +{ + unsigned long hwcap2 = getauxval (AT_HWCAP2); + + if (!(hwcap2 & HWCAP2_SME2) && !(hwcap2 & HWCAP2_SME2P1)) + return; + + char buffer[64]; + + for (int i = 0; i < 64; i++) + buffer[i] = 0xff; + + __asm __volatile ("mov x0, %0\n\t" \ + : : "r" (buffer)); + + /* Initialize ZT0. */ + /* ldr zt0, x0 */ + __asm __volatile (".word 0xe11f8000"); +} + static void initialize_tpidr2 () { @@ -273,8 +299,8 @@ static int set_svl_size (int new_svl) 0 - FPSIMD 1 - SVE 2 - SSVE - 3 - ZA - 4 - ZA and SSVE. */ + 3 - ZA (+ SME2 ZT0) + 4 - ZA and SSVE (+ SME2 ZT0). */ void enable_states (int state) { @@ -295,6 +321,7 @@ void enable_states (int state) { enable_za (); initialize_za_state (); + initialize_zt_state (); } else if (state == 4) { @@ -302,6 +329,7 @@ void enable_states (int state) enable_sm (); initialize_sve_state (); initialize_za_state (); + initialize_zt_state (); } return; diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl index 35e3d981e10..d387dd11a0e 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-core.exp.tcl @@ -13,7 +13,7 @@ # You should have received a copy of the GNU General Public License # along with this program. If not, see . # -# Exercise core file reading/writing in the presence of SME support. +# Exercise core file reading/writing in the presence of SME and SME2 support. # This test exercises GDB's dumping/loading capability for Linux # Kernel core files and for gcore core files. diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl index ad3f0ee1dcc..74aeeb46684 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-available.exp.tcl @@ -14,6 +14,7 @@ # along with this program. If not, see . # Exercise reading/writing ZA registers when there is ZA state. +# Exercise reading/writing to ZT0 when there is ZA state available. load_lib aarch64-scalable.exp @@ -119,6 +120,22 @@ proc check_regs { mode vl svl } { set last_slice [expr ($last_slice / 2)] set num_elements [expr $num_elements / 2] } + + # Exercise reading/writing from/to SME2 registers. + if [is_sme2_available] { + # The target supports SME2. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + + # Initially, when ZA is activated, ZT0 will be all zeroes. + set zt_pattern [string_to_regexp [1d_array_value_pattern 0 $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" "validate zeroed zt0" + + # Validate that writing to ZT0 does the right thing. + initialize_1d_array "\$zt0" 255 $zt_size + set zt_pattern [string_to_regexp [1d_array_value_pattern 255 $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" "read back from zt0" + } } # diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c index 9bc3e9c16fc..8f0827cf83a 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.c @@ -34,6 +34,11 @@ #define HWCAP2_SME (1 << 23) #endif +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + #ifndef PR_SVE_SET_VL #define PR_SVE_SET_VL 50 #define PR_SVE_GET_VL 51 @@ -152,6 +157,27 @@ initialize_za_state () __asm __volatile ("bne loop"); } +static void +initialize_zt_state () +{ + unsigned long hwcap2 = getauxval (AT_HWCAP2); + + if (!(hwcap2 & HWCAP2_SME2) && !(hwcap2 & HWCAP2_SME2P1)) + return; + + char buffer[64]; + + for (int i = 0; i < 64; i++) + buffer[i] = 0xff; + + __asm __volatile ("mov x0, %0\n\t" \ + : : "r" (buffer)); + + /* Initialize ZT0. */ + /* ldr zt0, x0 */ + __asm __volatile (".word 0xe11f8000"); +} + static void initialize_sve_state () { @@ -271,8 +297,8 @@ static int set_svl_size (int new_svl) 0 - FPSIMD 1 - SVE 2 - SSVE - 3 - ZA - 4 - ZA and SSVE. */ + 3 - ZA (+ SME2 ZT0) + 4 - ZA and SSVE (+ SME2 ZT0). */ void enable_states (int state) { @@ -293,6 +319,7 @@ void enable_states (int state) { enable_za (); initialize_za_state (); + initialize_zt_state (); } else if (state == 4) { @@ -300,6 +327,7 @@ void enable_states (int state) enable_sm (); initialize_sve_state (); initialize_za_state (); + initialize_zt_state (); } return; diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl index c2962417f70..30c7adb4db6 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-sigframe.exp.tcl @@ -90,10 +90,12 @@ proc test_sme_registers_sigframe { id_start id_end } { # Check the value of SVCR. gdb_test "print \$svcr" [get_svcr_value $state] "svcr before signal" - # Handle SME ZA initialization and state. + # Handle SME ZA and SME2 initialization and state. set byte 0 + set sme2_byte 0 if { $state == "za" || $state == "za_ssve" } { set byte 170 + set sme2_byte 255 } # Set the expected ZA pattern. @@ -160,6 +162,15 @@ proc test_sme_registers_sigframe { id_start id_end } { # Check the value of TPIDR2 in the signal frame. gdb_test "print/x \$tpidr2" " = 0x102030405060708" "tpidr2 contents from signal frame" + + # Check the value of SME2 ZT0 in the signal frame. + if [is_sme2_available] { + # The target supports SME2. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + set zt_pattern [string_to_regexp [1d_array_value_pattern $sme2_byte $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" "zt contents from signal frame" + } } } } diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl index 41d65c523f3..402996826b7 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl +++ b/gdb/testsuite/gdb.arch/aarch64-sme-regs-unavailable.exp.tcl @@ -17,6 +17,7 @@ # - Printing ZA registers when there is no ZA state. # - Setting values of ZA registers when there is no ZA state. # - Validating ZA state is activated when we write to ZA registers. +# - Validate that reading ZT0 without an active ZA state works as expected. load_lib aarch64-scalable.exp @@ -89,6 +90,17 @@ proc_with_prefix check_regs { vl svl } { set expected_size [expr $expected_size / 2] set elements [expr ($elements / 2)] } + + # Exercise reading from SME2 registers. + if [is_sme2_available] { + # The target supports SME2. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + + # If ZA is not active, ZT0 will always be zero. + set zt_pattern [string_to_regexp [1d_array_value_pattern 0 $zt_size]] + gdb_test "print \$zt0" " = $zt_pattern" + } } # diff --git a/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c index 694de0626d2..71b46b17855 100644 --- a/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c +++ b/gdb/testsuite/gdb.arch/aarch64-sme-sanity.c @@ -33,6 +33,11 @@ #define HWCAP2_SME (1 << 23) #endif +#ifndef HWCAP2_SME2 +#define HWCAP2_SME2 (1UL << 37) +#define HWCAP2_SME2P1 (1UL << 38) +#endif + static void enable_za () { @@ -131,6 +136,27 @@ initialize_za_state () __asm __volatile ("bne loop"); } +static void +initialize_zt_state () +{ + unsigned long hwcap2 = getauxval (AT_HWCAP2); + + if (!(hwcap2 & HWCAP2_SME2) && !(hwcap2 & HWCAP2_SME2P1)) + return; + + char buffer[64]; + + for (int i = 0; i < 64; i++) + buffer[i] = 0xff; + + __asm __volatile ("mov x0, %0\n\t" \ + : : "r" (buffer)); + + /* Initialize ZT0. */ + /* ldr zt0, x0 */ + __asm __volatile (".word 0xe11f8000"); +} + static void initialize_sve_state () { @@ -190,8 +216,8 @@ initialize_sve_state () 0 - FPSIMD 1 - SVE 2 - SSVE - 3 - ZA - 4 - ZA and SSVE. */ + 3 - ZA (+ SME2 ZT0) + 4 - ZA and SSVE (+ SME2 ZT0). */ void enable_states (int state) { @@ -212,6 +238,7 @@ void enable_states (int state) { enable_za (); initialize_za_state (); + initialize_zt_state (); } else if (state == 4) { @@ -219,6 +246,7 @@ void enable_states (int state) enable_sm (); initialize_sve_state (); initialize_za_state (); + initialize_zt_state (); } return; diff --git a/gdb/testsuite/lib/aarch64-scalable.exp b/gdb/testsuite/lib/aarch64-scalable.exp index 5512fcb9d1c..f77daec2308 100644 --- a/gdb/testsuite/lib/aarch64-scalable.exp +++ b/gdb/testsuite/lib/aarch64-scalable.exp @@ -186,6 +186,18 @@ proc check_sme_regs { byte state svl } { gdb_test "print \$za" $za_pattern } +# +# Validate the values of the SME2 registers. +# +proc check_sme2_regs { byte } { + # The size of the ZT registers should always be fixed to 64 bytes. + set zt_size 64 + gdb_test "print sizeof \$zt0" " = $zt_size" + # Check that we have the expected pattern of bytes for the ZT registers. + set zt_pattern [string_to_regexp [1d_array_value_pattern $byte $zt_size]] + gdb_test "print \$zt0" $zt_pattern +} + # # With register STATE, vector length VL and streaming vector length SVL, # run some register state checks to make sure the values are the expected @@ -200,6 +212,9 @@ proc check_state { state vl svl } { # # The SME (ZA) register is initialized with a value of 0xaa (170) for # each byte. + # + # The SME2 (ZT) registers are initialized with a value of 0xff (255) for + # each byte. # Check VG to make sure it is correct set expected_vg [expr $vl / 8] @@ -234,6 +249,35 @@ proc check_state { state vl svl } { check_sve_regs $sve_byte $state $vl $svl # Check SME registers check_sme_regs 170 $state $svl + + # Check SME2 registers + if [is_sme2_available] { + # The SME2 ZT0 register will always be zero, except when ZA is active. + set sme2_byte 0 + if {$state == "za" || $state == "za_ssve"} { + set sme2_byte 255 + } + + # The target supports SME2, so check the ZT register values. + check_sme2_regs $sme2_byte + } } +# +# Return 1 if SME2 is available (meaning the ZT0 register exists). +# Return 0 otherwise. +# +proc is_sme2_available { } { + # Does the ZT0 register exist? + gdb_test_multiple "print \$zt0" "" { + -re " = void.*${::gdb_prompt} $" { + # SME2 is not available. + return 0 + } + -re " = {.*}\r\n${::gdb_prompt} $" { + # SME2 is available. + return 1 + } + } +} diff --git a/gdb/testsuite/lib/aarch64.exp b/gdb/testsuite/lib/aarch64.exp index cd43a4c4f77..40bba861b5f 100644 --- a/gdb/testsuite/lib/aarch64.exp +++ b/gdb/testsuite/lib/aarch64.exp @@ -151,3 +151,56 @@ proc check_fpsimd_regs { byte state vl svl} { gdb_test "print $register_name" $fpsimd_pattern } } + +# +# Validate the values of the SVE registers. +# +proc check_sve_regs { byte state vl svl } { + + # If streaming mode is enabled, the vector length is the streaming + # vector length. + set z_pattern "" + set z_size 0 + if {$state == "ssve" || $state == "za_ssve"} { + set z_pattern [string_to_regexp [1d_array_value_pattern $byte $svl]] + set z_size $svl + } else { + set z_size $vl + + if {$state == "fpsimd" || $state == "za"} { + # If there is no SVE/SSVE state, the contents of the Z/P/FFR registers + # are zero. + if {$vl == 16} { + set z_pattern [string_to_regexp [1d_array_value_pattern $byte $vl]] + } else { + set z_repeats [expr $vl - 16] + set z_pattern [string_to_regexp "{$byte , 0 }"] + } + } else { + set z_pattern [string_to_regexp [1d_array_value_pattern $byte $vl]] + } + } + set p_size [expr $z_size / 8] + + # If there is no SVE/SSVE state, the contents of the Z/P/FFR registers + # are zero. + set p_byte $byte + if {$state == "fpsimd" || $state == "za"} { + set p_byte 0 + } + set p_pattern [string_to_regexp [1d_array_value_pattern $p_byte $p_size]] + + for {set number 0} {$number < 32} {incr number} { + set register_name "\$z${number}\.b\.u" + gdb_test "print sizeof $register_name" " = $z_size" + gdb_test "print $register_name" $z_pattern + } + + for {set number 0} {$number < 16} {incr number} { + set register_name "\$p${number}" + gdb_test "print sizeof $register_name" " = $p_size" + gdb_test "print $register_name" $p_pattern + } + + gdb_test "print \$ffr" $p_pattern +} -- 2.25.1