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Wed, 13 Sep 2023 10:18:29 +0000 From: Luis Machado To: CC: , Subject: [PATCH v6 09/17] [gdb/aarch64] sve: Fix signal frame z/v register restore Date: Wed, 13 Sep 2023 11:18:07 +0100 Message-ID: <20230913101815.178154-10-luis.machado@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230913101815.178154-1-luis.machado@arm.com> References: <20230913101815.178154-1-luis.machado@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: AM7EUR03FT034:EE_|AS8PR08MB9042:EE_|DBAEUR03FT047:EE_|AS8PR08MB6310:EE_ X-MS-Office365-Filtering-Correlation-Id: 51de9115-877b-4fee-bf45-08dbb442ccc7 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: MObGxItvuv6TZxY8t852t8c8miqqQaph8zXMn/THgQRyxy0KGxxQadn1wfn0uVMfVzzoJFbQdWJaql1vnrFUFInERGxmAPpOw7sIdM4OOkcj35+KJx01f2L8Z2XMkdc84f53MymH5waOQgbSIp6Qivh7PM36zRhYWIXpnK9u0T//dpjhu+k1vnCYwy7LvX27J4wugiWjT8EydxoDWk37/FZ7kgPzgsSqaaKSmf977Q/fpDgxvTtHyunCtdMIayn8E6UL8uv6S5jRvSrRR6VsrgIMrAs0PK1o9APuZ7+vZZ55ZfjH4NQlKcOEmg2+GbWWN/Sb73X6oBLrkwrqq28s9ZSVds3BuqQ+BfENMsMiWa7LrVH9NARo3XkdHSkM06xe95hGF0hok49J5SOCIKBZv3Dlm5pPKzfHW4ELafqG+9AQQ4qrV49qQY4F2Y2Vz+dVO2Uhld9mYWH08utwjYxebPtBIyHniIgFx8FKUrf78FueNZXqkIjg94FEurHCgfjbdZfltsM0ipg2rnfMob4vLwK45jfwrfVHWnE/dJxiyXoOk1bWPI40axjNNagCY7zjKVeApj2YKrgtXz4aFbtskO/tH/BDbYBo16rnDKcbJDaCfT0n1glBBxzusgFaHy3be/j6WH/avCRG0TrdCCbdSm3dCrX5n/Dh+giQwhKi/n4PnrUzr5bd9M8sQwQ6xVcW0lHOTpWs1CNks6Sbmgv64qFbU+2giL8RRVQn+zp6WwJ/yPLsVTg6b6bfL7iYaCr5/kLLHfBkhCy7NFIBCTtOcQ== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(376002)(346002)(136003)(451199024)(186009)(1800799009)(82310400011)(46966006)(36840700001)(40470700004)(36756003)(86362001)(356005)(1076003)(81166007)(478600001)(40480700001)(70586007)(426003)(8676002)(41300700001)(6666004)(70206006)(26005)(7696005)(6916009)(8936002)(44832011)(336012)(316002)(5660300002)(40460700003)(2616005)(4326008)(54906003)(47076005)(82740400003)(2906002)(36860700001)(83380400001)(36900700001);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 10:18:39.9384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51de9115-877b-4fee-bf45-08dbb442ccc7 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT047.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6310 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: While doing some SME work, I ran into the situation where the Z register contents restored from a signal frame are incorrect if the signal frame only contains fpsimd state and no sve state. This happens because we only restore the v register values in that case, and don't do anything for the z registers. Fix this by initializing the z registers to 0 and then copying over the overlapping part of the v registers to the z registers. While at it, refactor the code a bit to simplify it and make it smaller. Regression-tested on aarch64-linux Ubuntu 22.04/20.04. --- gdb/aarch64-linux-tdep.c | 107 +++++++++++++++++++++++---------------- 1 file changed, 62 insertions(+), 45 deletions(-) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index b183a3c9a38..bdd5cb05c10 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -196,14 +196,13 @@ read_aarch64_ctx (CORE_ADDR ctx_addr, enum bfd_endian byte_order, /* Given CACHE, use the trad_frame* functions to restore the FPSIMD registers from a signal frame. - VREG_NUM is the number of the V register being restored, OFFSET is the - address containing the register value, BYTE_ORDER is the endianness and - HAS_SVE tells us if we have a valid SVE context or not. */ + FPSIMD_CONTEXT is the address of the signal frame context containing FPSIMD + data. */ static void -aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, - int vreg_num, CORE_ADDR offset, - enum bfd_endian byte_order, bool has_sve) +aarch64_linux_restore_vregs (struct gdbarch *gdbarch, + struct trad_frame_cache *cache, + CORE_ADDR fpsimd_context) { /* WARNING: SIMD state is laid out in memory in target-endian format. @@ -215,11 +214,22 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, 2 - If the target is little endian, then SIMD state is little endian, so no byteswap is needed. */ - if (byte_order == BFD_ENDIAN_BIG) + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + int num_regs = gdbarch_num_regs (gdbarch); + aarch64_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + for (int i = 0; i < 32; i++) { + CORE_ADDR offset = (fpsimd_context + AARCH64_FPSIMD_V0_OFFSET + + (i * AARCH64_FPSIMD_VREG_SIZE)); + gdb_byte buf[V_REGISTER_SIZE]; - if (target_read_memory (offset, buf, V_REGISTER_SIZE) != 0) + /* Read the contents of the V register. */ + if (target_read_memory (offset, buf, V_REGISTER_SIZE)) + error (_("Failed to read fpsimd register from signal context.")); + + if (byte_order == BFD_ENDIAN_BIG) { size_t size = V_REGISTER_SIZE/2; @@ -234,50 +244,66 @@ aarch64_linux_restore_vreg (struct trad_frame_cache *cache, int num_regs, store_unsigned_integer (buf + size , size, BFD_ENDIAN_LITTLE, u64); /* Now we can store the correct bytes for the V register. */ - trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + vreg_num, + trad_frame_set_reg_value_bytes (cache, AARCH64_V0_REGNUM + i, {buf, V_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_Q0_REGNUM - + vreg_num, {buf, Q_REGISTER_SIZE}); + + i, {buf, Q_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_D0_REGNUM - + vreg_num, {buf, D_REGISTER_SIZE}); + + i, {buf, D_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_S0_REGNUM - + vreg_num, {buf, S_REGISTER_SIZE}); + + i, {buf, S_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_H0_REGNUM - + vreg_num, {buf, H_REGISTER_SIZE}); + + i, {buf, H_REGISTER_SIZE}); trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_B0_REGNUM - + vreg_num, {buf, B_REGISTER_SIZE}); + + i, {buf, B_REGISTER_SIZE}); - if (has_sve) + if (tdep->has_sve ()) trad_frame_set_reg_value_bytes (cache, num_regs + AARCH64_SVE_V0_REGNUM - + vreg_num, {buf, V_REGISTER_SIZE}); + + i, {buf, V_REGISTER_SIZE}); } - return; - } + else + { + /* Little endian, just point at the address containing the register + value. */ + trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + i, offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + i, + offset); + trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + i, + offset); - /* Little endian, just point at the address containing the register - value. */ - trad_frame_set_reg_addr (cache, AARCH64_V0_REGNUM + vreg_num, offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_Q0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_D0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_S0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_H0_REGNUM + vreg_num, - offset); - trad_frame_set_reg_addr (cache, num_regs + AARCH64_B0_REGNUM + vreg_num, - offset); - - if (has_sve) - trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM - + vreg_num, offset); + if (tdep->has_sve ()) + trad_frame_set_reg_addr (cache, num_regs + AARCH64_SVE_V0_REGNUM + + i, offset); + } + if (tdep->has_sve ()) + { + /* If SVE is supported for this target, zero out the Z + registers then copy the first 16 bytes of each of the V + registers to the associated Z register. Otherwise the Z + registers will contain uninitialized data. */ + std::vector z_buffer (tdep->vq * 16); + + /* We have already handled the endianness swap above, so we don't need + to worry about it here. */ + memcpy (z_buffer.data (), buf, V_REGISTER_SIZE); + trad_frame_set_reg_value_bytes (cache, + AARCH64_SVE_Z0_REGNUM + i, + z_buffer); + } + } } /* Implement the "init" method of struct tramp_frame. */ @@ -432,16 +458,7 @@ aarch64_linux_sigframe_init (const struct tramp_frame *self, /* If there was no SVE section then set up the V registers. */ if (sve_regs == 0) - { - for (int i = 0; i < 32; i++) - { - CORE_ADDR offset = (fpsimd + AARCH64_FPSIMD_V0_OFFSET - + (i * AARCH64_FPSIMD_VREG_SIZE)); - - aarch64_linux_restore_vreg (this_cache, num_regs, i, offset, - byte_order, tdep->has_sve ()); - } - } + aarch64_linux_restore_vregs (gdbarch, this_cache, fpsimd); } trad_frame_set_id (this_cache, frame_id_build (sp, func)); -- 2.25.1