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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2023 21:27:29.8057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb27439e-7786-4814-0ee8-08dbb88e1021 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT003.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS4PR08MB8119 X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: v3: - Assert the buffer size is capable of holding data we need to read/write. -- This patch adds support for ZT register dumps/reads for core files. The ZT register is available when the SME2 feature is advertised as available by the Linux Kernel. Unlike the enablement for SME1 and the ZA register, support for SME2 is rather simple given the fixed size of the ZT0 register. Validated on the Fast Models. Reviewed-by: Thiago Jung Bauermann --- gdb/aarch64-linux-tdep.c | 87 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index 41629902f49..f1fcce9b9eb 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -1373,6 +1373,56 @@ aarch64_linux_collect_za_regset (const struct regset *regset, size - SVE_HEADER_SIZE); } +/* Supply register REGNUM from BUF to REGCACHE, using the register map + in REGSET. If REGNUM is -1, do this for all registers in REGSET. + If BUF is NULL, set the registers to "unavailable" status. */ + +static void +aarch64_linux_supply_zt_regset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *buf, size_t size) +{ + /* Read the ZT register note from a core file into the register buffer. */ + + /* Make sure the buffer contains at least the expected amount of data we are + supposed to get. */ + gdb_assert (size >= AARCH64_SME2_ZT0_SIZE); + + /* Handle an empty buffer. */ + if (buf == nullptr) + return regcache->supply_regset (regset, regnum, nullptr, size); + + aarch64_gdbarch_tdep *tdep + = gdbarch_tdep (regcache->arch ()); + + /* Supply the ZT0 register contents. */ + regcache->raw_supply (tdep->sme2_zt0_regnum, buf); +} + +/* Collect register REGNUM from REGCACHE to BUF, using the register + map in REGSET. If REGNUM is -1, do this for all registers in + REGSET. */ + +static void +aarch64_linux_collect_zt_regset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *buf, size_t size) +{ + /* Read the ZT register contents from the register buffer into the core + file section. */ + + /* Make sure the buffer can hold the data we need to return. */ + gdb_assert (size >= AARCH64_SME2_ZT0_SIZE); + gdb_assert (buf != nullptr); + + aarch64_gdbarch_tdep *tdep + = gdbarch_tdep (regcache->arch ()); + + /* Dump the register cache contents for the ZT register to the buffer. */ + regcache->collect_regset (regset, tdep->sme2_zt0_regnum, buf, + AARCH64_SME2_ZT0_SIZE); +} + /* Implement the "iterate_over_regset_sections" gdbarch method. */ static void @@ -1461,6 +1511,30 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, SVE_HEADER_SIZE, SVE_HEADER_SIZE + std::pow (sve_vl_from_vq (tdep->sme_svq), 2), &aarch64_linux_za_regset, "ZA register", cb_data); + + /* Handle SME2 (ZT) as well, which is only available if SME is + available. */ + if (tdep->has_sme2 ()) + { + const struct regcache_map_entry zt_regmap[] = + { + { 1, tdep->sme2_zt0_regnum, AARCH64_SME2_ZT0_SIZE } + }; + + /* We set the register set size to REGSET_VARIABLE_SIZE here because + in the future there might be more ZT registers. */ + const struct regset aarch64_linux_zt_regset = + { + zt_regmap, + aarch64_linux_supply_zt_regset, aarch64_linux_collect_zt_regset, + REGSET_VARIABLE_SIZE + }; + + cb (".reg-aarch-zt", + AARCH64_SME2_ZT0_SIZE, + AARCH64_SME2_ZT0_SIZE, + &aarch64_linux_zt_regset, "ZT registers", cb_data); + } } if (tdep->has_pauth ()) @@ -1566,6 +1640,19 @@ aarch64_linux_core_read_description (struct gdbarch *gdbarch, features.svq = aarch64_linux_core_read_vq (gdbarch, abfd, ".reg-aarch-za"); + /* Are the ZT registers available? */ + if (bfd_get_section_by_name (abfd, ".reg-aarch-zt") != nullptr) + { + /* Check if ZA is also available, otherwise this is an invalid + combination. */ + if (bfd_get_section_by_name (abfd, ".reg-aarch-za") != nullptr) + features.sme2 = true; + else + warning (_("While reading core file sections, found ZT registers entry " + "but no ZA register entry. The ZT contents will be " + "ignored")); + } + return aarch64_read_description (features); } -- 2.25.1