From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by sourceware.org (Postfix) with ESMTPS id CF8F13858C62 for ; Fri, 13 Oct 2023 20:35:07 +0000 (GMT) ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CF8F13858C62 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697229309; cv=none; b=RpN8iOTUx7RvxSfkj8J8w2A4KVTgkScdfba+hv14rFgSv2J9oa6vpFrQ9T1FjxcBaBTucW9+bNuQs3rUtKBafgOms6spfdBVOxbe28vVz+/tgHjZG547aF2Zlt2qjIjwUdI1pxKqDtrRyNxqKrwuEryH4c3ZKS2syK4Lt6XvM04= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697229309; c=relaxed/simple; bh=h+hOxWpi4qzAhKQ5bQ5rmqj0Z2R6d/UaQ0UE3eEnPCA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=W3vFCgVSZRj6Um267/wlHsDMKsTQwzJLll5MZsjgB3E/G664vRLRP/qMBBzHxMpod2KRaNP4b6x4f8xUzGcgm+ed8yZjNdg/ov49YklEELL0FSWbNBwdcEErbLVFpdBdUy9q7zc2PFjfHzL+kpmxh40jHTB8djmeOTaPDCcxN6U= ARC-Authentication-Results: i=1; server2.sourceware.org DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CF8F13858C62 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=redhat.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1697229307; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WgeCht6GsonloOwbFrmE7TkakcEgBhdmpwbQ5b/fdy4=; b=VSHPQnZXHSgw60kARfK+ytyUul3ckK0BV/zqGBCyEueLEG7ISDPur4lBZ9ToQrsn3UXPI6 JeQiu/m+ewKwL4u8h7o16486PObmaoobA4BSTIjJfAqZEXH5R6F99TnVgMmh5M/imuQDig 8HmV79uFuFIYwf4z3s3XawNZF5PpBgM= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-173-5y-9wWxpOXeE7fORTI0DSQ-1; Fri, 13 Oct 2023 16:35:04 -0400 X-MC-Unique: 5y-9wWxpOXeE7fORTI0DSQ-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E7E9F185A7B5; Fri, 13 Oct 2023 20:35:03 +0000 (UTC) Received: from guittard.redhat.com (unknown [10.22.18.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 852B09DD; Fri, 13 Oct 2023 20:35:03 +0000 (UTC) From: Keith Seitz To: cel@us.ibm.com Cc: Ulrich.Weigand@de.ibm.com, gdb-patches@sourceware.org Subject: Re: [PATCH 2/2] PowerPC, Fix-test-gdb.base-store.exp Date: Fri, 13 Oct 2023 13:35:03 -0700 Message-ID: <20231013203503.1548215-1-keiths@redhat.com> In-Reply-To: <0a1d201b8868269496bcb15fd22811607e93a0c5.camel@us.ibm.com> References: <0a1d201b8868269496bcb15fd22811607e93a0c5.camel@us.ibm.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Carl Love wrote: As in your previous patch, I only have some really trivial nits to point out. So treat similarly, and thank you for the patch. > The test currently fails for IEEE 128-bit floating point types. PowerPC > supports the IBM double 128-bit floating point format and IEEE 128-bit Looks like a tab got inserted above? > format. The IBM double 128-bit floating point format uses two 64-bit > floating point registers to store the 128-bit value. The IEEE 128-bit > floating point format stores the value in a single 128-bit vector-scalar > register (vsr). > The various floating point values, 32-bit float, 64-bit double, IBM double > 128-bit float and IEEE 128-bit floating point numbers are all mapped to the > DWARF fpr numbers. The issue is the IEEE 128-bit floating point values are > actually stored in a vsr not the fprs. This patch changes the register > mapping for the vsrs from the fpr to the vsr registers so the value is > properly accessed by GDB. The functions rs6000_linux_register_to_value, > rs6000_linux_value_to_register, rs6000_linux_value_from_register check if > the value is an IEEE 128-bit floating point value and adjust the register > number as needed. The test in function rs6000_convert_register_p is fixed > to so it is only true for floating point values. "fixed [to] so" > This patch fixes three regression tests in gdb.base/store.exp. > > The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 LE > with no regressions. Indeed! Tested-by: Keith Seitz > Change to inline function Stray line or was there something more to communicate? Keith --- gdb/ppc-linux-tdep.c | 4 +++ gdb/rs6000-tdep.c | 66 +++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c index 7fb90799dff..ba646a7230f 100644 --- a/gdb/ppc-linux-tdep.c +++ b/gdb/ppc-linux-tdep.c @@ -63,6 +63,7 @@ #include #include "elf-bfd.h" #include "producer.h" +#include "target-float.h" #include "features/rs6000/powerpc-32l.c" #include "features/rs6000/powerpc-altivec32l.c" @@ -2101,6 +2102,9 @@ rs6000_linux_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) /* FIXME: jimb/2004-05-05: What should we do when the debug info specifies registers the architecture doesn't have? Our callers don't check the value we return. */ + /* Map dwarf register numbers for floating point, double, IBM double and + IEEE 128-bit floating point to the fpr range. Will have to fix the + mapping for the IEEE 128-bit register numbers later. */ I suggest rewording this last incomplete sentence to something like: "The mapping for the IEEE 128-bit register numbers will have to be fixed later." return tdep->ppc_fp0_regnum + (num - 32); else if (77 <= num && num < 77 + 32) return tdep->ppc_vr0_regnum + (num - 77); diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 23397d037ae..ada9cea3353 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -2676,7 +2676,25 @@ rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs && type->code () == TYPE_CODE_FLT && (type->length () - != builtin_type (gdbarch)->builtin_double->length ())); + == builtin_type (gdbarch)->builtin_float->length ())); +} + +static int +ieee_128_float_regnum_adjust (struct gdbarch *gdbarch, struct type *type, + int regnum) +{ + ppc_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + + /* If we have the an IEEE 128-bit floating point value, need to map the + register number to the corresponding VSR. */ "If we have the an" --> "If we have an". "need to" --> "" + if (tdep->ppc_vsr0_regnum != -1 + && regnum >= tdep->ppc_fp0_regnum + && regnum < (tdep->ppc_fp0_regnum + ppc_num_fprs) + && (gdbarch_long_double_format (gdbarch) == floatformats_ieee_quad) + && (type->length() == 16)) + regnum = regnum - tdep->ppc_fp0_regnum + tdep->ppc_vsr0_regnum; + + return regnum; } static int @@ -2691,6 +2709,10 @@ rs6000_register_to_value (frame_info_ptr frame, gdb_assert (type->code () == TYPE_CODE_FLT); + /* We have an IEEE 128-bit float need to change regnum mapping from + fpr to vsr. */ + regnum = ieee_128_float_regnum_adjust (gdbarch, type, regnum); + Add "--" before "need". Similarly below in a few spots. if (!get_frame_register_bytes (frame, regnum, 0, gdb::make_array_view (from, register_size (gdbarch, @@ -2715,11 +2737,52 @@ rs6000_value_to_register (frame_info_ptr frame, gdb_assert (type->code () == TYPE_CODE_FLT); + /* We have an IEEE 128-bit float need to change regnum mapping from + fpr to vsr. */ + regnum = ieee_128_float_regnum_adjust (gdbarch, type, regnum); + target_float_convert (from, type, to, builtin_type (gdbarch)->builtin_double); put_frame_register (frame, regnum, to); } +static struct value * +rs6000_value_from_register (struct gdbarch *gdbarch, struct type *type, + int regnum, struct frame_id frame_id) +{ + int len = type->length (); + struct value *value = value::allocate (type); + frame_info_ptr frame; + + /* We have an IEEE 128-bit float need to change regnum mapping from + fpr to vsr. */ + regnum = ieee_128_float_regnum_adjust (gdbarch, type, regnum); + + value->set_lval (lval_register); + frame = frame_find_by_id (frame_id); + + if (frame == NULL) + frame_id = null_frame_id; + else + frame_id = get_frame_id (get_next_frame_sentinel_okay (frame)); + + VALUE_NEXT_FRAME_ID (value) = frame_id; + VALUE_REGNUM (value) = regnum; + + /* Any structure stored in more than one register will always be + an integral number of registers. Otherwise, you need to do + some fiddling with the last register copied here for little + endian machines. */ + if (type_byte_order (type) == BFD_ENDIAN_BIG + && len < register_size (gdbarch, regnum)) + /* Big-endian, and we want less than full size. */ + value->set_offset (register_size (gdbarch, regnum) - len); + else + value->set_offset (0); + + return value; +} + /* The type of a function that moves the value of REG between CACHE or BUF --- in either direction. */ typedef enum register_status (*move_ev_register_func) (struct regcache *, @@ -8337,6 +8400,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); + set_gdbarch_value_from_register (gdbarch, rs6000_value_from_register); set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); -- 2.37.2