From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp.polymtl.ca (smtp.polymtl.ca [132.207.4.11]) by sourceware.org (Postfix) with ESMTPS id 996A23858D35 for ; Wed, 8 Nov 2023 05:21:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 996A23858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=polymtl.ca Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=polymtl.ca ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 996A23858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=132.207.4.11 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699420905; cv=none; b=TljjcLE67hLL+tuWEtM8ZmpLFvWI5ViA/XMWTJJhhXetBCcsd7Sm6/b6EL0zDPfDtg8vKHs+R8hlxMW0Xz89VbzK9FuVZpZcnMghYg08K19uCwOXGZfZCH0X85GhS8L0zej7dURD9eR3QB3VO7mxDqOoF54dUBRUt370jY7DlaA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699420905; c=relaxed/simple; bh=9ZClA6t2fPylEB8dcoTaSLcsxfMh+JFjoriLOWtfiLo=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=DmRhtEAGt8lktZVBCD+whd0Egocj0Y13pBQJVSJTrOUmams3VF16YIE7rNi5rWWmB3x6uS/FvzEURoYIQJrFHJQcIFNeZ2wSzgxuiinf0kRZTLGQSXf5cAwAnczm8cgjoXupvookfwBllMRjzl9l5DOSKrLNTxssdt92F5sS/30= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from simark.ca (simark.ca [158.69.221.121]) (authenticated bits=0) by smtp.polymtl.ca (8.14.7/8.14.7) with ESMTP id 3A85LcNi016953 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 8 Nov 2023 00:21:42 -0500 DKIM-Filter: OpenDKIM Filter v2.11.0 smtp.polymtl.ca 3A85LcNi016953 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=polymtl.ca; s=default; t=1699420903; bh=Bj8PgNZ47TjErJBqt5ZZa6hphVyigICLEVIYo+VXbKI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WElyXWQddubiweoNm5y2Alm93zGneEqt8E+QNKJd9QystwfvnWNd6+qwwvptHp8+S dWQhhE5FWzPPvsAlRt7K27JZ1/Hyg68yFQjMWY8mJxpA/Pjqafty+msMmfVPs5dNch QXESQMGEnNAUHXzEtmpkXu/FNc/TnYuSIPu1J9yY= Received: from simark.localdomain (modemcable238.237-201-24.mc.videotron.ca [24.201.237.238]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPSA id CCBF51E1CC; Wed, 8 Nov 2023 00:16:37 -0500 (EST) From: Simon Marchi To: gdb-patches@sourceware.org Cc: Simon Marchi Subject: [PATCH 23/24] gdb: migrate arm to new gdbarch_pseudo_register_write Date: Wed, 8 Nov 2023 00:01:07 -0500 Message-ID: <20231108051222.1275306-24-simon.marchi@polymtl.ca> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20231108051222.1275306-1-simon.marchi@polymtl.ca> References: <20231108051222.1275306-1-simon.marchi@polymtl.ca> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Poly-FromMTA: (simark.ca [158.69.221.121]) at Wed, 8 Nov 2023 05:21:38 +0000 X-Spam-Status: No, score=-3188.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Simon Marchi Make arm use the new gdbarch_pseudo_register_write. This fixes writing pseudo registers to non-current frames for that architecture. Change-Id: Icb2a649ab6394817844230e9e94c3d0564d2f765 --- gdb/arm-tdep.c | 62 +++++++++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 26 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 9bf51485b800..a0d019b564bf 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -9908,57 +9908,67 @@ arm_neon_quad_write (struct gdbarch *gdbarch, struct regcache *regcache, regcache->raw_write (double_regnum + 1, buf + 8); } +static void +arm_neon_quad_write (gdbarch *gdbarch, frame_info_ptr next_frame, + int quad_reg_index, gdb::array_view buf) +{ + std::string raw_reg_name = string_printf ("d%d", quad_reg_index << 1); + int double_regnum + = user_reg_map_name_to_regnum (gdbarch, raw_reg_name.data (), + raw_reg_name.length ()); + + pseudo_to_concat_raw (next_frame, buf, double_regnum, double_regnum + 1); +} + /* Store the contents of BUF to the MVE pseudo register REGNUM. */ static void -arm_mve_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, - int regnum, const gdb_byte *buf) +arm_mve_pseudo_write (gdbarch *gdbarch, frame_info_ptr next_frame, + int pseudo_reg_num, gdb::array_view buf) { arm_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); /* P0 is the first 16 bits of VPR. */ - regcache->raw_write_part (tdep->mve_vpr_regnum, 0, 2, buf); + pseudo_to_raw_part(next_frame, buf, tdep->mve_vpr_regnum, 0); } static void -arm_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, - int regnum, const gdb_byte *buf) +arm_pseudo_write (gdbarch *gdbarch, frame_info_ptr next_frame, + const int pseudo_reg_num, + gdb::array_view buf) { - const int num_regs = gdbarch_num_regs (gdbarch); - char name_buf[4]; - gdb_byte reg_buf[8]; - int offset, double_regnum; arm_gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); - gdb_assert (regnum >= num_regs); + gdb_assert (pseudo_reg_num >= gdbarch_num_regs (gdbarch)); - if (is_q_pseudo (gdbarch, regnum)) + if (is_q_pseudo (gdbarch, pseudo_reg_num)) { /* Quad-precision register. */ - arm_neon_quad_write (gdbarch, regcache, - regnum - tdep->q_pseudo_base, buf); + arm_neon_quad_write (gdbarch, next_frame, + pseudo_reg_num - tdep->q_pseudo_base, buf); } - else if (is_mve_pseudo (gdbarch, regnum)) - arm_mve_pseudo_write (gdbarch, regcache, regnum, buf); + else if (is_mve_pseudo (gdbarch, pseudo_reg_num)) + arm_mve_pseudo_write (gdbarch, next_frame, pseudo_reg_num, buf); else { - regnum -= tdep->s_pseudo_base; + int s_reg_index = pseudo_reg_num - tdep->s_pseudo_base; + /* Single-precision register. */ - gdb_assert (regnum < 32); + gdb_assert (s_reg_index < 32); /* s0 is always the least significant half of d0. */ + int offset; if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) - offset = (regnum & 1) ? 0 : 4; + offset = (s_reg_index & 1) ? 0 : 4; else - offset = (regnum & 1) ? 4 : 0; + offset = (s_reg_index & 1) ? 4 : 0; - xsnprintf (name_buf, sizeof (name_buf), "d%d", regnum >> 1); - double_regnum = user_reg_map_name_to_regnum (gdbarch, name_buf, - strlen (name_buf)); + std::string raw_reg_name = string_printf ("d%d", s_reg_index >> 1); + int double_regnum + = user_reg_map_name_to_regnum (gdbarch, raw_reg_name.c_str (), + raw_reg_name.length ()); - regcache->raw_read (double_regnum, reg_buf); - memcpy (reg_buf + offset, buf, 4); - regcache->raw_write (double_regnum, reg_buf); + pseudo_to_raw_part (next_frame, buf, double_regnum, offset); } } @@ -10918,7 +10928,7 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) { set_gdbarch_num_pseudo_regs (gdbarch, num_pseudos); set_gdbarch_pseudo_register_read_value (gdbarch, arm_pseudo_read_value); - set_gdbarch_deprecated_pseudo_register_write (gdbarch, arm_pseudo_write); + set_gdbarch_pseudo_register_write (gdbarch, arm_pseudo_write); } /* Add standard register aliases. We add aliases even for those -- 2.42.1