From: <jaydeep.patil@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
<joseph.faulls@imgtec.com>, <bhushan.attarde@imgtec.com>,
<jaydeep.patil@imgtec.com>
Subject: [PATCH v7 0/1] sim: riscv: Compressed instruction simulation
Date: Tue, 23 Jan 2024 05:50:37 +0000 [thread overview]
Message-ID: <20240123055038.249677-1-jaydeep.patil@imgtec.com> (raw)
From: Jaydeep Patil <jaydeep.patil@imgtec.com>
Hi Mike, Andrew,
Addressed review comments.
- Retain the error block which checks length of opcode
- Change simulator tests to match 'riscv32 riscv64' instead of 'all'
Jaydeep Patil (1):
sim: riscv: Add support for compressed integer instructions
sim/riscv/model_list.def | 9 +
sim/riscv/sim-main.c | 332 +++++++++++++++++++++++++++++++-
sim/testsuite/riscv/allinsn.exp | 2 +-
sim/testsuite/riscv/c-ext.s | 95 +++++++++
sim/testsuite/riscv/jalr.s | 2 +-
sim/testsuite/riscv/m-ext.s | 2 +-
sim/testsuite/riscv/pass.s | 2 +-
7 files changed, 436 insertions(+), 8 deletions(-)
create mode 100644 sim/testsuite/riscv/c-ext.s
--
2.25.1
next reply other threads:[~2024-01-23 5:51 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-23 5:50 jaydeep.patil [this message]
2024-01-23 5:50 ` [PATCH v7 1/1] sim: riscv: Add support for compressed integer instructions jaydeep.patil
2024-01-31 18:18 ` Andrew Burgess
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