From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id DAA8A3858431 for ; Mon, 26 Feb 2024 14:23:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DAA8A3858431 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DAA8A3858431 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957386; cv=none; b=WsZgswFJ9zhpWwtORHWOJ5L4p3xT4nVZT4aY/cJ8fLUGYHf+i7aLWzjQvNX/SsYr004xUo0i60p8dN2DJCYTYyg/xsIW1B42uTVvEZv8X9I1DlYhjETGfXGMj03lBtmFEbL5DxQtYGdTJq0bA2xqPryxAxse+Cja/HgjjJbrUlg= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957386; c=relaxed/simple; bh=xdM1vxdC3Txoow5cCOdKFa59CJ1GkM06XQGWd/4jty0=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=uE/JLxuVgq9m4jZ/CoHjplun5Ch5aQkloz4AfRI8jfrYIRkjJORM004A1KZEWfKAkknC+kLpr4tEU6cqH4gC37dqVAlYGt2xO4+FISGMC/VjyCxkSNRZeSywJ2s0ocO1fj47EcoUpSfsVm8nymwIDATM1SgQg8hGTmSdSlh55uY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q8CPdL013671; Mon, 26 Feb 2024 14:22:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= dk201812; bh=COouRicamEJ6ua3hjVy6M0FKBD+/jmx8JvnZnUNp0GE=; b=Xbh fYDOo3faDx2XExJhkKsKzlre8uPjG93KRE/4N46ovjkWRi8kAzE2xloPynOddnyb o2tR5L5Ktj6pl/085jm2Fg0VlQWdbUFX+a0q0hdBWZ0YDW5WQLzR6dN4ZG2dG5j3 C9kNPkpZuc8jvnwKS2r2+yQOz+AZSmQkRZVk6XaSLXqjTOJvW1jnfyzqlDZMSPfJ LjCwkQyXCsYC5AoHYIw9yhhIWzgRi6LJFI5mQetCNQ21pV3jpW/o/koOYGk4IqCC aolFVUuugqSxXEkxqbzLDlBefzdWkyjPKX0Tf4uHTKnTZd9yDLhMjn0cA1zGoiQ8 JsbvIR/Tnu3MAn/Zpfg== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3wf7kssr3e-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 26 Feb 2024 14:22:51 +0000 (GMT) Received: from hhbattarde.hh.imgtec.org (10.100.136.78) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 14:22:49 +0000 From: To: CC: , , , Bhushan Attarde Subject: [PATCH 03/11] sim: riscv: Add floating-point CSR instructions Date: Mon, 26 Feb 2024 14:22:26 +0000 Message-ID: <20240226142234.1628932-4-bhushan.attarde@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226142234.1628932-1-bhushan.attarde@imgtec.com> References: <20240226142234.1628932-1-bhushan.attarde@imgtec.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.100.136.78] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: rtQ8-bfw_16XbQr8AE8m5hsTn4z49qmH X-Proofpoint-ORIG-GUID: rtQ8-bfw_16XbQr8AE8m5hsTn4z49qmH X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Bhushan Attarde Added simulation of following single precision floating-point instructions frcsr, fscsr, frrm, fsrm, fsrmi, frflags, fsflags and fsflagsi. Added test file sim/testsuite/riscv/f-csr.s to test these instructions. --- sim/riscv/sim-main.c | 64 +++++++++++++++++++++++++++++++++++++ sim/testsuite/riscv/f-csr.s | 56 ++++++++++++++++++++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 sim/testsuite/riscv/f-csr.s diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 9c132d9a448..0e873895f76 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -599,6 +599,21 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) riscv_cpu->regs[rs1]); \ break; #include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; + case MATCH_CSRRWI: + TRACE_INSN (cpu, "csrrwi"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, \ + fetch_csr (cpu, #name, num, &riscv_cpu->csr.name)); \ + store_csr (cpu, #name, num, &riscv_cpu->csr.name, \ + rs1); \ + break; +#include "opcode/riscv-opc.h" #undef DECLARE_CSR } break; @@ -949,6 +964,54 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FMAX_S: float32_math (cpu, rd, rs1, rs2, FMAX); break; + case MATCH_FRCSR: + TRACE_INSN (cpu, "frcsr %s;", rd_name); + store_rd (cpu, rd, riscv_cpu->csr.fcsr); + break; + case MATCH_FSCSR: + TRACE_INSN (cpu, "fscsr %s, %s;", rd_name, rs1_name); + store_rd (cpu, rd, riscv_cpu->csr.fcsr); + riscv_cpu->csr.fcsr = riscv_cpu->regs[rs1] & 0xff; + riscv_cpu->csr.frm = (riscv_cpu->regs[rs1] >> 5) & 0x7; + riscv_cpu->csr.fflags = riscv_cpu->regs[rs1] & 0x1f; + TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->regs[rs1]); + break; + case MATCH_FRRM: + TRACE_INSN (cpu, "frrm %s;", rd_name); + store_rd (cpu, rd, riscv_cpu->csr.frm); + break; + case MATCH_FSRM: + TRACE_INSN (cpu, "fsrm %s, %s;", rd_name, rs1_name); + store_rd (cpu, rd, riscv_cpu->csr.frm); + riscv_cpu->csr.frm = riscv_cpu->regs[rs1] & 0x7; + riscv_cpu->csr.fcsr |= (riscv_cpu->regs[rs1] & 0x7) << 5; + TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr); + break; + case MATCH_FSRMI: + TRACE_INSN (cpu, "fsrmi %s, %x;", rd_name, rs1); + store_rd (cpu, rd, riscv_cpu->csr.frm); + riscv_cpu->csr.frm = rs1 & 0x7; + riscv_cpu->csr.fcsr |= (rs1 & 0x7) << 5; + TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr); + break; + case MATCH_FRFLAGS: + TRACE_INSN (cpu, "frflags %s;", rd_name); + store_rd (cpu, rd, riscv_cpu->csr.fflags); + break; + case MATCH_FSFLAGS: + TRACE_INSN (cpu, "fsflags %s, %s;", rd_name, rs1_name); + store_rd (cpu, rd, riscv_cpu->csr.fflags); + riscv_cpu->csr.fflags = riscv_cpu->regs[rs1] & 0x1f; + riscv_cpu->csr.fcsr |= riscv_cpu->regs[rs1] & 0x1f; + TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr); + break; + case MATCH_FSFLAGSI: + TRACE_INSN (cpu, "fsflagsi %s, %x;", rd_name, rs1); + store_rd (cpu, rd, riscv_cpu->csr.fflags); + riscv_cpu->csr.fflags = rs1 & 0x1f; + riscv_cpu->csr.fcsr |= rs1 & 0x1f; + TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr); + break; default: TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL); @@ -1592,6 +1655,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case INSN_CLASS_F_INX: return execute_f (cpu, iw, op); case INSN_CLASS_I: + case INSN_CLASS_ZICSR: return execute_i (cpu, iw, op); case INSN_CLASS_M: case INSN_CLASS_ZMMUL: diff --git a/sim/testsuite/riscv/f-csr.s b/sim/testsuite/riscv/f-csr.s new file mode 100644 index 00000000000..c8f930b0d86 --- /dev/null +++ b/sim/testsuite/riscv/f-csr.s @@ -0,0 +1,56 @@ +# Floating-point CSR instructions tests +# mach: riscv32 riscv64 +# sim(riscv32): --model RV32IF +# sim(riscv64): --model RV64ID +# ld(riscv32): -m elf32lriscv +# ld(riscv64): -m elf64lriscv +# as(riscv32): -march=rv32if +# as(riscv64): -march=rv64id + +.include "testutils.inc" + + start + # Test fscsr and frcsr instruction. + li a4,0x44 # mode:RDN, exception flags:OF + fscsr a5,a4 + frcsr a6 + bne a4,a6,test_fail + + # Test rounding mode and flags read instruction. + li a4,0x2 # mode:RDN + frrm a5 + bne a4,a5,test_fail + frflags a5 + li a6,0x4 # exception flags:OF + bne a6,a5,test_fail + + # Test swap rounding mode instruction. + li a6,0x7 # mode:Dynamic + fsrm a5,a6 + bne a4,a5,test_fail # earlier mode should be RDN + frrm a5 + bne a6,a5,test_fail # new mode should be Dynamic + + # Test swap rounding mode with immediate value instruction. + fsrmi a5,0x2 # set new mode RDN (0x2) + frrm a5 # read the mode + li a6,0x2 + bne a6,a5,test_fail # should be RDN (0x2) + + # Test swap exception flags instruction. + li a6,0x8 # flag:Divide by zero + fsflags a5,a6 + frflags a5 + bne a5,a6,test_fail + + # Test swap exception flags with immediate value instruction. + fsflagsi a5,0x2 # set new flag to underflow (0x2) + frflags a5 # read the flag + li a6,0x2 + bne a5,a6,test_fail # should be underflow (0x2) + +test_pass: + pass + +test_fail: + fail -- 2.25.1