From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by sourceware.org (Postfix) with ESMTPS id F24B23858C35 for ; Tue, 7 May 2024 02:22:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F24B23858C35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F24B23858C35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::636 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715048579; cv=none; b=gUmb/+5wxPz+tJFIRBy4063dGP8hwv3bQLAC3O50GfxGr0TgQTLyafXiqM4fRKplBGkr3OlNQGl4rGc3Ys0ec614Cji8sQ5tg0NnKFhtNytU6TVZfyNjElFUj6ZUbzerlcmLUXgqu37YmYiho8iuNmUT9O3bokb76pHK5V/pgvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1715048579; c=relaxed/simple; bh=zFSGUkqDI0MOYM2pUE6DA4E5R/J5pmMjMuyE9SYiKT4=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=fbYnm2RIeMi6ktTCJCDjXw5hEXaucUm06xX9uGeWdkQ9sn73M1RAcw7lRckhNOnvQ+OUNCIkO/rZBgLlo6Myv4NfhBnjA+DOqZMEuimnHVsMiLh1cCyDGmKuhAc9jWlQCx7wHAHLJUiBI3ajQNy+81PPSKHzYyHpLzAS8H3DVnc= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1e65a1370b7so23769745ad.3 for ; Mon, 06 May 2024 19:22:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1715048575; x=1715653375; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fzlvsQCgH/KfN0WcXJlNAmkEuOxm7DAKAv7avv6N3us=; b=VuwhZLCCTKbiFF0ZYDF+RnUrg8rWxiH9FfH9+m40U04IMYP7Z6ZI7YQd3WWhWwWNSR ZtRG5jI6KwHNegpmZjsZId5ufHMqZixlGtn+UqEdfz0lb4ZGWuDd+2qEJxfLuC801wJF nUL1jBC4UDKawNpWg5+hdQf+F+VNM2brai4Z6OpPm6UxjGgcEgEACeyT4Ee9G08bZ6re qq/+cQci5MsJkZJx1oK4gC3bPIK/MDX0HaRmkGl+gOnDtJiAYn2YLrfHVyQBxOqrOpq0 BqlfcUqRIoA3wfqyTHR5h3gjn2pmqDKsL7Tt1HTgKWgh2wRhcIEIR0IayZnDNJLnPFVK yRaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715048575; x=1715653375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fzlvsQCgH/KfN0WcXJlNAmkEuOxm7DAKAv7avv6N3us=; b=CBMPSCaU8YGACZPwwt/DZwyVt0c8newc3BRDwUq+Z0a3ix7tSU2fLA8Xqc0mWJMJsX OPorkyVBh3yufbsC341vdCHE22YOOfx2wNlcV5tIp1xnW+4+5n41yRBfyHZ4lL3OIFsS ktwFgcGisgg5Lk5uXc8A7dcDaQ5Mnp3ekRyzWd8c5ZTGnAzCOoHL0AGwV50Tu9uwkfLF H5ho1f0Y3+BNIhxoylrwNvTO3LiWG2mMo75Y0mcJoOezxayZcDuU8mjZ/JRf+HR1Naeh Vd33Z2F616BKpqnGzWOk9QLCoDpNw0kqbIT1Urd9ZNNUkMV3BbSJ80vbfRf9WuRhtOMV CbwA== X-Gm-Message-State: AOJu0YyFWpxs70sP5WXWVnYPQ13VZcdcDIGmsgE81jolB7aXRd3MhYpB FWnbwB3jusLywVyr0MfXm6U2C1PQvTVehPbui8UpLLxy1tV0hb82lrrCv/6+p6P/RshNIdpuukX w X-Google-Smtp-Source: AGHT+IHfgOnewyNnIczvpdm1L4nZaE+Ko5+bJW0R6CGcW39MZxzUXKm5qAWY25jD7To/ocSNwhPH0g== X-Received: by 2002:a17:902:cec3:b0:1ec:198:bfbc with SMTP id d3-20020a170902cec300b001ec0198bfbcmr16602952plg.34.1715048574706; Mon, 06 May 2024 19:22:54 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8470:38ad:4156:59df:8141]) by smtp.gmail.com with ESMTPSA id t18-20020a170902e85200b001eb50eba52esm8928070plg.214.2024.05.06.19.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 May 2024 19:22:54 -0700 (PDT) From: Thiago Jung Bauermann To: gdb-patches@sourceware.org Cc: Christophe Lyon Subject: [PATCH v2 1/5] gdb/aarch64: Implement software single stepping for MOPS instructions Date: Mon, 6 May 2024 23:22:45 -0300 Message-ID: <20240507022249.554831-2-thiago.bauermann@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240507022249.554831-1-thiago.bauermann@linaro.org> References: <20240507022249.554831-1-thiago.bauermann@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: The AArch64 MOPS (Memory Operation) instructions provide a standardised instruction sequence to perform a memset, memcpy or memmove. A sequence is always composed of three instructions: a prologue instruction, a main instruction and an epilogue instruction. As an illustration, here are the implementations of these memory operations in glibc 2.39: (gdb) disassemble/r Dump of assembler code for function __memset_mops: => 0x0000fffff7e8d780 <+0>: d503201f nop 0x0000fffff7e8d784 <+4>: aa0003e3 mov x3, x0 0x0000fffff7e8d788 <+8>: 19c10443 setp [x3]!, x2!, x1 0x0000fffff7e8d78c <+12>: 19c14443 setm [x3]!, x2!, x1 0x0000fffff7e8d790 <+16>: 19c18443 sete [x3]!, x2!, x1 0x0000fffff7e8d794 <+20>: d65f03c0 ret End of assembler dump. (gdb) disassemble/r Dump of assembler code for function __memcpy_mops: => 0x0000fffff7e8c580 <+0>: d503201f nop 0x0000fffff7e8c584 <+4>: aa0003e3 mov x3, x0 0x0000fffff7e8c588 <+8>: 19010443 cpyfp [x3]!, [x1]!, x2! 0x0000fffff7e8c58c <+12>: 19410443 cpyfm [x3]!, [x1]!, x2! 0x0000fffff7e8c590 <+16>: 19810443 cpyfe [x3]!, [x1]!, x2! 0x0000fffff7e8c594 <+20>: d65f03c0 ret End of assembler dump. (gdb) disassemble/r Dump of assembler code for function __memmove_mops: => 0x0000fffff7e8d180 <+0>: d503201f nop 0x0000fffff7e8d184 <+4>: aa0003e3 mov x3, x0 0x0000fffff7e8d188 <+8>: 1d010443 cpyp [x3]!, [x1]!, x2! 0x0000fffff7e8d18c <+12>: 1d410443 cpym [x3]!, [x1]!, x2! 0x0000fffff7e8d190 <+16>: 1d810443 cpye [x3]!, [x1]!, x2! 0x0000fffff7e8d194 <+20>: d65f03c0 ret End of assembler dump. The Arm Architecture Reference Manual says that "the prologue, main, and epilogue instructions are expected to be run in succession and to appear consecutively in memory". Therefore GDB needs to treat them as an atomic instruction sequence, and also can't do displaced stepping with them. This patch implements support for executing the sequence atomically, and also disables displaced step on them. PR tdep/31666 Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31666 --- gdb/aarch64-tdep.c | 107 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 2 deletions(-) No change in v2. diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 8d0553f3d7cd..e920cea49066 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -3444,6 +3444,104 @@ value_of_aarch64_user_reg (const frame_info_ptr &frame, const void *baton) return value_of_register (*reg_p, get_next_frame_sentinel_okay (frame)); } +/* Single step through MOPS instruction sequences on AArch64. */ + +static std::vector +aarch64_software_single_step_mops (struct regcache *regcache, CORE_ADDR loc, + uint32_t insn) +{ + const int insn_size = 4; + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); + uint8_t o0 = bit (insn, 21); + uint8_t op1 = bits (insn, 22, 23); + uint8_t op2 = bits (insn, 12, 15); + + /* Look for the prologue instruction that begins the sequence. */ + + /* CPYFP* */ + if (!((o0 == 0 && op1 == 0) + /* SETP* */ + || (o0 == 0 && op1 == 3 && op2 < 4) + /* CPYP* */ + || (o0 == 1 && op1 == 0) + /* SETGP* */ + || (o0 == 1 && op1 == 3 && op2 < 4))) + /* Prologue instruction not found. */ + return {}; + + /* Now look for the main instruction in the middle of the sequence. */ + + loc += insn_size; + ULONGEST insn_from_memory; + if (!safe_read_memory_unsigned_integer (loc, insn_size, + byte_order_for_code, + &insn_from_memory)) + { + /* Assume we don't have a MOPS sequence, as we couldn't read the + instruction in this location. */ + return {}; + } + + insn = insn_from_memory; + aarch64_inst inst; + if (aarch64_decode_insn (insn, &inst, 1, nullptr) != 0) + return {}; + if (!AARCH64_CPU_HAS_FEATURE (*inst.opcode->avariant, MOPS)) + return {}; + + o0 = bit (insn, 21); + op1 = bits (insn, 22, 23); + op2 = bits (insn, 12, 15); + + /* CPYFM* */ + if (!((o0 == 0 && op1 == 1) + /* SETM* */ + || (o0 == 0 && op1 == 3 && op2 >= 4 && op2 < 8) + /* CPYM* */ + || (o0 == 1 && op1 == 1) + /* SETGM* */ + || (o0 == 1 && op1 == 3 && op2 >= 4 && op2 < 8))) + /* Main instruction not found. */ + return {}; + + /* Now look for the epilogue instruction that ends the sequence. */ + + loc += insn_size; + if (!safe_read_memory_unsigned_integer (loc, insn_size, + byte_order_for_code, + &insn_from_memory)) + { + /* Assume we don't have a MOPS sequence, as we couldn't read the + instruction in this location. */ + return {}; + } + + insn = insn_from_memory; + if (aarch64_decode_insn (insn, &inst, 1, nullptr) != 0) + return {}; + if (!AARCH64_CPU_HAS_FEATURE (*inst.opcode->avariant, MOPS)) + return {}; + + o0 = bit (insn, 21); + op1 = bits (insn, 22, 23); + op2 = bits (insn, 12, 15); + + /* CPYFE* */ + if (!((o0 == 0 && op1 == 2) + /* SETE* (op2 >= 12 is unallocated space) */ + || (o0 == 0 && op1 == 3 && op2 >= 8 && op2 < 12) + /* CPYE* */ + || (o0 == 1 && op1 == 2) + /* SETGE* (op2 >= 12 is unallocated space) */ + || (o0 == 1 && op1 == 3 && op2 >= 8 && op2 < 12))) + /* Epilogue instruction not found. */ + return {}; + + /* Insert breakpoint after the end of the atomic sequence. */ + return { loc + insn_size }; +} + /* Implement the "software_single_step" gdbarch method, needed to single step through atomic sequences on AArch64. */ @@ -3479,6 +3577,9 @@ aarch64_software_single_step (struct regcache *regcache) if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) return {}; + if (AARCH64_CPU_HAS_FEATURE (*inst.opcode->avariant, MOPS)) + return aarch64_software_single_step_mops (regcache, loc, insn); + /* Look for a Load Exclusive instruction which begins the sequence. */ if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) return {}; @@ -3808,8 +3909,10 @@ aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) return NULL; - /* Look for a Load Exclusive instruction which begins the sequence. */ - if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) + /* Look for a Load Exclusive instruction which begins the sequence, + or for a MOPS instruction. */ + if ((inst.opcode->iclass == ldstexcl && bit (insn, 22)) + || AARCH64_CPU_HAS_FEATURE (*inst.opcode->avariant, MOPS)) { /* We can't displaced step atomic sequences. */ return NULL;