From: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
To: gdb-patches@sourceware.org
Cc: Christophe Lyon <christophe.lyon@linaro.org>
Subject: [PATCH v2 2/5] gdb/aarch64: Add record support for MOPS instructions.
Date: Mon, 6 May 2024 23:22:46 -0300 [thread overview]
Message-ID: <20240507022249.554831-3-thiago.bauermann@linaro.org> (raw)
In-Reply-To: <20240507022249.554831-1-thiago.bauermann@linaro.org>
There are two kinds of MOPS instructions: set instructions and copy
instructions. Within each group there are variants with minor
differences in how they read or write to memory — e.g., non-temporal
read and/or write, unprivileged read and/or write and permutations of
those — but they work in the same way in terms of the registers and
regions of memory that they modify.
PR tdep/31666
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31666
---
gdb/aarch64-tdep.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
No change in v2.
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e920cea49066..c60c5d6e0ec2 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -5289,6 +5289,86 @@ aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r)
return AARCH64_RECORD_SUCCESS;
}
+/* Record handler for Memory Copy and Memory Set instructions. */
+
+static unsigned int
+aarch64_record_memcopy_memset (aarch64_insn_decode_record *aarch64_insn_r)
+{
+ if (record_debug)
+ debug_printf ("Process record: memory copy and memory set\n");
+
+ uint8_t op1 = bits (aarch64_insn_r->aarch64_insn, 22, 23);
+ uint8_t op2 = bits (aarch64_insn_r->aarch64_insn, 12, 15);
+ uint32_t reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4);
+ uint32_t reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9);
+ uint32_t record_buf[3];
+ uint64_t record_buf_mem[4];
+
+ if (op1 != 3)
+ {
+ /* Copy instructions. */
+ uint32_t reg_rs = bits (aarch64_insn_r->aarch64_insn, 16, 20);
+
+ record_buf[0] = reg_rd;
+ record_buf[1] = reg_rn;
+ record_buf[2] = reg_rs;
+ aarch64_insn_r->reg_rec_count = 3;
+
+ ULONGEST dest_addr;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rd,
+ &dest_addr);
+ ULONGEST source_addr;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rs,
+ &source_addr);
+ LONGEST length;
+ regcache_raw_read_signed (aarch64_insn_r->regcache, reg_rn,
+ &length);
+
+ /* In a processor using algorithm option A, the length in Rn has an
+ inverted sign. */
+ if (length < 0)
+ length *= -1;
+
+ record_buf_mem[0] = length;
+ record_buf_mem[1] = dest_addr;
+ record_buf_mem[2] = length;
+ record_buf_mem[3] = source_addr;
+ aarch64_insn_r->mem_rec_count = 2;
+ }
+ else if ((op1 == 3 && op2 < 12) || (op1 == 3 && op2 < 12))
+ {
+ /* Set instructions. */
+ record_buf[0] = reg_rd;
+ record_buf[1] = reg_rn;
+ aarch64_insn_r->reg_rec_count = 2;
+
+ ULONGEST address;
+ regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rd,
+ &address);
+
+ LONGEST length;
+ regcache_raw_read_signed (aarch64_insn_r->regcache, reg_rn,
+ &length);
+
+ /* In a processor using algorithm option B, the length in Rn has an
+ inverted sign. */
+ if (length < 0)
+ length *= -1;
+
+ record_buf_mem[0] = length;
+ record_buf_mem[1] = address;
+ aarch64_insn_r->mem_rec_count = 1;
+ }
+ else
+ return AARCH64_RECORD_UNKNOWN;
+
+ MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count,
+ record_buf_mem);
+ REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count,
+ record_buf);
+ return AARCH64_RECORD_SUCCESS;
+}
+
/* Record handler for load and store instructions. */
static unsigned int
@@ -5566,6 +5646,10 @@ aarch64_record_load_store (aarch64_insn_decode_record *aarch64_insn_r)
if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03)
record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn;
}
+ /* Memory Copy and Memory Set instructions. */
+ else if ((insn_bits24_27 & 1) == 1 && insn_bits28_29 == 1
+ && insn_bits10_11 == 1 && !insn_bit21)
+ return aarch64_record_memcopy_memset (aarch64_insn_r);
/* Advanced SIMD load/store instructions. */
else
return aarch64_record_asimd_load_store (aarch64_insn_r);
next prev parent reply other threads:[~2024-05-07 2:22 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-07 2:22 [PATCH v2 0/5] Add support for AArch64 " Thiago Jung Bauermann
2024-05-07 2:22 ` [PATCH v2 1/5] gdb/aarch64: Implement software single stepping for " Thiago Jung Bauermann
2024-05-10 13:23 ` Pedro Alves
2024-05-21 21:40 ` Thiago Jung Bauermann
2024-05-22 10:51 ` Luis Machado
2024-05-07 2:22 ` Thiago Jung Bauermann [this message]
2024-05-07 2:22 ` [PATCH v2 3/5] gdb/testsuite: Add gdb.arch/aarch64-mops-watchpoint.exp Thiago Jung Bauermann
2024-05-10 13:32 ` Pedro Alves
2024-05-21 21:03 ` Thiago Jung Bauermann
2024-05-22 9:22 ` Tom de Vries
2024-05-22 15:38 ` Tom Tromey
2024-05-22 16:43 ` Thiago Jung Bauermann
2024-05-07 2:22 ` [PATCH v2 4/5] gdb/testsuite: Add gdb.arch/aarch64-mops-atomic-inst.exp Thiago Jung Bauermann
2024-05-07 2:22 ` [PATCH v2 5/5] gdb/testsuite: Add gdb.reverse/aarch64-mops.exp Thiago Jung Bauermann
2024-05-08 8:52 ` [PATCH v2 0/5] Add support for AArch64 MOPS instructions Luis Machado
2024-05-09 3:24 ` Thiago Jung Bauermann
2024-05-10 5:20 ` Thiago Jung Bauermann
2024-05-10 13:11 ` Luis Machado
2024-05-10 15:07 ` Guinevere Larsen
2024-05-23 1:43 ` Thiago Jung Bauermann
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