* [PATCH 1/4] gdb: sim: consolidate configure settings
@ 2021-08-19 21:23 Mike Frysinger
2021-08-19 21:23 ` [PATCH 2/4] gdb: aarch64: enable sim integration Mike Frysinger
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Mike Frysinger @ 2021-08-19 21:23 UTC (permalink / raw)
To: gdb-patches
Moving all the sim settings to one section makes it easier to track,
and makes it easier to keep it aligned with the sim target tests.
The gdb logic was duplicating this when handling different OS targets
instead of having a single cpu check. Now it's more obvious that the
sim is tied to a cpu and not related to the OS.
---
gdb/configure.tgt | 75 ++++++++++++++++++++++-------------------------
1 file changed, 35 insertions(+), 40 deletions(-)
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index cac76f4106c9..b5259dfbc762 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -190,30 +190,25 @@ arm*-*-openbsd*)
arm*-*-*)
# Target: ARM embedded system
gdb_target_obs="arm-pikeos-tdep.o"
- gdb_sim=../sim/arm/libsim.a
;;
avr-*-*)
# Target: AVR
gdb_target_obs="avr-tdep.o"
- gdb_sim=../sim/avr/libsim.a
;;
bfin-*-*linux*)
# Target: Blackfin Linux
gdb_target_obs="bfin-tdep.o bfin-linux-tdep.o linux-tdep.o"
- gdb_sim=../sim/bfin/libsim.a
;;
bfin-*-*)
# Target: Blackfin processor
gdb_target_obs="bfin-tdep.o"
- gdb_sim=../sim/bfin/libsim.a
;;
bpf-*-*)
# Target: eBPF
gdb_target_obs="bpf-tdep.o"
- gdb_sim=../sim/bpf/libsim.a
;;
cris*)
@@ -235,18 +230,15 @@ csky*-*-*)
frv-*-*)
# Target: Fujitsu FRV processor
gdb_target_obs="frv-tdep.o frv-linux-tdep.o linux-tdep.o solib-frv.o"
- gdb_sim=../sim/frv/libsim.a
;;
moxie-*-elf | moxie-*-moxiebox | moxie-*-rtems*)
gdb_target_obs="moxie-tdep.o"
- gdb_sim=../sim/moxie/libsim.a
;;
h8300-*-*)
# Target: H8300 processor
gdb_target_obs="h8300-tdep.o"
- gdb_sim=../sim/h8300/libsim.a
;;
hppa*-*-linux*)
@@ -338,20 +330,15 @@ ia64-*-*vms*)
iq2000-*-*)
gdb_target_obs="iq2000-tdep.o"
- gdb_sim=../sim/iq2000/libsim.a
;;
lm32-*-*)
gdb_target_obs="lm32-tdep.o"
- gdb_sim=../sim/lm32/libsim.a
;;
m32c-*-*)
# Target: Renesas M32C family
gdb_target_obs="m32c-tdep.o"
- # There may also be a SID / CGEN simulator for this,
- # but we do have DJ Delorie's mini-sim.
- gdb_sim=../sim/m32c/libsim.a
;;
m32r*-*-linux*)
@@ -359,18 +346,15 @@ m32r*-*-linux*)
gdb_target_obs="m32r-tdep.o m32r-linux-tdep.o \
glibc-tdep.o solib-svr4.o symfile-mem.o \
linux-tdep.o"
- gdb_sim=../sim/m32r/libsim.a
;;
m32r*-*-*)
# Target: Renesas m32r processor
gdb_target_obs="m32r-tdep.o"
- gdb_sim=../sim/m32r/libsim.a
;;
m68hc11*-*-*|m6811*-*-*)
# Target: Motorola 68HC11 processor
gdb_target_obs="m68hc11-tdep.o"
- gdb_sim=../sim/m68hc11/libsim.a
;;
m68*-*-aout* | m68*-*-coff* | m68*-*-elf* | m68*-*-rtems* | m68*-*-uclinux* | \
@@ -402,29 +386,24 @@ microblaze*-linux-*|microblaze*-*-linux*)
# Target: Xilinx MicroBlaze running Linux
gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
symfile-mem.o linux-tdep.o"
- gdb_sim=../sim/microblaze/libsim.a
;;
microblaze*-*-*)
# Target: Xilinx MicroBlaze running standalone
gdb_target_obs="microblaze-tdep.o"
- gdb_sim=../sim/microblaze/libsim.a
;;
mips*-*-linux*)
# Target: Linux/MIPS
gdb_target_obs="mips-tdep.o mips-linux-tdep.o glibc-tdep.o \
solib-svr4.o symfile-mem.o linux-tdep.o"
- gdb_sim=../sim/mips/libsim.a
;;
mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
# Target: MIPS running NetBSD
gdb_target_obs="mips-tdep.o mips-netbsd-tdep.o"
- gdb_sim=../sim/mips/libsim.a
;;
mips*-*-freebsd*)
# Target: MIPS running FreeBSD
gdb_target_obs="mips-tdep.o mips-fbsd-tdep.o"
- gdb_sim=../sim/mips/libsim.a
;;
mips64*-*-openbsd*)
# Target: OpenBSD/mips64
@@ -433,28 +412,23 @@ mips64*-*-openbsd*)
mips*-sde*-elf*)
# Target: MIPS SDE
gdb_target_obs="mips-tdep.o mips-sde-tdep.o"
- gdb_sim=../sim/mips/libsim.a
;;
mips*-*-elf)
# Target: MIPS ELF
gdb_target_obs="mips-tdep.o"
- gdb_sim=../sim/mips/libsim.a
;;
mips*-*-*)
# Target: MIPS
gdb_target_obs="mips-tdep.o"
- gdb_sim=../sim/mips/libsim.a
;;
mn10300-*-*)
# Target: Matsushita mn10300
gdb_target_obs="mn10300-tdep.o"
- gdb_sim=../sim/mn10300/libsim.a
;;
msp430-*-elf*)
gdb_target_obs="msp430-tdep.o"
- gdb_sim=../sim/msp430/libsim.a
;;
nds32*-*-elf)
@@ -477,13 +451,11 @@ or1k*-*-linux*)
# Target: OpenCores OpenRISC 1000 32-bit running Linux
gdb_target_obs="or1k-tdep.o or1k-linux-tdep.o solib-svr4.o \
symfile-mem.o glibc-tdep.o linux-tdep.o"
- gdb_sim=../sim/or1k/libsim.a
;;
or1k-*-* | or1knd-*-*)
# Target: OpenCores OpenRISC 1000 32-bit implementation bare metal
gdb_target_obs="or1k-tdep.o"
- gdb_sim=../sim/or1k/libsim.a
;;
powerpc*-*-freebsd*)
@@ -497,7 +469,6 @@ powerpc-*-netbsd* | powerpc-*-knetbsd*-gnu)
# Target: NetBSD/powerpc
gdb_target_obs="rs6000-tdep.o ppc-sysv-tdep.o ppc-netbsd-tdep.o \
ravenscar-thread.o ppc-ravenscar-thread.o"
- gdb_sim=../sim/ppc/libsim.a
;;
powerpc-*-openbsd*)
# Target: OpenBSD/powerpc
@@ -518,7 +489,6 @@ powerpc*-*-linux*)
ravenscar-thread.o ppc-ravenscar-thread.o \
linux-record.o \
arch/ppc-linux-common.o"
- gdb_sim=../sim/ppc/libsim.a
;;
powerpc-*-lynx*178)
# Target: PowerPC running Lynx178.
@@ -530,7 +500,6 @@ powerpc*-*-*)
# Target: PowerPC running eabi
gdb_target_obs="rs6000-tdep.o ppc-sysv-tdep.o solib-svr4.o \
ravenscar-thread.o ppc-ravenscar-thread.o"
- gdb_sim=../sim/ppc/libsim.a
;;
s390*-*-linux*)
@@ -553,19 +522,16 @@ riscv*-*-linux*)
riscv*-*-*)
# Target: RISC-V architecture
gdb_target_obs=""
- gdb_sim=../sim/riscv/libsim.a
;;
rl78-*-elf)
# Target: Renesas rl78
gdb_target_obs="rl78-tdep.o"
- gdb_sim=../sim/rl78/libsim.a
;;
rx-*-elf)
# Target: Renesas RX
gdb_target_obs="rx-tdep.o"
- gdb_sim=../sim/rx/libsim.a
;;
score-*-*)
@@ -578,12 +544,10 @@ sh*-*-linux*)
gdb_target_obs="sh-tdep.o sh-linux-tdep.o \
solib-svr4.o symfile-mem.o \
glibc-tdep.o linux-tdep.o"
- gdb_sim=../sim/sh/libsim.a
;;
sh*-*-netbsd* | sh*-*-knetbsd*-gnu)
# Target: NetBSD/sh
gdb_target_obs="sh-tdep.o sh-netbsd-tdep.o"
- gdb_sim=../sim/sh/libsim.a
;;
sh*-*-openbsd*)
# Target: OpenBSD/sh
@@ -592,7 +556,6 @@ sh*-*-openbsd*)
sh*)
# Target: Embedded Renesas Super-H processor
gdb_target_obs="sh-tdep.o"
- gdb_sim=../sim/sh/libsim.a
;;
sparc-*-linux*)
@@ -653,7 +616,6 @@ sparc-*-*)
# Target: SPARC
gdb_target_obs="sparc-tdep.o \
ravenscar-thread.o sparc-ravenscar-thread.o"
- gdb_sim=../sim/erc32/libsim.a
;;
sparc64-*-*)
# Target: UltraSPARC
@@ -691,13 +653,11 @@ xstormy16-*-*)
ft32-*-elf)
gdb_target_obs="ft32-tdep.o"
- gdb_sim=../sim/ft32/libsim.a
;;
v850*-*-elf | v850*-*-rtems*)
# Target: NEC V850 processor
gdb_target_obs="v850-tdep.o"
- gdb_sim=../sim/v850/libsim.a
;;
vax-*-netbsd* | vax-*-knetbsd*-gnu)
@@ -773,6 +733,41 @@ esac
gdb_target_obs="${cpu_obs} ${os_obs} ${gdb_target_obs}"
+# Get the sim settings.
+# NB: Target matching is aligned with sim/configure.ac. Changes must be kept
+# in sync with that file.
+
+case "${targ}" in
+arm*-*-*) gdb_sim=arm ;;
+avr*-*-*) gdb_sim=avr ;;
+bfin-*-*) gdb_sim=bfin ;;
+bpf-*-*) gdb_sim=bpf ;;
+frv-*-*) gdb_sim=frv ;;
+ft32-*-*) gdb_sim=ft32 ;;
+h8300*-*-*) gdb_sim=h8300 ;;
+iq2000-*-*) gdb_sim=iq2000 ;;
+lm32-*-*) gdb_sim=lm32 ;;
+m32c-*-*) gdb_sim=m32c ;;
+m32r-*-*) gdb_sim=m32r ;;
+m68hc11-*-*|m6811-*-*) gdb_sim=m68hc11 ;;
+microblaze*-*-*) gdb_sim=microblaze ;;
+mips*-*-*) gdb_sim=mips ;;
+mn10300*-*-*) gdb_sim=mn10300 ;;
+moxie-*-*) gdb_sim=moxie ;;
+msp430*-*-*) gdb_sim=msp430 ;;
+or1k*-*-*) gdb_sim=or1k ;;
+powerpc*-*-*) gdb_sim=ppc ;;
+riscv*-*-*) gdb_sim=riscv ;;
+rl78-*-*) gdb_sim=rl78 ;;
+rx-*-*) gdb_sim=rx ;;
+sh*-*-*) gdb_sim=sh ;;
+sparc-*-*) gdb_sim=erc32 ;;
+v850*-*-*) gdb_sim=v850 ;;
+esac
+if test "x$gdb_sim" != "x"; then
+ gdb_sim="../sim/${gdb_sim}/libsim.a"
+fi
+
# map target onto default OS ABI
case "${targ}" in
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] gdb: aarch64: enable sim integration
2021-08-19 21:23 [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
@ 2021-08-19 21:23 ` Mike Frysinger
2021-09-07 14:39 ` Simon Marchi
2021-08-19 21:23 ` [PATCH 3/4] gdb: cris: " Mike Frysinger
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Mike Frysinger @ 2021-08-19 21:23 UTC (permalink / raw)
To: gdb-patches
The sim side is already ready to go for aarch64, so wire it up.
---
gdb/configure.tgt | 1 +
1 file changed, 1 insertion(+)
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index b5259dfbc762..55ae7541b619 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -738,6 +738,7 @@ gdb_target_obs="${cpu_obs} ${os_obs} ${gdb_target_obs}"
# in sync with that file.
case "${targ}" in
+aarch64*-*-*) gdb_sim=aarch64 ;;
arm*-*-*) gdb_sim=arm ;;
avr*-*-*) gdb_sim=avr ;;
bfin-*-*) gdb_sim=bfin ;;
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/4] gdb: cris: enable sim integration
2021-08-19 21:23 [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
2021-08-19 21:23 ` [PATCH 2/4] gdb: aarch64: enable sim integration Mike Frysinger
@ 2021-08-19 21:23 ` Mike Frysinger
2021-09-07 14:40 ` Simon Marchi
2021-08-19 21:23 ` [PATCH 4/4] sim: update configure target list Mike Frysinger
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Mike Frysinger @ 2021-08-19 21:23 UTC (permalink / raw)
To: gdb-patches
The sim side is already ready to go for cris, so wire it up.
---
gdb/configure.tgt | 1 +
1 file changed, 1 insertion(+)
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index 55ae7541b619..c678027faef4 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -743,6 +743,7 @@ arm*-*-*) gdb_sim=arm ;;
avr*-*-*) gdb_sim=avr ;;
bfin-*-*) gdb_sim=bfin ;;
bpf-*-*) gdb_sim=bpf ;;
+cris-*-*|cris32-*-*) gdb_sim=cris ;;
frv-*-*) gdb_sim=frv ;;
ft32-*-*) gdb_sim=ft32 ;;
h8300*-*-*) gdb_sim=h8300 ;;
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/4] sim: update configure target list
2021-08-19 21:23 [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
2021-08-19 21:23 ` [PATCH 2/4] gdb: aarch64: enable sim integration Mike Frysinger
2021-08-19 21:23 ` [PATCH 3/4] gdb: cris: " Mike Frysinger
@ 2021-08-19 21:23 ` Mike Frysinger
2021-09-04 1:12 ` [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
2021-09-07 14:39 ` Simon Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Mike Frysinger @ 2021-08-19 21:23 UTC (permalink / raw)
To: gdb-patches
Fix sorting of the list, and update the globs to match the list used
in gdb's configure script.
---
sim/configure | 42 +++++++++++++++++++++---------------------
sim/configure.ac | 11 +++++++----
2 files changed, 28 insertions(+), 25 deletions(-)
diff --git a/sim/configure b/sim/configure
index 8dec72cf3b40..c1db1b66e1dd 100755
--- a/sim/configure
+++ b/sim/configure
@@ -867,8 +867,8 @@ ac_subdirs_all='bpf
mips
mn10300
or1k
-riscv
ppc
+riscv
v850'
# Initialize some variables set by options.
@@ -14028,7 +14028,7 @@ subdirs="$subdirs bpf"
esac
case "${targ}" in
- all|microblaze-*-*)
+ all|microblaze*-*-*)
if test "${targ}" = "${target}"; then
SIM_PRIMARY_TARGET=microblaze
fi
@@ -14112,7 +14112,7 @@ subdirs="$subdirs bpf"
esac
case "${targ}" in
- all|or1k-*-* | or1knd-*-*)
+ all|or1k*-*-*)
if test "${targ}" = "${target}"; then
SIM_PRIMARY_TARGET=or1k
fi
@@ -14123,6 +14123,21 @@ subdirs="$subdirs bpf"
+ ;;
+ esac
+
+ case "${targ}" in
+ all|powerpc*-*-*)
+ if test "${targ}" = "${target}"; then
+ SIM_PRIMARY_TARGET=ppc
+ fi
+ subdirs="$subdirs ppc"
+
+
+ ac_config_commands="$ac_config_commands depdir-ppc"
+
+
+
;;
esac
@@ -14214,7 +14229,7 @@ subdirs="$subdirs bpf"
esac
case "${targ}" in
- all|sparc-*-rtems*|sparc-*-elf*)
+ all|sparc-*-*)
if test "${targ}" = "${target}"; then
SIM_PRIMARY_TARGET=erc32
fi
@@ -14228,21 +14243,6 @@ subdirs="$subdirs bpf"
- ;;
- esac
-
- case "${targ}" in
- all|powerpc*-*-*)
- if test "${targ}" = "${target}"; then
- SIM_PRIMARY_TARGET=ppc
- fi
- subdirs="$subdirs ppc"
-
-
- ac_config_commands="$ac_config_commands depdir-ppc"
-
-
-
;;
esac
@@ -15882,6 +15882,7 @@ do
"msp430/Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS msp430/Makefile" ;;
"depdir-msp430") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-msp430" ;;
"depdir-or1k") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-or1k" ;;
+ "depdir-ppc") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-ppc" ;;
"pru/Makefile.sim") CONFIG_FILES="$CONFIG_FILES pru/Makefile.sim:pru/Makefile.in" ;;
"pru/Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS pru/Makefile" ;;
"depdir-pru") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-pru" ;;
@@ -15898,7 +15899,6 @@ do
"erc32/Makefile.sim") CONFIG_FILES="$CONFIG_FILES erc32/Makefile.sim:erc32/Makefile.in" ;;
"erc32/Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS erc32/Makefile" ;;
"depdir-erc32") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-erc32" ;;
- "depdir-ppc") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-ppc" ;;
"depdir-v850") CONFIG_COMMANDS="$CONFIG_COMMANDS depdir-v850" ;;
"example-synacor/Makefile.sim") CONFIG_FILES="$CONFIG_FILES example-synacor/Makefile.sim:example-synacor/Makefile.in" ;;
"example-synacor/Makefile") CONFIG_COMMANDS="$CONFIG_COMMANDS example-synacor/Makefile" ;;
@@ -17483,6 +17483,7 @@ $as_echo X"$file" |
;;
"depdir-msp430":C) $SHELL $ac_aux_dir/mkinstalldirs msp430/$DEPDIR ;;
"depdir-or1k":C) $SHELL $ac_aux_dir/mkinstalldirs or1k/$DEPDIR ;;
+ "depdir-ppc":C) $SHELL $ac_aux_dir/mkinstalldirs ppc/$DEPDIR ;;
"pru/Makefile":C) sed -n \
-e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ {
/^srcdir = / s:$:/pru:
@@ -17549,7 +17550,6 @@ $as_echo X"$file" |
rm -f erc32/Makesim1.tmp erc32/Makesim2.tmp
;;
"depdir-erc32":C) $SHELL $ac_aux_dir/mkinstalldirs erc32/$DEPDIR ;;
- "depdir-ppc":C) $SHELL $ac_aux_dir/mkinstalldirs ppc/$DEPDIR ;;
"depdir-v850":C) $SHELL $ac_aux_dir/mkinstalldirs v850/$DEPDIR ;;
"example-synacor/Makefile":C) sed -n \
-e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ {
diff --git a/sim/configure.ac b/sim/configure.ac
index 098d88bc01ef..5d36e5556d34 100644
--- a/sim/configure.ac
+++ b/sim/configure.ac
@@ -107,6 +107,9 @@ dnl WHEN ADDING ENTRIES TO THIS MATRIX:
dnl Make sure that the left side always has two dashes. Otherwise you can get
dnl spurious matches. Even for unambiguous cases, do this as a convention, else
dnl the table becomes a real mess to understand and maintain.
+dnl
+dnl NB: Target matching is aligned with gdb/configure.tgt. Changes must be kept
+dnl in sync with that file.
if test "${enable_sim}" != no; then
sim_igen=no
for targ in `echo $target $enable_targets | sed 's/,/ /g'`
@@ -128,19 +131,19 @@ if test "${enable_sim}" != no; then
SIM_TARGET([m32r-*-*], [m32r])
SIM_TARGET([m68hc11-*-*|m6811-*-*], [m68hc11])
SIM_TARGET([mcore-*-*], [mcore])
- SIM_TARGET([microblaze-*-*], [microblaze])
+ SIM_TARGET([microblaze*-*-*], [microblaze])
SIM_TARGET([mips*-*-*], [mips], [true], [sim_igen=yes])
SIM_TARGET([mn10300*-*-*], [mn10300], [true], [sim_igen=yes])
SIM_TARGET([moxie-*-*], [moxie])
SIM_TARGET([msp430*-*-*], [msp430])
- SIM_TARGET([or1k-*-* | or1knd-*-*], [or1k], [true])
+ SIM_TARGET([or1k*-*-*], [or1k], [true])
+ SIM_TARGET([powerpc*-*-*], [ppc], [true])
SIM_TARGET([pru*-*-*], [pru])
SIM_TARGET([riscv*-*-*], [riscv], [true])
SIM_TARGET([rl78-*-*], [rl78])
SIM_TARGET([rx-*-*], [rx])
SIM_TARGET([sh*-*-*], [sh])
- SIM_TARGET([sparc-*-rtems*|sparc-*-elf*], [erc32])
- SIM_TARGET([powerpc*-*-*], [ppc], [true])
+ SIM_TARGET([sparc-*-*], [erc32])
SIM_TARGET([v850*-*-*], [v850], [true], [sim_igen=yes])
done
--
2.31.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] gdb: sim: consolidate configure settings
2021-08-19 21:23 [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
` (2 preceding siblings ...)
2021-08-19 21:23 ` [PATCH 4/4] sim: update configure target list Mike Frysinger
@ 2021-09-04 1:12 ` Mike Frysinger
2021-09-07 14:39 ` Simon Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Mike Frysinger @ 2021-09-04 1:12 UTC (permalink / raw)
To: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 153 bytes --]
any feedback on these gdb bits ? or should i consider them as part of the
sim umbrella ? MAINTAINERS talks about sim/, but not sim bits in gdb/.
-mike
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/4] gdb: sim: consolidate configure settings
2021-08-19 21:23 [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
` (3 preceding siblings ...)
2021-09-04 1:12 ` [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
@ 2021-09-07 14:39 ` Simon Marchi
4 siblings, 0 replies; 9+ messages in thread
From: Simon Marchi @ 2021-09-07 14:39 UTC (permalink / raw)
To: Mike Frysinger, gdb-patches
On 2021-08-19 5:23 p.m., Mike Frysinger via Gdb-patches wrote:
> Moving all the sim settings to one section makes it easier to track,
> and makes it easier to keep it aligned with the sim target tests.
> The gdb logic was duplicating this when handling different OS targets
> instead of having a single cpu check. Now it's more obvious that the
> sim is tied to a cpu and not related to the OS.
Sounds like a good idea, LGTM.
Simon
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/4] gdb: aarch64: enable sim integration
2021-08-19 21:23 ` [PATCH 2/4] gdb: aarch64: enable sim integration Mike Frysinger
@ 2021-09-07 14:39 ` Simon Marchi
0 siblings, 0 replies; 9+ messages in thread
From: Simon Marchi @ 2021-09-07 14:39 UTC (permalink / raw)
To: Mike Frysinger, gdb-patches
On 2021-08-19 5:23 p.m., Mike Frysinger via Gdb-patches wrote:
> The sim side is already ready to go for aarch64, so wire it up.
> ---
> gdb/configure.tgt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/gdb/configure.tgt b/gdb/configure.tgt
> index b5259dfbc762..55ae7541b619 100644
> --- a/gdb/configure.tgt
> +++ b/gdb/configure.tgt
> @@ -738,6 +738,7 @@ gdb_target_obs="${cpu_obs} ${os_obs} ${gdb_target_obs}"
> # in sync with that file.
>
> case "${targ}" in
> +aarch64*-*-*) gdb_sim=aarch64 ;;
> arm*-*-*) gdb_sim=arm ;;
> avr*-*-*) gdb_sim=avr ;;
> bfin-*-*) gdb_sim=bfin ;;
>
LGTM.
Simon
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] gdb: cris: enable sim integration
2021-08-19 21:23 ` [PATCH 3/4] gdb: cris: " Mike Frysinger
@ 2021-09-07 14:40 ` Simon Marchi
2021-09-08 2:33 ` Mike Frysinger
0 siblings, 1 reply; 9+ messages in thread
From: Simon Marchi @ 2021-09-07 14:40 UTC (permalink / raw)
To: Mike Frysinger, gdb-patches
On 2021-08-19 5:23 p.m., Mike Frysinger via Gdb-patches wrote:
> The sim side is already ready to go for cris, so wire it up.
> ---
> gdb/configure.tgt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/gdb/configure.tgt b/gdb/configure.tgt
> index 55ae7541b619..c678027faef4 100644
> --- a/gdb/configure.tgt
> +++ b/gdb/configure.tgt
> @@ -743,6 +743,7 @@ arm*-*-*) gdb_sim=arm ;;
> avr*-*-*) gdb_sim=avr ;;
> bfin-*-*) gdb_sim=bfin ;;
> bpf-*-*) gdb_sim=bpf ;;
> +cris-*-*|cris32-*-*) gdb_sim=cris ;;
> frv-*-*) gdb_sim=frv ;;
> ft32-*-*) gdb_sim=ft32 ;;
> h8300*-*-*) gdb_sim=h8300 ;;
>
Any reason not to use
cris*-*-*
similar to other arches?
LGTM either way.
Simon
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/4] gdb: cris: enable sim integration
2021-09-07 14:40 ` Simon Marchi
@ 2021-09-08 2:33 ` Mike Frysinger
0 siblings, 0 replies; 9+ messages in thread
From: Mike Frysinger @ 2021-09-08 2:33 UTC (permalink / raw)
To: Simon Marchi; +Cc: gdb-patches
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On 07 Sep 2021 10:40, Simon Marchi wrote:
> On 2021-08-19 5:23 p.m., Mike Frysinger via Gdb-patches wrote:
> > The sim side is already ready to go for cris, so wire it up.
> > ---
> > gdb/configure.tgt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/gdb/configure.tgt b/gdb/configure.tgt
> > index 55ae7541b619..c678027faef4 100644
> > --- a/gdb/configure.tgt
> > +++ b/gdb/configure.tgt
> > @@ -743,6 +743,7 @@ arm*-*-*) gdb_sim=arm ;;
> > avr*-*-*) gdb_sim=avr ;;
> > bfin-*-*) gdb_sim=bfin ;;
> > bpf-*-*) gdb_sim=bpf ;;
> > +cris-*-*|cris32-*-*) gdb_sim=cris ;;
> > frv-*-*) gdb_sim=frv ;;
> > ft32-*-*) gdb_sim=ft32 ;;
> > h8300*-*-*) gdb_sim=h8300 ;;
> >
>
> Any reason not to use
>
> cris*-*-*
>
> similar to other arches?
the two cris tuples here are what's used throughout the tree. i don't have
an opinion on it in general, but having gdb match the rest of the tree seems
like the best bet. i get that earlier in this file it does "cris*". maybe
the cris maintainers want to rectify this ? :)
$ grep 'cris-[*]' configure* */configure*
configure: cris-*-* | crisv32-*-*)
configure: cris-*-* | crisv32-*-*)
configure.ac: cris-*-* | crisv32-*-*)
configure.ac: cris-*-* | crisv32-*-*)
gas/configure: cris-*-*aout*) emulation="crisaout criself" ;;
gas/configure: cris-*-*) emulation="criself crisaout" ;;
gas/configure.ac: cris-*-*aout*) emulation="crisaout criself" ;;
gas/configure.ac: cris-*-*) emulation="criself crisaout" ;;
gas/configure.tgt: cris-*-linux-* | crisv32-*-linux-*)
gas/configure.tgt: cris-*-* | crisv32-*-*) fmt=multi ;;
ld/configure.tgt:cris-*-*aout*) targ_emul=crisaout
ld/configure.tgt:cris-*-linux-* | crisv32-*-linux-*)
ld/configure.tgt:cris-*-* | crisv32-*-*) targ_emul=criself
sim/configure: all|cris-*-* | crisv32-*-*)
sim/configure.ac: SIM_TARGET([cris-*-* | crisv32-*-*], [cris])
$ grep 'cris[*]' configure* */configure*
gdb/configure.tgt:cris*)
-mike
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-09-08 2:33 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-19 21:23 [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
2021-08-19 21:23 ` [PATCH 2/4] gdb: aarch64: enable sim integration Mike Frysinger
2021-09-07 14:39 ` Simon Marchi
2021-08-19 21:23 ` [PATCH 3/4] gdb: cris: " Mike Frysinger
2021-09-07 14:40 ` Simon Marchi
2021-09-08 2:33 ` Mike Frysinger
2021-08-19 21:23 ` [PATCH 4/4] sim: update configure target list Mike Frysinger
2021-09-04 1:12 ` [PATCH 1/4] gdb: sim: consolidate configure settings Mike Frysinger
2021-09-07 14:39 ` Simon Marchi
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