From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 40959 invoked by alias); 27 Jun 2018 13:17:28 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 40029 invoked by uid 89); 27 Jun 2018 13:17:27 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=AWL,BAYES_00,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx3-rdu2.redhat.com (HELO mx1.redhat.com) (66.187.233.73) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 27 Jun 2018 13:17:26 +0000 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 72419857AB; Wed, 27 Jun 2018 13:17:24 +0000 (UTC) Received: from [127.0.0.1] (ovpn04.gateway.prod.ext.ams2.redhat.com [10.39.146.4]) by smtp.corp.redhat.com (Postfix) with ESMTP id CDF6F21565E1; Wed, 27 Jun 2018 13:17:23 +0000 (UTC) Subject: Re: [PATCH] Fix Cell debugging regression (Re: [PATCH] Use thread_info and inferior pointers more throughout) To: Ulrich Weigand References: <20180627131239.5F0D5D801C0@oc3748833570.ibm.com> Cc: Tom Tromey , gdb-patches@sourceware.org From: Pedro Alves Message-ID: <393b6452-79f3-4b87-d9e2-15fbe2125dc8@redhat.com> Date: Wed, 27 Jun 2018 13:17:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.8.0 MIME-Version: 1.0 In-Reply-To: <20180627131239.5F0D5D801C0@oc3748833570.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2018-06/txt/msg00644.txt.bz2 On 06/27/2018 02:12 PM, Ulrich Weigand wrote: > Pedro Alves wrote: > >>> The change above switches the behavior to use the SPU architecture >>> if GDB happens to interrupt SPU code. This is wrong and causes >>> internal GDB errors pretty much instantly when starting an SPU ... >> Sorry, missed that. Some comments here would be helpful. > > Agreed. :-) > >> gdb/ChangeLog: >> 2018-06-27 Pedro Alves >> >> * proc-service.c (ps_lgetregs, ps_lsetregs, ps_lgetfpregs) >> (ps_lsetfpregs): Use get_thread_main_regcache. >> * regcache.c (get_thread_main_regcache): Define. >> * regcache.h (get_thread_main_regcache): Declare. > > This looks good to me as far as the architecture is concerned. > > In the meantime I also noticed another potential issue (which is > not related to multi-arch at all): > >> ps_err_e >> ps_lgetregs (struct ps_prochandle *ph, lwpid_t lwpid, prgregset_t gregset) >> { >> - ptid_t ptid = ptid_build (ptid_get_pid (ph->ptid), lwpid, 0); >> - struct regcache *regcache >> - = get_thread_arch_regcache (ptid, target_gdbarch ()); >> + struct regcache *regcache = get_thread_regcache (ph->thread); > > This change also assumes that ph->thread is the same thread > as the one indicated by lwpid. Looking at the callers of the > various libthread_db routines that might result in a callback > to the ps_...regs routines, it is not immediately obvious to > me that this is actually true. Are you sure this can never > be called to look up registers of another thread? Argh, no, I completely missed that. Let me take a better look. Thanks, Pedro Alves