Re: [PATCH 3/8] start/stop btrace with coresight etm and parse etm buffer. nat independant

[Zied Guermazi <zied.guermazi@trande.de>]

Hello Markus

the code was amended according to the outcome of the discussion. it 
works fine. There is no blocking points anymore.

I am running the testsuite on i686, armv7 and armv8, to check any 
possible regression. it takes long time on ARMv7. I guess it will finish 
by the evening. I will send the patch suite after checking the result 
(if everything goes fine)

Kind Regards

Zied Guermazi

On 29.03.21 16:01, Metzger, Markus T wrote:
>
> Hello Zied,
>
> >> For the point concerning the use of a vector of registers in btrace_insn:
>
> >> a vector of registers is added to the btrace_insn structure. This adds 
> an overhead of 3 pointers when the vector is empty. It will be the 
> overhead when not used (intel pt). I think this should be acceptable.
>
> >> 
>
> >> That's doubling the current size; tripling it if we declared ICLASS 
> 8b (as it
>
> >> should be).  I don't think that's acceptable.
>
> > 
>
> > on ARMv7 this is need for all instructions, to allow step and next to 
> set the breakpoints properly in the code.
>
> > 
>
> >> Is this to distinguish ARM and Thumb modes?  How would the information
>
> >> be used?
>
> > [Zied] let me give you a better insight on this topic to find a better solution:
>
> > this information is needed for two purposes:
>
> I believe this was discussed in 
> https://sourceware.org/pipermail/gdb/2021-March/049293.html.
>
> Is there anything left to discuss?
>
> Regards,
>
> Markus.
>
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