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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Jul 2023 09:28:22.9213 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7dadc8bc-844f-4341-1ffa-08db8cf17ddf X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT049.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6205 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,GIT_PATCH_0,KAM_DMARC_NONE,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 7/24/23 17:19, Thiago Jung Bauermann wrote: > > Luis Machado via Gdb-patches writes: > >> This is a patch in preparation to upcoming patches enabling SME support. It >> attempts to simplify the gdb/gdbserver shared interface used to read/write >> SVE registers. >> >> Where the current code makes use of unique_ptr, allocating a new buffer by >> hand and passing a buffer around, this patch makes that code use >> gdb::byte_vector and passes a reference to this byte vector to the functions, >> allowing the functions to have ready access to the size of the buffer. > > Nice! > >> It also shares a bit more code between gdb and gdbserver, in particular around >> handling of ptrace get/set requests for SVE. > > Also nice! > >> diff --git a/gdb/nat/aarch64-scalable-linux-ptrace.c b/gdb/nat/aarch64-scalable-linux-ptrace.c >> index cc43f510892..192eebcda19 100644 >> --- a/gdb/nat/aarch64-scalable-linux-ptrace.c >> +++ b/gdb/nat/aarch64-scalable-linux-ptrace.c >> @@ -120,28 +120,44 @@ aarch64_sve_set_vq (int tid, struct reg_buffer_common *reg_buf) >> >> /* See nat/aarch64-scalable-linux-ptrace.h. */ >> >> -std::unique_ptr >> -aarch64_sve_get_sveregs (int tid) >> +gdb::byte_vector >> +aarch64_fetch_sve_regset (int tid) >> { >> - struct iovec iovec; >> uint64_t vq = aarch64_sve_get_vq (tid); >> >> if (vq == 0) >> - perror_with_name (_("Unable to fetch SVE register header")); >> + perror_with_name (_("Unable to fetch SVE vector length")); >> >> /* A ptrace call with NT_ARM_SVE will return a header followed by either a >> dump of all the SVE and FP registers, or an fpsimd structure (identical to >> the one returned by NT_FPREGSET) if the kernel has not yet executed any >> SVE code. Make sure we allocate enough space for a full SVE dump. */ >> >> - iovec.iov_len = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE); >> - std::unique_ptr buf (new gdb_byte[iovec.iov_len]); >> - iovec.iov_base = buf.get (); >> + gdb::byte_vector sve_state (SVE_PT_SIZE (vq, SVE_PT_REGS_SVE), 0); >> + >> + struct iovec iovec; >> + iovec.iov_base = sve_state.data (); >> + iovec.iov_len = sve_state.size (); >> >> if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_SVE, &iovec) < 0) >> perror_with_name (_("Unable to fetch SVE registers")); >> >> - return buf; >> + return sve_state; >> +} >> + >> +/* See nat/aarch64-scalable-linux-ptrace.h. */ >> + >> +bool > > This function always returns true, and its only caller doesn't use the > return value. Should it return void instead? > I think it is reasonable for now. An earlier iteration of this patch used to let an error be handled by the callers, and I changed that. I'll get it updated, and also change the same for the za regset. >> +aarch64_store_sve_regset (int tid, const gdb::byte_vector &sve_state) >> +{ >> + struct iovec iovec; >> + iovec.iov_base = (void *) sve_state.data (); > > Minor nit: is the cast necessary? The code looks cleaner without it. > Also, it's not used in aarch64_fetch_sve_regset. > I don't think it is needed. Probably an artifact of when the code used unique_ptr's. >> + else >> + { >> + /* Otherwise, reformat the fpsimd structure into a full SVE set, by >> + expanding the V registers (working backwards so we don't splat >> + registers before they are copied) and using zero for everything >> + else. >> + Note that enough space for a full SVE dump was originally allocated >> + for base. */ >> + >> + header->flags |= SVE_PT_REGS_SVE; >> + header->size = SVE_PT_SIZE (vq, SVE_PT_REGS_SVE); >> + >> + memcpy (base + SVE_PT_SVE_FPSR_OFFSET (vq), &fpsimd->fpsr, >> + sizeof (uint32_t)); >> + memcpy (base + SVE_PT_SVE_FPCR_OFFSET (vq), &fpsimd->fpcr, >> + sizeof (uint32_t)); >> + >> + for (int i = AARCH64_SVE_Z_REGS_NUM; i >= 0 ; i--) > > Shouldn't i start from AARCH64_SVE_Z_REGS_NUM - 1? If this is correct, a > comment explaining why would be helpful. > Yes, it should. It seems this slipped through from the previous code. I'll fix it while at it. Thanks for spotting it!