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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 May 2024 14:44:10.3764 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 834be159-3620-4893-1ec0-08dc6ea42807 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A6C.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6168 X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi, On 5/7/24 15:29, Willgerodt, Felix wrote: >> -----Original Message----- >> From: Gdb-patches > bounces+felix.willgerodt=intel.com@sourceware.org> On Behalf Of Thiago Jung >> Bauermann via Gdb-patches >> Sent: Montag, 30. Januar 2023 05:45 >> To: gdb-patches@sourceware.org >> Cc: Thiago Jung Bauermann >> Subject: [PATCH v3 0/8] gdbserver improvements for AArch64 SVE support >> >> Hello, >> >> This is version 3 of the patch series adding support to gdbserver for >> inferiors that change the SVE vector length at runtime. This is already >> supported by GDB, but not by gdbserver. Version 2 was posted here: >> >> https://inbox.sourceware.org/gdb-patches/20221126020452.1686509-1- >> thiago.bauermann@linaro.org/ >> >> This version incorporates the review comments from v2 (thanks!). The >> biggest change is that it implements Simon's idea¹: >> >>> If it's the case, that we need to extend the RSP to allow fetching >>> per-thread tdesc, here's the idea I had in mind for a while, to avoid >>> adding too much overhead. Stop replies and the qXfer:threads:read reply >>> could include a per-thread tdesc identifier. That tdesc identifier >>> would be something short, either an incrementing number, or some kind of >>> hash of the tdesc. It would be something opaque chosen by the stub. A >>> new packet would be introduced to allow GDB to request the XML given >>> that ID. On the GDB side, GDB would request the XML when encountering a >>> tdesc ID it doesn't know about, and then cache the result. >> >> The only difference from the above in this series is that instead of >> creating a new packet to allow GDB to request the XML given the ID, I'm >> extending the qXfer:features:read request: GDB can send "target-id-%u.xml" >> as the annex, where %u is the target description ID. Please let me know if >> you think a separate packet would be better. The remote protocol changes >> are documented in patch 5. >> >> I had to drop the Reviewed-by tags from some patches because they have some >> significant changes from the version that was reviewed. >> >> There's also a new testcase exercising the case of an inferior's thread >> changing its SVE vector length. The previous version of this series failed >> the testcase, but this one passes it. >> >> With this series applied, gdb.arch/aarch64-sve.exp passes all tests on >> extended-remote aarch64-linux. Without them, it fails tests after the >> testcase changes the vector length. >> >> Tested on native and extended-remote aarch64-linux, x86_64-linux and >> armv7l-linux-gnueabihf (the last one on QEMU TCG). >> >> ¹ https://inbox.sourceware.org/gdb-patches/559069a3-f3ce-2059-bf4a- >> 44add43979f7@simark.ca/ > > Hi Thiago, Hi Luis, > > I wonder what happened to this series. Do you plan to revive it at some > point? I realise this isn't an easy series to land. Tough it would be great > to have in my view. I think it is an essential piece to make gdbserver work correctly for both SVE and SME (and similar features on other architectures), as well as enabling remote debugging stubs to support vector size changes mid-execution. Thiago was the last one to touch this code, so he may have better information on future plans. Unfortunately I don't have cycles to get back to this particular feature at the moment, but I'd gladly review future iterations of the series. > > Regards, > Felix > > > Intel Deutschland GmbH > Registered Address: Am Campeon 10, 85579 Neubiberg, Germany > Tel: +49 89 99 8853-0, www.intel.de > Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva > Chairperson of the Supervisory Board: Nicole Lau > Registered Office: Munich > Commercial Register: Amtsgericht Muenchen HRB 186928