From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20768 invoked by alias); 11 Nov 2013 10:12:01 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 20756 invoked by uid 89); 11 Nov 2013 10:12:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.7 required=5.0 tests=AWL,BAYES_40,GARBLED_BODY,RDNS_NONE autolearn=no version=3.3.2 X-HELO: relay1.mentorg.com Received: from Unknown (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Nov 2013 10:11:25 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1VfoSb-0007Vm-S4 from Yao_Qi@mentor.com ; Mon, 11 Nov 2013 02:11:09 -0800 Received: from SVR-ORW-FEM-05.mgc.mentorg.com ([147.34.97.43]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Mon, 11 Nov 2013 02:11:09 -0800 Received: from qiyao.dyndns.org (147.34.91.1) by svr-orw-fem-05.mgc.mentorg.com (147.34.97.43) with Microsoft SMTP Server id 14.2.247.3; Mon, 11 Nov 2013 02:11:09 -0800 Message-ID: <5280ACE9.9050308@codesourcery.com> Date: Mon, 11 Nov 2013 10:53:00 -0000 From: Yao Qi User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130110 Thunderbird/17.0.2 MIME-Version: 1.0 To: Omair Javaid CC: , Patch Tracking Subject: Re: [PATCH 1/2] GDB process record and reverse debugging improvements for arm*-linux* References: <526884D5.309@codesourcery.com> <527C5856.50500@linaro.org> In-Reply-To: <527C5856.50500@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2013-11/txt/msg00284.txt.bz2 Patch looks good to me, and you still need a maintainer's approval. Some of the comments are too long. Please make sure they don't exceed the limitation (around 74 characters should be fine). On 11/08/2013 11:19 AM, Omair Javaid wrote: > +/* Handler for thumb2 ld/st dual, ld/st exclusive, table branch > instructions. */ > + here. > +static int > +thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r) > +{ > + struct regcache *reg_cache = thumb2_insn_r->regcache; > + .... > + > +/* Decodes thumb2 instruction type and return an instruction id. */ > + > +static unsigned int > +thumb2_record_decode_inst_id (uint32_t thumb2_insn) > +{ > + uint32_t op = 0; > + uint32_t op1 = 0; > + uint32_t op2 = 0; > + > + op = bit (thumb2_insn, 15); > + op1 = bits (thumb2_insn, 27, 28); > + op2 = bits (thumb2_insn, 20, 26); > + > + if (op1 == 0x01) > + { > + if (!(op2 & 0x64 )) > + { > + /* Load/store multiple instruction. */ > + return 0; > + } > + else if (!((op2 & 0x64) ^ 0x04)) > + { > + /* Load/store dual, load/store exclusive, table branch > instruction. */ and here. > + return 1; > + } > + else if (!((op2 & 0x20) ^ 0x20)) > + { > + /* Data-processing (shifted register). */ > + return 2; > + } > + else if (op2 & 0x40) > + { > + /* Co-processor instructions. */ > + return 3; > + } > + } > + else if (op1 == 0x02) > + { > + if (op) > + { > + /* Branches and miscellaneous control instructions. */ > + return 6; > + } > + else if (op2 & 0x20) > + { > + /* Data-processing (plain binary immediate) instruction. */ > + return 5; > + } > + else > + { > + /* Data-processing (modified immediate). */ > + return 4; > + } > + } > + else if (op1 == 0x03) > + { > + if (!(op2 & 0x71 )) > + { > + /* Store single data item. */ > + return 7; > + } > + else if (!((op2 & 0x71) ^ 0x10)) > + { > + /* Advanced SIMD element or structure load/store > instructions. */ here. > + return 8; > + } > + else if (!((op2 & 0x67) ^ 0x01)) > + { > + /* Load byte, memory hints instruction. */ > + return 9; > + } > + else if (!((op2 & 0x67) ^ 0x03)) > + { > + /* Load halfword, memory hints instruction. */ > + return 10; > + } > + else if (!((op2 & 0x67) ^ 0x05)) > + { > + /* Load word instruction. */ > + return 11; > + } > + else if (!((op2 & 0x70) ^ 0x20)) > + { > + /* Data-processing (register) instruction. */ > + return 12; > + } > + else if (!((op2 & 0x78) ^ 0x30)) > + { > + /* Multiply, multiply accumulate, absolute difference > instruction. */ here. > + return 13; > + } > + else if (!((op2 & 0x78) ^ 0x38)) > + { > + /* Long multiply, long multiply accumulate, and divide. */ > + return 14; > + } > + else if (op2 & 0x40) > + { > + /* Co-processor instructions. */ > + return 15; > + } > + } > + > + return -1; > +} > > /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 > on success > and positive val on fauilure. */ > @@ -12452,7 +13034,7 @@ decode_insn (insn_decode_record *arm_rec > arm_record_ld_st_reg_offset, /* 011. */ > arm_record_ld_st_multiple, /* 100. */ > arm_record_b_bl, /* 101. */ > - arm_record_coproc, /* 110. */ > + arm_record_unsupported_insn, /* 110. */ > arm_record_coproc_data_proc /* 111. */ > }; > > @@ -12469,6 +13051,27 @@ decode_insn (insn_decode_record *arm_rec > thumb_record_branch /* 111. */ > }; > > + /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb > instruction. */ here. -- Yao (齐尧)