From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32629 invoked by alias); 23 Dec 2013 17:39:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 32619 invoked by uid 89); 23 Dec 2013 17:39:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 23 Dec 2013 17:39:03 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 23 Dec 2013 17:39:01 +0000 Received: from [10.1.201.52] ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 23 Dec 2013 17:39:01 +0000 Message-ID: <52B87534.80300@arm.com> Date: Mon, 23 Dec 2013 17:39:00 -0000 From: Yufeng Zhang User-Agent: Mozilla/5.0 (X11; Linux i686 on x86_64; rv:8.0) Gecko/20111105 Thunderbird/8.0 MIME-Version: 1.0 To: Pedro Alves CC: Andrew Pinski , "gdb-patches@sourceware.org" , Andrew Pinski Subject: Re: [PATCH] AARCH64: Change cpsr type to be 64bit. References: <1387393684-29115-1-git-send-email-apinski@cavium.com> <52B482C8.7000203@redhat.com> In-Reply-To: <52B482C8.7000203@redhat.com> X-MC-Unique: 113122317390100501 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2013-12/txt/msg00889.txt.bz2 On 12/20/13 17:47, Pedro Alves wrote: > On 12/18/2013 07:08 PM, Andrew Pinski wrote: >> As mentioned in http://www.spinics.net/lists/arm-kernel/msg290896.html, = we should change gdb's notion of cpsr to be 64bit. >> >> OK? Build and tested for aarch64-linux-gnu with no regressions. >> I also double checked to make sure that what is passed down from the ker= nel (via sigcontext), is the full 64bit. > > With this, the register will be exposed as 64-bit to the > user. Is that desirable? The fact that the original > description used 32-bit makes it sounds like it's not. > What's the real register width at the (asm visible) > machine level? There is no access to CPSR as a single register in AArch64 (*).=20 Instead, process states can be accessed/modified via system=20 instructions. I guess the kernel synthesizes one CPSR register, so if=20 kernel defines it as a 64-bit register, it is reasonable for gdb to=20 treat it of the same size as well. Yufeng Reference: * ARMv8 Instruction Set Overview - Chapter 3 A64 Overview