From: Pierre Langlois <pierre.langlois@arm.com>
To: Yao Qi <qiyaoltc@gmail.com>
Cc: pierre.langlois@arm.com,
"gdb-patches@sourceware.org" <gdb-patches@sourceware.org>
Subject: Re: [PATCH] [AArch64] Mark single precision pseudo registers unavailable if invalid
Date: Thu, 16 Jul 2015 09:09:00 -0000 [thread overview]
Message-ID: <55A774BA.1010708@arm.com> (raw)
In-Reply-To: <55A670FF.7010805@gmail.com>
On 15/07/15 15:41, Yao Qi wrote:
> On 15/07/15 15:00, Yao Qi wrote:
>> ... when I read your patch, I am wondering why does aarch64 implement
>> gdbarch method pseudo_register_read_value rather than
>> pseudo_register_read. If we implement the pseudo_register_read, the
>> caller will mark the value unavailable according to its return value.
>> pseudo_register_read_value was added to handle partially available
>> registers byhttps://sourceware.org/ml/gdb-patches/2011-07/msg00351.html
>> but I don't think of a case that some aarch64 register is partially
>> available. Maybe, another fix to this problem is to implement
>> pseudo_register_read instead of pseudo_register_read_value.
Yes, it makes sense to me. I don't think we should have partially
available V registers in any cases. For example, reading the S0 register
just ignores the top-level bits of the Q0 register, but they are still
available to read through Q0. And writing to S0 will clear the top-level
bits of Q0. As it is implemented in aarch64_pseudo_write.
>
> To be clear, your patch can be pushed in, as it is correct and fixes
> fails in tests. We can discuss and implement pseudo_register_read
> rather than pseudo_register_read_value for aarch64 later in the
> follow-up patch.
>
OK, I'll push it in and make sure pseudo_register_read works as expected in
a follow-up patch.
Thanks,
Pierre
prev parent reply other threads:[~2015-07-16 9:09 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-15 10:53 Pierre Langlois
2015-07-15 14:01 ` Yao Qi
2015-07-15 14:41 ` Yao Qi
2015-07-16 9:09 ` Pierre Langlois [this message]
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