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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT008.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8324 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, BODY_8BITS, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Oct 2022 17:43:28 -0000 On 10/4/22 18:08, John Baldwin wrote: > On 10/4/22 1:43 AM, Luis Machado via Gdb-patches wrote: >> On 10/3/22 20:16, Pedro Alves wrote: >>> On 2022-09-20 1:30 p.m., Luis Machado via Gdb-patches wrote: >>> >>>> diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h >>>> index 36757493406..74a6ba93bc7 100644 >>>> --- a/gdb/arch/arm.h >>>> +++ b/gdb/arch/arm.h >>>> @@ -44,11 +44,6 @@ enum gdb_regnum { >>>>      ARM_SP_REGNUM = 13,        /* Contains address of top of stack */ >>>>      ARM_LR_REGNUM = 14,        /* address to return to from a function call */ >>>>      ARM_PC_REGNUM = 15,        /* Contains program counter */ >>>> -  /* F0..F7 are the fp registers for the (obsolete) FPA architecture.  */ >>> >>> Shouldn't we leave behind a comment explaining why there's a hole between 15 and 25? >> >> I pondered about this a bit more, and I think we should close the gap and bring CPSR down to >> 16, its "natural" position. It is what linux uses for user_regs as well, in gdb/arch/arm-linux.h: >> >> /* The index to access CSPR in user_regs defined in GLIBC.  */ >> #define ARM_CPSR_GREGNUM 16 >> >>> >>> IIRC the numbers can't be changed since we need to handle the case when the target >>> doesn't send an xml tdesc, so it'd be good to help future readers understand why >>> there's a hole. >> >> That's correct. Though a 32-bit Arm target that doesn't support XML descriptions these days is not very >> common. I haven't seen one in a while. >> >> I'm willing to declare old 32-bit Arm targets that don't send XML target descriptions back as unsupported. >> >> To that effect, I suppose we should add a note to make it more explicit. >> >> More below. > > FWIW, the GDB stub in FreeBSD's kernel does not use XML target descriptions > for any architectures, but it also only tends to do GPRs and not any floating > point.  For 32-bit ARM it does not report any register values higher than > number 15 (PC), so it would not be affected by changing this. Does it care about CPSR and/or XPSR? Could you please give it a try to see if the defaults would suit it just fine? > > Do you know if LLDB supports floating-point registers on 32-bit arm as well? > The register numbers in the 'g' packet are effectively part of the protocol > shared between the two, so might be worth coording with lldb folks as well if > they support FPA? > It does seem to support FP registers, but not FPA. For example, from https://github.com/llvm-mirror/lldb/blob/master/examples/python/armv7_cortex_m_target_defintion.py: armv7_register_infos = [ { 'name':'r0' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg1' }, { 'name':'r1' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg2' }, { 'name':'r2' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg3' }, { 'name':'r3' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'arg4' }, { 'name':'r4' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r5' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r6' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r7' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'fp' }, { 'name':'r8' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r9' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r10' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r11' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'r12' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo }, { 'name':'sp' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'r13' }, { 'name':'lr' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'r14' }, { 'name':'pc' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'r15' }, { 'name':'xpsr' , 'set':0, 'bitsize':32 , 'encoding':eEncodingUint , 'format':eFormatAddressInfo, 'alt-name':'cpsr' }, ]; Also, for the SEGGER J-Link: arm David, does LLDB actively maintain register descriptions for 32-bit Arm?