From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102442 invoked by alias); 11 Dec 2015 16:11:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 102415 invoked by uid 89); 11 Dec 2015 16:11:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 X-HELO: usplmg21.ericsson.net Received: from usplmg21.ericsson.net (HELO usplmg21.ericsson.net) (198.24.6.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 11 Dec 2015 16:11:17 +0000 Received: from EUSAAHC001.ericsson.se (Unknown_Domain [147.117.188.75]) by usplmg21.ericsson.net (Symantec Mail Security) with SMTP id A5.56.32102.E95FA665; Fri, 11 Dec 2015 17:11:10 +0100 (CET) Received: from [142.133.110.95] (147.117.188.8) by smtp-am.internal.ericsson.com (147.117.188.77) with Microsoft SMTP Server id 14.3.248.2; Fri, 11 Dec 2015 11:11:12 -0500 Subject: Re: [PATCH v7.1] Support software single step on ARM in GDBServer. To: Yao Qi References: <1449583641-18156-7-git-send-email-antoine.tremblay@ericsson.com> <1449691701-11845-1-git-send-email-antoine.tremblay@ericsson.com> <8637v9qc50.fsf@gmail.com> <566AE65E.5080209@ericsson.com> <86twnpov11.fsf@gmail.com> CC: Pedro Alves , From: Antoine Tremblay Message-ID: <566AF5A0.2040606@ericsson.com> Date: Fri, 11 Dec 2015 16:11:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <86twnpov11.fsf@gmail.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2015-12/txt/msg00238.txt.bz2 On 12/11/2015 10:38 AM, Yao Qi wrote: > Antoine Tremblay writes: > >> >> I'm not sure a macro is a good thing, it often makes the code harder >> to parse for ides/emacs etc... > > Why macro is bad? > Well in my view, I write a macro when there's no other way to write what I want to write or the macro is generic enough to be used freely in many places like MAKE_THUMB_ADDR. In this case there is a way to avoid a macro, I can add a local variable with shorter name, or maybe I could just rename the original operation with : self->ops->read_mem_uint vs. ARM_READ_UINT It's still 12 more but it avoids the macro and should be short enough. How about that? >> >> And I don't think shortening the lines is a good justification in >> general for a macro. > > It is! Supposing we have a macro like this ... > > #define ARM_READ_UINT(MEMADDR, LEN, BYTE_ORDER) \ > self->ops->read_memory_unsigned_integer ((MEMADDR), (LEN), (BYTE_ORDER)) > I don't like that the macro assumes a very specific context and this context is not reflected in the name. I find it confusing if somebody saw the macro ARM_READ_UINT he might think it's possible to use as a general macro in the file but it's not. I think the best solution is to rename the ops to read_mem_uint. >> >> How about I use a function pointer variable like : >> >> ULONGEST (*read_memory_uint) (CORE_ADDR memaddr, int len, int byte_order); >> >> read_memory_uint = self->ops->read_memory_unsigned_integer; >> >> That would be already 23 shorter. >> >>>> + loc += 2; >>>> + if (!((insn1 & 0xfff0) == 0xe850 >>>> + || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040))) >>>> + return NULL; >>>> + >>>> + /* Assume that no atomic sequence is longer than "atomic_sequence_length" >>>> + instructions. */ >>>> + for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) >>>> + { >>>> + insn1 >>>> + = self->ops->read_memory_unsigned_integer (loc, 2,byte_order_for_code); >>>> + loc += 2; >>>> + >>>> + if (thumb_insn_size (insn1) != 4) >>>> + { >>>> + /* Assume that there is at most one conditional branch in the >>>> + atomic sequence. If a conditional branch is found, put a >>>> + breakpoint in its destination address. */ >>>> + if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f) >>>> + { >>>> + if (last_breakpoint > 0) >>>> + return NULL; /* More than one conditional branch found, >>>> + fallback to the standard code. */ >>>> + >>>> + breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1); >>>> + last_breakpoint++; >>>> + } >>>> + >>>> + /* We do not support atomic sequences that use any *other* >>>> + instructions but conditional branches to change the PC. >>>> + Fall back to standard code to avoid losing control of >>>> + execution. */ >>>> + else if (thumb_instruction_changes_pc (insn1)) >>>> + return NULL; >>>> + } >>>> + else >>>> + { >>>> + insn2 = self->ops->read_memory_unsigned_integer >>>> + (loc, 2, byte_order_for_code); >>> >>> Format looks wrong, multiple instances of this problem in the patch. >>> >> >> Yes actually I was not sure about that and discussed this with Pedro >> and he agreed this was ok. That's why I went with that. >> >> At some point when you have >> if >> if >> if >> long_function_name (long variable, >> >> And that does not fit you could have >> >> long_function_name ( >> long variable, ... ) >> >> or long_function_name >> (long variable, ...) >> >> or ? >> > > ... then, this problem doesn't exist at all. Isn't it better below? > > insn2 = ARM_READ_UINT (loc, 2, byte_order_for_code); >