From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 90906 invoked by alias); 25 Sep 2018 15:04:33 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 90782 invoked by uid 89); 25 Sep 2018 15:04:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy= X-HELO: prv1-mh.provo.novell.com Received: from prv1-mh.provo.novell.com (HELO prv1-mh.provo.novell.com) (137.65.248.33) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 25 Sep 2018 15:04:25 +0000 Received: from INET-PRV1-MTA by prv1-mh.provo.novell.com with Novell_GroupWise; Tue, 25 Sep 2018 09:04:24 -0600 Message-Id: <5BAA4E7302000078001EBC73@prv1-mh.provo.novell.com> Date: Tue, 25 Sep 2018 15:04:00 -0000 From: "Jan Beulich" To: , "Simon Marchi" Cc: ,"GDB" Subject: Re: [PATCH] x86-64: fix ZMM register state tracking References: <5B8FD8B302000078001E5940@prv1-mh.provo.novell.com> <369f9b84-77e3-3fa4-f363-a89ee503cff4@ericsson.com> <5B960E3D020000780013C85E@prv1-mh.provo.novell.com> <5BA0FFB102000078001E97B0@prv1-mh.provo.novell.com> <0e0d9f23-2cbf-eb5a-64fa-6cda3392053a@ericsson.com> In-Reply-To: <0e0d9f23-2cbf-eb5a-64fa-6cda3392053a@ericsson.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-SW-Source: 2018-09/txt/msg00831.txt.bz2 >>> On 25.09.18 at 05:28, wrote: > On 2018-09-18 09:37 AM, Jan Beulich wrote: > Thanks for the instructions. There is already a test covering AVX512 > instructions, so I figured I would add it there. However, I don't > have a processor that supports AVX512, so I'm unable to run the test. >=20 > Here's a patch, can you try to confirm that the test fails without the > fix and passes with the fix? I probably screwed up somewhere, but it > should be pretty close. There are two issues here: First of all, unrelated to this patch, the construct around line 95 in i386-avx512.exp should look like if [is_amd64_regs_target] { set nr_regs 32 } else { set nr_regs 8 } Of course this also affects other tests in here, but without this correction the loop you add does nothing at all. And then that very loop and the i386-avx512.c addition are not in sync, and I'm not sure which way you meant it to be: Either in the C file all 16 upper ZMM registers need to be set identically (not just ZMM16), or there should be no loop. Furthermore I think the C code addition and hence the test will need to be x86-64-specific, as registers ZMM8 and higher are inaccessible in 32-bit mode. So what I can confirm at this point is that with the fix in place there's one less new failure from the test than with the fix no in place. Jan