From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24834 invoked by alias); 7 Mar 2010 16:31:43 -0000 Received: (qmail 24826 invoked by uid 22791); 7 Mar 2010 16:31:42 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,SARE_MSGID_LONG40 X-Spam-Check-By: sourceware.org Received: from mail-wy0-f169.google.com (HELO mail-wy0-f169.google.com) (74.125.82.169) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sun, 07 Mar 2010 16:31:38 +0000 Received: by wyb29 with SMTP id 29so2738895wyb.0 for ; Sun, 07 Mar 2010 08:31:36 -0800 (PST) MIME-Version: 1.0 Received: by 10.216.165.67 with SMTP id d45mr1889451wel.28.1267979495847; Sun, 07 Mar 2010 08:31:35 -0800 (PST) In-Reply-To: <6dc9ffc81003070637q3e554ba4n2ee6053c2fd24511@mail.gmail.com> References: <20100304180219.GA10826@intel.com> <20100306221634.GA21133@intel.com> <201003071416.o27EGPfu007140@glazunov.sibelius.xs4all.nl> <6dc9ffc81003070637q3e554ba4n2ee6053c2fd24511@mail.gmail.com> Date: Sun, 07 Mar 2010 16:31:00 -0000 Message-ID: <6dc9ffc81003070831yf923b9bj83da56cb9c83a751@mail.gmail.com> Subject: Re: PATCH: 0/6 [2nd try]: Add AVX support From: "H.J. Lu" To: Mark Kettenis Cc: gdb-patches@sourceware.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2010-03/txt/msg00274.txt.bz2 On Sun, Mar 7, 2010 at 6:37 AM, H.J. Lu wrote: > On Sun, Mar 7, 2010 at 6:16 AM, Mark Kettenis w= rote: >>> Date: Sat, 6 Mar 2010 14:16:34 -0800 >>> From: "H.J. Lu" >>> >>> AVX registers are saved and restored via the XSAVE extended state. The >>> extended control register 0 (the XFEATURE_ENABLED_MASK register), XCR0, >>> is used to determine which states, x87, SSE, AVX, ... are supported >>> in the XSAVE extended state. =A0XCR0 can be read with the new "xgetbv" >>> instruction. =A0The xstate_bv field at byte offset 512 in the XSAVE >>> extended state indicates what states the current process is in. If >>> the feature bit is cleared, the corresponding registers should be read = as >>> 0. If we update a register, we should set the corresponding feature >>> bit in the xstate_bv field. >>> >>> We added PTRACE_GETREGSET and PTRACE_SETREGSET to Linux kernel to >>> fetch and store AVX registers with ptrace. Linux kernel also stores >>> XCR0 at the first 8 bytes of the software usable bytes, starting at >>> byte offset 464. >>> >>> There are total 6 patches to add AVX support for Linux. =A0They support: >>> >>> 1. The upper 128bit YMM registers are added for AVX support. The upper >>> 128bit YMM registers are hidden from users. Gdb combines XMM register, >>> %xmmX, with 128bit YMM register, %ymmXh, and present the whole 256bit >>> YMM register, %ymmX, as pseudo register to users. >>> 2. Backward compatible. If AVX isn't supported, SSE will be used. >>> 3. Forward compatible. If new state beyond AVX is supported in >>> the XSAVE extended state, only AVX state will be used. >>> 4. Remote gdb protocol extension. GDB will send "x86=3Dxml" in qSupport= ed >>> request packet to indicate that GDB supports x86 XML target desciption. >>> The gdb stub will send x86 XML target desciption if it sees "x86=3Dxml" >>> in qSupported request packet. >>> >>> One advantage of this approach is YMM registers are actually stored as >>> XMM registers and upper YMM registers in the XSAVE extended state. =A0It >>> is easy and natural to access them as %xmmX and %ymmXh internally. =A0We >>> just need to hide %ymmXh from users. >>> >>> To support AVX on other OSes, the following changes are needed: >>> >>> 1. Kernel support to get/set the XSAVE extended state. >>> 2. Handle 8/16 upper YMM registers. >>> 3. Provide target to_read_description to return SSE or AVX target >>> description. >>> 4. Update gdbarch_core_read_description to return SSE or AVX target >>> description based on contents of core dump. >> >> Wait; there is something important missing here. =A0How are the new %ymm >> registers referred to in debug info? =A0The AMD64 SysV psABI defines the >> DWARF register Number Mapping, but the 0.99.4 draft copy I have >> doesn't define any mappings for the %ymm registers. =A0What mapping does >> GCC use? >> > > In gcc, XMM and YMM registers have the same register number. They map > to be the same DWARF register with different sizes. =A0Since XMM and YMM > registers are caller-saved, they don't appear in unwind info. So, the same > DWARF register with different sizes for XMM/YMM registers isn't a problem. > > Yes, there is a problem. amd64_dwarf_reg_to_regnum needs to map 256bit register to YMM. How do other arches solve this? --=20 H.J.