From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Nelson Chu <nelson@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: binutils@sourceware.org, gdb-patches@sourceware.org
Subject: [PATCH v3 3/3] gdb/testsuite: RISC-V disassembler option tests
Date: Sun, 20 Nov 2022 02:23:29 +0000 [thread overview]
Message-ID: <70a4ac1ba8c12101de56c24d3a47939a2f5ee542.1668910970.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1668910970.git.research_trasio@irq.a4lg.com>
From: Tsukasa OI <research_trasio@irq.a4lg.com>
This commit adds RISC-V disassembler option tests for:
- "no-aliases" and "numeric" options
- overridable "priv-spec" option
- new "arch" option
and makes sure that option override correctly works and they can be unset
thereafter (with "set disassembler-options" with no options).
---
.../gdb.arch/riscv-disassembler-options.exp | 129 ++++++++++++++++++
.../gdb.arch/riscv-disassembler-options.s | 29 ++++
2 files changed, 158 insertions(+)
create mode 100644 gdb/testsuite/gdb.arch/riscv-disassembler-options.exp
create mode 100644 gdb/testsuite/gdb.arch/riscv-disassembler-options.s
diff --git a/gdb/testsuite/gdb.arch/riscv-disassembler-options.exp b/gdb/testsuite/gdb.arch/riscv-disassembler-options.exp
new file mode 100644
index 000000000000..e5548eb426d3
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disassembler-options.exp
@@ -0,0 +1,129 @@
+# Copyright 2022 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Test RISC-V disassembler options.
+
+if {![istarget "riscv*-*-*"]} {
+ verbose "Skipping ${gdb_test_file_name}."
+ return
+}
+
+standard_testfile .s
+set objfile [standard_output_file ${testfile}.o]
+
+set compile_flags { \
+ "additional_flags=-march=rv64i_zicsr -mabi=lp64" \
+ "additional_flags=-Xassembler -mpriv-spec=1.11" \
+ }
+
+if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${objfile}" object \
+ ${compile_flags}] != "" } {
+ untested "could not compile test program"
+ return
+}
+
+clean_restart ${objfile}
+
+proc riscv_set_disassembler_options { opts } {
+ gdb_test_no_output "set disassembler-options $opts"
+ gdb_test "show disassembler-options" \
+ "The current disassembler options are '$opts'\r\n.*" \
+ "show disassembler-options: $opts"
+}
+
+# We can disable disassembly using alias instructions.
+riscv_set_disassembler_options "no-aliases"
+gdb_test_sequence "disassemble test_func" "option: no-aliases" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\taddi\ta0,zero,1\r\n"
+ "\[^:\]+:\tcsrrs\ta0,0x3d0,zero\r\n"
+ "\[^:\]+:\t\\.4byte\t0x62000073\r\n"
+ "\[^:\]+:\tjalr\tzero,0\\(ra\\)\r\n"
+ "End of assembler dump\."
+}
+
+# We can disassemble using numeric register names.
+riscv_set_disassembler_options "numeric"
+gdb_test_sequence "disassemble test_func" "option: numeric" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\tli\tx10,1\r\n"
+ "\[^:\]+:\tcsrr\tx10,0x3d0\r\n"
+ "\[^:\]+:\t\\.4byte\t0x62000073\r\n"
+ "\[^:\]+:\tret\r\n"
+ "End of assembler dump\."
+}
+
+# We can switch to the privileged specification 1.11.
+riscv_set_disassembler_options "priv-spec=1.11"
+gdb_test_sequence "disassemble test_func" "privileged specification 1.11 CSRs" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\tli\ta0,1\r\n"
+ "\[^:\]+:\tcsrr\ta0,0x3d0\r\n"
+ "\[^:\]+:\t\\.4byte\t0x62000073\r\n"
+ "\[^:\]+:\tret\r\n"
+ "End of assembler dump\."
+}
+
+# We can switch to the privileged specification 1.12.
+riscv_set_disassembler_options "priv-spec=1.12"
+gdb_test_sequence "disassemble test_func" "privileged specification 1.12 CSRs" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\tli\ta0,1\r\n"
+ "\[^:\]+:\tcsrr\ta0,pmpaddr32\r\n"
+ "\[^:\]+:\t\\.4byte\t0x62000073\r\n"
+ "\[^:\]+:\tret\r\n"
+ "End of assembler dump\."
+}
+
+# We can enable the 'H'-extension support.
+riscv_set_disassembler_options "arch=rv64gch"
+gdb_test_sequence "disassemble test_func" "'H'-extension" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\tli\ta0,1\r\n"
+ "\[^:\]+:\tcsrr\ta0,0x3d0\r\n"
+ "\[^:\]+:\thfence\\.gvma\r\n"
+ "\[^:\]+:\tret\r\n"
+ "End of assembler dump\."
+}
+
+# We can set multiple comma-separated options
+riscv_set_disassembler_options "arch=rv64gch,priv-spec=1.12,no-aliases,numeric"
+gdb_test_sequence "disassemble test_func" "multiple options" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\taddi\tx10,x0,1\r\n"
+ "\[^:\]+:\tcsrrs\tx10,pmpaddr32,x0\r\n"
+ "\[^:\]+:\thfence\\.gvma\tx0,x0\r\n"
+ "\[^:\]+:\tjalr\tx0,0\\(x1\\)\r\n"
+ "End of assembler dump\."
+}
+
+# Once we set empty disassembler option, we can restore the default one.
+# Defaults:
+# - enable aliases
+# - ABI register names
+# - priv-spec=1.11
+# - arch=rv64i_zicsr
+gdb_test_no_output "set disassembler-options" "set NULL disassembler-options"
+gdb_test "show disassembler-options" \
+ "The current disassembler options are ''\r\n.*" \
+ "show NULL disassembler-options"
+gdb_test_sequence "disassemble test_func" "restore to default" {
+ "Dump of assembler code for function test_func:\r\n"
+ "\[^:\]+:\tli\ta0,1\r\n"
+ "\[^:\]+:\tcsrr\ta0,0x3d0\r\n"
+ "\[^:\]+:\t\\.4byte\t0x62000073\r\n"
+ "\[^:\]+:\tret\r\n"
+ "End of assembler dump\."
+}
diff --git a/gdb/testsuite/gdb.arch/riscv-disassembler-options.s b/gdb/testsuite/gdb.arch/riscv-disassembler-options.s
new file mode 100644
index 000000000000..fc33b03b0c00
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disassembler-options.s
@@ -0,0 +1,29 @@
+/* Copyright 2022 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+ .attribute arch, "rv64i_zicsr"
+ .option nopic
+ .text
+
+ .align 1
+ .globl test_func
+ .type test_func, @function
+test_func:
+ li a0, 1
+ csrr a0, 0x3d0
+ # hfence.gvma (an alias of hfence.gvma zero,zero)
+ .insn 0x62000073
+ ret
+ .size test_func, .-test_func
--
2.38.1
prev parent reply other threads:[~2022-11-20 2:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-20 2:23 [PATCH v3 0/3] RISC-V: Add overridable "priv-spec" and "arch" disassembler options Tsukasa OI
2022-11-20 2:23 ` [PATCH v3 1/3] RISC-V: Make "priv-spec" overridable Tsukasa OI
2022-11-20 2:23 ` [PATCH v3 2/3] RISC-V: Add "arch" disassembler option Tsukasa OI
2022-11-20 2:23 ` Tsukasa OI [this message]
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