From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 0D78D3858C83 for ; Fri, 22 Apr 2022 19:47:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0D78D3858C83 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 23MI5qj4025773; Fri, 22 Apr 2022 19:47:21 GMT Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0a-001b2d01.pphosted.com with ESMTP id 3fkm5q9r5y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Apr 2022 19:47:21 +0000 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 23MJh2f2004745; Fri, 22 Apr 2022 19:47:20 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma01dal.us.ibm.com with ESMTP id 3ffnebg82k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Apr 2022 19:47:19 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 23MJlIqC10682692 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 22 Apr 2022 19:47:18 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 23E06124064; Fri, 22 Apr 2022 19:47:18 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2C8B5124055; Fri, 22 Apr 2022 19:47:17 +0000 (GMT) Received: from li-e362e14c-2378-11b2-a85c-87d605f3c641.ibm.com (unknown [9.163.11.46]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP; Fri, 22 Apr 2022 19:47:17 +0000 (GMT) Message-ID: <7a58364bfd2bf433ac7fe6603a73ad179bfea99b.camel@us.ibm.com> Subject: Re: [PATCH 2/2 Version 5 PING] Add recording support for the ISA 3.1 Powerpc instructions From: Carl Love To: Joel Brobecker , cel@us.ibm.com Cc: Pedro Alves , will schmidt , gdb-patches@sourceware.org, Ulrich Weigand , Tulio Magno , Rogerio Alves Date: Fri, 22 Apr 2022 12:47:16 -0700 In-Reply-To: <9c137bdf94b78fa5fb3f43c6b63df29a5f91751f.camel@us.ibm.com> References: <7ff0655bead2a8245018fbf9624f207cd38a5b7f.camel@us.ibm.com> <18e61a00641bcaeab322db4d416c03ddc30c8950.camel@us.ibm.com> <09bc969fde2b89abbcc6060e9adc0df3c583fd4c.camel@us.ibm.com> <2cde8652-c16a-bfa8-5f28-2339f70bf58f@palves.net> <1147f8bac229d0e70fedbfe50867e95ea6eca317.camel@us.ibm.com> <1c91727ea1aeb0ba2afb7fcce262a9b5907d61cc.camel@us.ibm.com> <9c137bdf94b78fa5fb3f43c6b63df29a5f91751f.camel@us.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Z6fg99Fx8FDcTsbu6X2SCIEr_jfLaifF X-Proofpoint-GUID: Z6fg99Fx8FDcTsbu6X2SCIEr_jfLaifF Content-Transfer-Encoding: 7bit X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_06,2022-04-22_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2204220083 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Apr 2022 19:47:27 -0000 Joel, Pedro, Will, GDB maintainers: Just wanted to check if there is any additional feedback on the patch or is it ready to commit? Thanks. Carl Love On Mon, 2022-04-18 at 12:21 -0700, Carl Love wrote: > Joel, Pedro, Will, GDB maintainers: > > On Sun, 2022-04-17 at 09:48 -0700, Joel Brobecker wrote: > > As mentioned by Pedro: PowerPC > > > > > > This patch adds Powerpc specific tests to verify recording of > > > various > > > > And here also. > > Yup, missed them. I went thru these patches and the rest of the > patches I am working on to fix in in all of them. Have some > additional > posted patches that need to have this fixed as well. > > > Fixed the additional space issues you mentioned. > > > > > +# Check initial and new of vs0 are different. > > > +set test_vs0_init_new "check vs0 initial versus vs0 new" > > > +if {[string compare $vs0_initial $vs0_new] == 0} { > > > + fail $test_vs0_init_new > > > +} else { > > > + pass $test_vs0_init_new > > > +} > > > > I looked at gdb_assert following Pedro's suggestion, and I agree > > it would really simplify your testcase. Any reason why you didn't > > follow his advice? > > I looked at his suggestion, but it didn't seem to me to make much > difference as you would still need the if statement. I looked at it > again and realized that it really does make is a lot simpler then I > initially thought since you don't need the if statement. The > gdb_assert takes care of doing the test pass/fail. So, yea it is a > good change. I changed the string compares in both the ISA 2.07 and > ISA 3.1 test cases. > > > > > > +# Execute in reverse to before test 1 > > > +gdb_test "set exec-direction reverse" "" "reverse to start of > > > test > > > 1" > > > +#gdb_test_no_output "set exec-direction reverse" > > > > I just noticied this, because we normally avoid commented-out code > > without a good reason behind it (which we also would typically > > provide as a comment next to the code). > > > > But looking at it more closely, I think the commented-out > > version seems to be the correct one, not the one you are using. > > In particular, there is an implicit ".*" at the start of the > > expected output's matching in gdb_test, which means using "" > > as the expected output is the same as matching anything. > > Don't remember if I was playing around with using the > gdb_test_no_output or not. I can't remember now. I may have been > and > got distracted and never got back to it???? Yea, the > gdb_test_no_output works just as well as the gdb_test. Changed to > following tests as well. Note, looks like I did use the > gdb_test_no_output in the ISA 2.07 test. > > Again, retested this patch to make sure I didn't break anything. > > Thanks for the detailed review. > > Carl > ----------------------------------------------------------- > GDB PowerPC record test cases for ISA 2.06 and ISA 3.1 > > This patch adds PowerPC specific tests to verify recording of various > instructions. The first test case checks the ISA 2.06 lxvd2x > instruction. > The second test case tests several of the ISA 3.01 > instructions. Specifically, > it checks the word and prefixed instructions and some of the Matrix > Multiply Assist (MMA) instructions. > > The patch has been run on both Power 10 and Power 9 to verify the ISA > 2.06 test case runs on both platforms without errors. The ISA 3.1 > test > runs without errors on Power 10 and is skipped as expected on Power > 9. > --- > .../gdb.reverse/ppc_record_test_isa_2_06.c | 39 ++ > .../gdb.reverse/ppc_record_test_isa_2_06.exp | 105 ++++++ > .../gdb.reverse/ppc_record_test_isa_3_1.c | 95 +++++ > .../gdb.reverse/ppc_record_test_isa_3_1.exp | 341 > ++++++++++++++++++ > 4 files changed, 580 insertions(+) > create mode 100644 > gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.c > create mode 100644 > gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.exp > create mode 100644 > gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.c > create mode 100644 > gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.exp > > diff --git a/gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.c > b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.c > new file mode 100644 > index 00000000000..45e58413da2 > --- /dev/null > +++ b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.c > @@ -0,0 +1,39 @@ > +/* This testcase is part of GDB, the GNU debugger. > + > + Copyright 2012-2022 Free Software Foundation, Inc. > + > + This program is free software; you can redistribute it and/or > modify > + it under the terms of the GNU General Public License as published > by > + the Free Software Foundation; either version 3 of the License, or > + (at your option) any later version. > + > + This program is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + GNU General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with this program. If not, see < > http://www.gnu.org/licenses/>. */ > + > +/* globals used for vector tests */ > +static vector unsigned long vec_xb; > +static unsigned long ra, rb, rs; > + > +int > +main () > +{ > + ra = 0xABCDEF012; > + rb = 0; > + rs = 0x012345678; > + > + /* 9.0, 16.0, 25.0, 36.0 */ > + vec_xb = (vector unsigned long){0x4110000041800000, > 0x41c8000042100000}; > + > + /* Test ISA 2.06 instructions. Load source into vs1, result of > sqrt > + put into vs0. */ > + ra = (unsigned long) & vec_xb; /* stop 1 */ > + __asm__ __volatile__ ("lxvd2x 1, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("xvsqrtsp 0, 1"); > + ra = 0; /* stop 2 */ > +} > + > diff --git a/gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.exp > b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.exp > new file mode 100644 > index 00000000000..d68dd7b9049 > --- /dev/null > +++ b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_2_06.exp > @@ -0,0 +1,105 @@ > +# Copyright 2008-2022 Free Software Foundation, Inc. > + > +# This program is free software; you can redistribute it and/or > modify > +# it under the terms of the GNU General Public License as published > by > +# the Free Software Foundation; either version 3 of the License, or > +# (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program. If not, see < > http://www.gnu.org/licenses/>. > +# > +# Test instruction record for PowerPC, ISA 2.06. > +# > + > +# The basic flow of the record tests are: > +# 1) Stop before executing the instructions of interest. Record > +# the initial value of the registers that the instruction will > +# change, i.e. the destination register. > +# 2) Execute the instructions. Record the new value of the > +# registers that changed. > +# 3) Reverse the direction of the execution and execute back to > +# just before the instructions of interest. Record the final > +# value of the registers of interest. > +# 4) Check that the initial and new values of the registers are > +# different, i.e. the instruction changed the registers as > expected. > +# 5) Check that the initial and final values of the registers are > +# the same, i.e. gdb record restored the registers to their > +# original values. > + > +standard_testfile > + > +set gen_src record_test_isa_2_06.c > +set executable record_test_isa_2_06 > +set options [list debug] > + > +if {![istarget "powerpc*"]} then { > + verbose "Skipping PowerPC ISA 2.06 instruction > record_test_2_06." > + return > +} > + > +if {[build_executable "failed to prepare" $executable $srcfile > $options] == -1} then { > + return -1 > +} > + > +clean_restart $executable > + > +if ![runto_main] then { > + untested "could not run to main" > + continue > +} > + > +gdb_test_no_output "record" > + > +###### Test: Test an ISA 2.06 load (lxvd2x) and square root > instruction > +###### (xvsqrtsp). The load instruction will load vs1. The sqrt > instruction > +###### will put its result into vs0. > + > +set stop1 [gdb_get_line_number "stop 1"] > +set stop2 [gdb_get_line_number "stop 2"] > + > +gdb_test "break $stop1" ".*Breakpoint .*" "about to execute test" > +gdb_test "continue" ".*Breakpoint .*" "at stop 1" > + > +# Record the initial values in vs0, vs1. > +set vs0_initial [capture_command_output "info register vs0" ""] > +set vs1_initial [capture_command_output "info register vs1" ""] > + > +gdb_test "break $stop2" ".*Breakpoint .*" "executed lxvd2x, > xvsqrtsp" > +gdb_test "continue" ".*Breakpoint .*" "at stop 2" > + > +# Record the new values of vs0 and vs1. > +set vs0_new [capture_command_output "info register vs0" ""] > +set vs1_new [capture_command_output "info register vs1" ""] > + > +# Reverse the execution direction. > +gdb_test_no_output "set exec-direction reverse" > +gdb_test "break $stop1" ".*Breakpoint .*" "un executed lxvd2x, > xvsqrtsp" > + > +# Execute in reverse to before the lxvd2x instruction. > +gdb_test "continue" ".*Breakpoint.*" "at stop 1 in reverse" > + > +# Record the final values of vs0, vs1. > +set vs0_final [capture_command_output "info register vs0" ""] > +set vs1_final [capture_command_output "info register vs1" ""] > + > +# Check initial and new of vs0 are different. > +gdb_assert [string compare $vs0_initial $vs1_new] \ > + "check vs0 initial versus vs0 new" > + > +# Check initial and new of vs1 are different. > +gdb_assert [string compare $vs1_initial $vs1_new] \ > + "check vs0 initial versus vs1 new" > + > +# Check initial and final are the same. > +gdb_assert ![string compare $vs0_initial $vs0_final] \ > + "check vs0 initial versus vs0 final" > + > +# Check initial and final are the same. > +gdb_assert ![string compare $vs1_initial $vs1_final] \ > + "check vs1 initial versus vs1 final" > + > diff --git a/gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.c > b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.c > new file mode 100644 > index 00000000000..c0d65d944af > --- /dev/null > +++ b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.c > @@ -0,0 +1,95 @@ > +/* This testcase is part of GDB, the GNU debugger. > + > + Copyright 2012-2022 Free Software Foundation, Inc. > + > + This program is free software; you can redistribute it and/or > modify > + it under the terms of the GNU General Public License as published > by > + the Free Software Foundation; either version 3 of the License, or > + (at your option) any later version. > + > + This program is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + GNU General Public License for more details. > + > + You should have received a copy of the GNU General Public License > + along with this program. If not, see < > http://www.gnu.org/licenses/>. */ > + > +/* Globals used for vector tests. */ > +static vector unsigned long vec_xa, vec_xb, vec_xt; > +static unsigned long ra, rb, rs; > + > +int > +main () > +{ > + ra = 0xABCDEF012; > + rb = 0; > + rs = 0x012345678; > + > + /* 9.0, 16.0, 25.0, 36.0 */ > + vec_xb = (vector unsigned long){0x4110000041800000, > 0x41c8000042100000}; > + > + vec_xt = (vector unsigned long){0xFF00FF00FF00FF00, > 0xAA00AA00AA00AA00}; > + > + /* Test 1, ISA 3.1 word instructions. Load source into r1, result > of brh > + put in r0. */ > + ra = 0xABCDEF012; /* stop 1 */ > + __asm__ __volatile__ ("pld 1, %0" :: "r" (ra )); > + __asm__ __volatile__ ("brh 0, 1" ); > + ra = 0; /* stop 2 */ > + > + /* Test 2, ISA 3.1 MMA instructions with results in various ACC > entries > + xxsetaccz - ACC[3] > + xvi4ger8 - ACC[4] > + xvf16ger2pn - ACC[5] > + pmxvi8ger4 - ACC[6] > + pmxvf32gerpp - ACC[7] and fpscr */ > + /* Need to initialize the vs registers to a non zero value. */ > + ra = (unsigned long) & vec_xb; > + __asm__ __volatile__ ("lxvd2x 12, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 13, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 14, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 15, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xa = (vector unsigned long){0x333134343987601, > 0x9994bbbc9983307}; > + vec_xb = (vector unsigned long){0x411234041898760, > 0x41c833042103400}; > + __asm__ __volatile__ ("lxvd2x 16, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xb = (vector unsigned long){0x123456789987650, > 0x235676546989807}; > + __asm__ __volatile__ ("lxvd2x 17, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xb = (vector unsigned long){0x878363439823470, > 0x413434c99839870}; > + __asm__ __volatile__ ("lxvd2x 18, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xb = (vector unsigned long){0x043765434398760, > 0x419876555558850}; > + __asm__ __volatile__ ("lxvd2x 19, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xb = (vector unsigned long){0x33313434398760, > 0x9994bbbc99899330}; > + __asm__ __volatile__ ("lxvd2x 20, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 21, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 22, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 23, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 24, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 25, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 26, %0, %1" :: "r" (ra ), "r" (rb)); > + __asm__ __volatile__ ("lxvd2x 27, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xa = (vector unsigned long){0x33313434398760, > 0x9994bbbc998330}; > + vec_xb = (vector unsigned long){0x4110000041800000, > 0x41c8000042100000}; > + __asm__ __volatile__ ("lxvd2x 28, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xb = (vector unsigned long){0x4567000046800000, > 0x4458000048700000}; > + __asm__ __volatile__ ("lxvd2x 29, %0, %1" :: "r" (ra ), "r" (rb)); > + vec_xb = (vector unsigned long){0x41dd000041e00000, > 0x41c8000046544400}; > + __asm__ __volatile__ ("lxvd2x 30, %0, %1" :: "r" (ra ), "r" (rb)); > + > + /* SNAN */ > + vec_xb = (vector unsigned long){0x7F8F00007F8F0000, > 0x7F8F00007F8F0000}; > + > + __asm__ __volatile__ ("lxvd2x 31, %0, %1" :: "r" (ra ), "r" (rb)); > + > + ra = 0xAB; /* stop 3 */ > + __asm__ __volatile__ ("xxsetaccz 3"); > + __asm__ __volatile__ ("xvi4ger8 4, %x0, %x1" :: "wa" (vec_xa), \ > + "wa" (vec_xb) ); > + __asm__ __volatile__ ("xvf16ger2pn 5, %x0, %x1" :: "wa" (vec_xa),\ > + "wa" (vec_xb) ); > + __asm__ __volatile__ ("pmxvi8ger4spp 6, %x0, %x1, 11, 13, 5" > + :: "wa" (vec_xa), "wa" (vec_xb) ); > + __asm__ __volatile__ ("pmxvf32gerpp 7, %x0, %x1, 11, 13" > + :: "wa" (vec_xa), "wa" (vec_xb) ); > + ra = 0; /* stop 4 */ > +} > diff --git a/gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.exp > b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.exp > new file mode 100644 > index 00000000000..9ea8931e9cf > --- /dev/null > +++ b/gdb/testsuite/gdb.reverse/ppc_record_test_isa_3_1.exp > @@ -0,0 +1,341 @@ > +# Copyright 2008-2022 Free Software Foundation, Inc. > + > +# This program is free software; you can redistribute it and/or > modify > +# it under the terms of the GNU General Public License as published > by > +# the Free Software Foundation; either version 3 of the License, or > +# (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program. If not, see < > http://www.gnu.org/licenses/>. > +# > +# Test instruction record for PowerPC, ISA 3.1. > +# > + > +# The basic flow of the record tests are: > +# 1) Stop before executing the instructions of interest. Record > +# the initial value of the registers that the instruction will > +# change, i.e. the destination register. > +# 2) Execute the instructions. Record the new value of the > +# registers that changed. > +# 3) Reverse the direction of the execution and execute back to > +# just before the instructions of interest. Record the final > +# value of the registers of interest. > +# 4) Check that the initial and new values of the registers are > +# different, i.e. the instruction changed the registers as > expected. > +# 5) Check that the initial and final values of the registers are > +# the same, i.e. gdb record restored the registers to their > +# original values. > + > + > +standard_testfile > + > +set gen_src record_test_isa_3_1.c > +set executable record_test_isa_3_1 > + > +if {![istarget "powerpc*"] || [skip_power_isa_3_1_tests] } then { > + verbose "Skipping PowerPC ISA 3.1 instruction record_test." > + return > +} > + > +set options [list additional_flags=-mcpu=power10 debug] > +if {[build_executable "failed to prepare" $executable $srcfile > $options] == -1} then { > + return -1 > +} > + > +clean_restart $executable > + > +if ![runto_main] then { > + untested "could not run to main" > + continue > +} > + > +gdb_test_no_output "record" > + > +###### Test 1: Test an ISA 3.1 byte reverse word instruction (brd) > and a > +###### prefixed load double (pld) instruction. > +set stop1 [gdb_get_line_number "stop 1"] > +set stop2 [gdb_get_line_number "stop 2"] > + > +gdb_test "break $stop1" ".*Breakpoint .*" "about to execute test 1" > +gdb_test "continue" ".*Breakpoint .*" "at stop 1" > + > +# Record the initial values in r0, r1 > +# Load the argument into r1, result of byte reverse is put into r0. > +set r0_initial [capture_command_output "info register r0" ""] > +set r1_initial [capture_command_output "info register r1" ""] > + > +gdb_test "break $stop2" ".*Breakpoint .*" "executed test 1" > +gdb_test "continue" ".*Breakpoint .*" "at stop 2" > + > +# Record the new values of r0 and r1 > +set r0_new [capture_command_output "info register r0" ""] > +set r1_new [capture_command_output "info register r1" ""] > + > +# Execute in reverse to before test 1 > +gdb_test_no_output "set exec-direction reverse" > + > +gdb_test "break $stop1" ".*Breakpoint .*" "reverse stop at test 1 > start" > +gdb_test "continue" ".*Breakpoint.*" "at stop 1 in reverse" > + > +# Record the final values of r0, r1 > +set r0_final [capture_command_output "info register r0" ""] > +set r1_final [capture_command_output "info register r1" ""] > + > +# Check initial and new of r0 are different. > +gdb_assert [string compare $r0_initial $r0_new] \ > + "check r0 initial versus r0 new" > + > +# Check initial and new of r1 are different. > +gdb_assert [string compare $r1_initial $r1_new] \ > + "check r0 initial versus r1 new" > + > +# Check initial and final are the same. > +gdb_assert ![string compare $r0_initial $r0_final] \ > + "check r0 initial versus r0 final" > + > +# Check initial and final are the same. > +gdb_assert ![string compare $r1_initial $r1_final] \ > + "check r1 initial versus r1 final" > + > + > +# Change execution direction to forward for next test. > +gdb_test_no_output "set exec-direction forward" "start forward > test3" > +gdb_test "record stop" ".*Process record is stopped.*" "stopped > recording 2" > +set test_del_bkpts "delete breakpoints, answer prompt 2" > + > +# Delete all breakpoints and catchpoints. > +delete_breakpoints > + > +gdb_test_no_output "record" "start recording test2" > + > + > +###### Test 2: Test the ISA 3.1 MMA instructions xxsetaccz, > xvi4ger8, > +###### xvf16ger2pn, pmxvi8ger4, and pmxvf32gerpp. Goal here is to > hit all > +###### the places where ppc_record_ACC_fpscr() gets called. > +## > +## xxsetaccz - ACC[3], vs[12] to vs[15] > +## xvi4ger8 - ACC[4], vs[16] to vs[19] > +## xvf16ger2pn - ACC[5], vs[20] to vs[23] > +## pmxvi8ger4 - ACC[6], vs[21] to vs[27] > +## pmxvf32gerpp - ACC[7], vs[28] to vs[31] and fpscr > + > +set stop3 [gdb_get_line_number "stop 3"] > +set stop4 [gdb_get_line_number "stop 4"] > + > +gdb_test "break $stop3" ".*Breakpoint .*" "about to execute test 2" > +gdb_test "continue" ".*Breakpoint .*" "at stop 3" > + > +# Record the initial values of vs's that correspond to the ACC > entries, > +# and fpscr. > +set acc_3_0_initial [capture_command_output "info register vs12" ""] > +set acc_3_1_initial [capture_command_output "info register vs13" ""] > +set acc_3_2_initial [capture_command_output "info register vs14" ""] > +set acc_3_3_initial [capture_command_output "info register vs15" ""] > +set acc_4_0_initial [capture_command_output "info register vs16" ""] > +set acc_4_1_initial [capture_command_output "info register vs17" ""] > +set acc_4_2_initial [capture_command_output "info register vs18" ""] > +set acc_4_3_initial [capture_command_output "info register vs19" ""] > +set acc_5_0_initial [capture_command_output "info register vs20" ""] > +set acc_5_1_initial [capture_command_output "info register vs21" ""] > +set acc_5_2_initial [capture_command_output "info register vs22" ""] > +set acc_5_3_initial [capture_command_output "info register vs23" ""] > +set acc_6_0_initial [capture_command_output "info register vs24" ""] > +set acc_6_1_initial [capture_command_output "info register vs25" ""] > +set acc_6_2_initial [capture_command_output "info register vs26" ""] > +set acc_6_3_initial [capture_command_output "info register vs27" ""] > +set acc_7_0_initial [capture_command_output "info register vs28" ""] > +set acc_7_1_initial [capture_command_output "info register vs29" ""] > +set acc_7_2_initial [capture_command_output "info register vs30" ""] > +set acc_7_3_initial [capture_command_output "info register vs31" ""] > +set fpscr_initial [capture_command_output "info register fpscr" ""] > + > +gdb_test "break $stop4" ".*Breakpoint .*" "executed test 2" > +gdb_test "continue" ".*Breakpoint .*" "at stop 4" > + > +# Record the new values of the ACC entries and fpscr. > +set acc_3_0_new [capture_command_output "info register vs12" ""] > +set acc_3_1_new [capture_command_output "info register vs13" ""] > +set acc_3_2_new [capture_command_output "info register vs14" ""] > +set acc_3_3_new [capture_command_output "info register vs15" ""] > +set acc_4_0_new [capture_command_output "info register vs16" ""] > +set acc_4_1_new [capture_command_output "info register vs17" ""] > +set acc_4_2_new [capture_command_output "info register vs18" ""] > +set acc_4_3_new [capture_command_output "info register vs19" ""] > +set acc_5_0_new [capture_command_output "info register vs20" ""] > +set acc_5_1_new [capture_command_output "info register vs21" ""] > +set acc_5_2_new [capture_command_output "info register vs22" ""] > +set acc_5_3_new [capture_command_output "info register vs23" ""] > +set acc_6_0_new [capture_command_output "info register vs24" ""] > +set acc_6_1_new [capture_command_output "info register vs25" ""] > +set acc_6_2_new [capture_command_output "info register vs26" ""] > +set acc_6_3_new [capture_command_output "info register vs27" ""] > +set acc_7_0_new [capture_command_output "info register vs28" ""] > +set acc_7_1_new [capture_command_output "info register vs29" ""] > +set acc_7_2_new [capture_command_output "info register vs30" ""] > +set acc_7_3_new [capture_command_output "info register vs31" ""] > +set fpscr_new [capture_command_output "info register fpscr" ""] > + > +# Execute in reverse to before test 2. > +gdb_test_no_output "set exec-direction reverse" "reverse to start of > test 2" > + > +gdb_test "break $stop3" ".*Breakpoint .*" "reverse stop at test 2 > start" > +gdb_test "continue" ".*Breakpoint.*" "at stop 3 in reverse" > + > +# Record the final values of the ACC entries and fpscr. > +set acc_3_0_final [capture_command_output "info register vs12" ""] > +set acc_3_1_final [capture_command_output "info register vs13" ""] > +set acc_3_2_final [capture_command_output "info register vs14" ""] > +set acc_3_3_final [capture_command_output "info register vs15" ""] > +set acc_4_0_final [capture_command_output "info register vs16" ""] > +set acc_4_1_final [capture_command_output "info register vs17" ""] > +set acc_4_2_final [capture_command_output "info register vs18" ""] > +set acc_4_3_final [capture_command_output "info register vs19" ""] > +set acc_5_0_final [capture_command_output "info register vs20" ""] > +set acc_5_1_final [capture_command_output "info register vs21" ""] > +set acc_5_2_final [capture_command_output "info register vs22" ""] > +set acc_5_3_final [capture_command_output "info register vs23" ""] > +set acc_6_0_final [capture_command_output "info register vs24" ""] > +set acc_6_1_final [capture_command_output "info register vs25" ""] > +set acc_6_2_final [capture_command_output "info register vs26" ""] > +set acc_6_3_final [capture_command_output "info register vs27" ""] > +set acc_7_0_final [capture_command_output "info register vs28" ""] > +set acc_7_1_final [capture_command_output "info register vs29" ""] > +set acc_7_2_final [capture_command_output "info register vs30" ""] > +set acc_7_3_final [capture_command_output "info register vs31" ""] > +set fpscr_final [capture_command_output "info register fpscr" ""] > + > +# check initial and new ACC entries are different. > +gdb_assert [string compare $acc_3_0_initial $acc_3_0_new] \ > + "check vs12 initial versus new" > + > +gdb_assert [string compare $acc_3_1_initial $acc_3_1_new] \ > + "check vs13 initial versus new" > + > +gdb_assert [string compare $acc_3_2_initial $acc_3_2_new] \ > + "check vs14 initial versus new" > + > +gdb_assert [string compare $acc_3_3_initial $acc_3_3_new] \ > + "check vs15 initial versus new" > + > +gdb_assert [string compare $acc_4_0_initial $acc_4_0_new] \ > + "check vs16 initial versus new" > + > +gdb_assert [string compare $acc_4_1_initial $acc_4_1_new] \ > + "check vs17 initial versus new" > + > +gdb_assert [string compare $acc_4_2_initial $acc_4_2_new] \ > + "check vs18 initial versus new" > + > +gdb_assert [string compare $acc_4_3_initial $acc_4_3_new] \ > + "check vs19 initial versus new" > + > +gdb_assert [string compare $acc_5_0_initial $acc_5_0_new] \ > + "check vs20 initial versus new" > + > +gdb_assert [string compare $acc_5_1_initial $acc_5_1_new] \ > + "check vs21 initial versus new" > + > +gdb_assert [string compare $acc_5_2_initial $acc_5_2_new] \ > + "check vs22 initial versus new" > + > +gdb_assert [string compare $acc_5_3_initial $acc_5_3_new] \ > + "check vs23 initial versus new" > + > +gdb_assert [string compare $acc_6_0_initial $acc_6_0_new] \ > + "check vs24 initial versus new" > + > +gdb_assert [string compare $acc_6_1_initial $acc_6_1_new] \ > + "check vs25 initial versus new" > + > +gdb_assert [string compare $acc_6_2_initial $acc_6_2_new] \ > + "check vs26 initial versus new" > + > +gdb_assert [string compare $acc_6_3_initial $acc_6_3_new] \ > + "check vs27 initial versus new" > + > +gdb_assert [string compare $acc_7_0_initial $acc_7_0_new] \ > + "check vs28 initial versus new" > + > +gdb_assert [string compare $acc_7_1_initial $acc_7_1_new] \ > + "check vs29 initial versus new" > + > +gdb_assert [string compare $acc_7_2_initial $acc_7_2_new] \ > + "check vs30 initial versus new" > + > +gdb_assert [string compare $acc_7_3_initial $acc_7_3_new] \ > + "check vs31 initial versus new" > + > +gdb_assert [string compare $fpscr_initial $fpscr_new] \ > + "check fpscr initial versus new" > + > + > +# Check initial and final ACC entries are the same. > +gdb_assert ![string compare $acc_3_0_initial $acc_3_0_final] \ > + "check vs12 initial versus final" > + > +gdb_assert ![string compare $acc_3_1_initial $acc_3_1_final] \ > + "check vs13 initial versus final" > + > +gdb_assert ![string compare $acc_3_2_initial $acc_3_2_final] \ > + "check vs14 initial versus final" > + > +gdb_assert ![string compare $acc_3_3_initial $acc_3_3_final] \ > + "check vs15 initial versus final" > + > +gdb_assert ![string compare $acc_4_0_initial $acc_4_0_final] \ > + "check vs16 initial versus final" > + > +gdb_assert ![string compare $acc_4_1_initial $acc_4_1_final] \ > + "check vs17 initial versus final" > + > +gdb_assert ![string compare $acc_4_2_initial $acc_4_2_final] \ > + "check vs18 initial versus final" > + > +gdb_assert ![string compare $acc_4_3_initial $acc_4_3_final] \ > + "check vs19 initial versus final" > + > +gdb_assert ![string compare $acc_5_0_initial $acc_5_0_final] \ > + "check vs20 initial versus final" > + > +gdb_assert ![string compare $acc_5_1_initial $acc_5_1_final] \ > + "check vs21 initial versus final" > + > +gdb_assert ![string compare $acc_5_2_initial $acc_5_2_final] \ > + "check vs22 initial versus final" > + > +gdb_assert ![string compare $acc_5_3_initial $acc_5_3_final] \ > + "check vs23 initial versus final" > + > +gdb_assert ![string compare $acc_6_0_initial $acc_6_0_final] \ > + "check vs24 initial versus final" > + > +gdb_assert ![string compare $acc_6_1_initial $acc_6_1_final] \ > + "check vs25 initial versus final" > + > +gdb_assert ![string compare $acc_6_2_initial $acc_6_2_final] \ > + "check vs26 initial versus final" > + > +gdb_assert ![string compare $acc_6_3_initial $acc_6_3_final] \ > + "check vs27 initial versus final" > + > +gdb_assert ![string compare $acc_7_0_initial $acc_7_0_final] \ > + "check vs28 initial versus final" > + > +gdb_assert ![string compare $acc_7_1_initial $acc_7_1_final] \ > + "check vs29 initial versus final" > + > +gdb_assert ![string compare $acc_7_2_initial $acc_7_2_final] \ > + "check !vs30 initial versus final" > + > +gdb_assert ![string compare $acc_7_3_initial $acc_7_3_final] \ > + "check !vs31 initial versus final" > + > +gdb_assert ![string compare $fpscr_initial $fpscr_final] \ > + "check fpscr initial versus final" > + > +