From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtp00.avonet.cz (smtp00.avonet.cz [217.112.162.55]) by sourceware.org (Postfix) with ESMTP id EF340385AC32 for ; Tue, 25 Oct 2022 15:35:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EF340385AC32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=fbl.cz Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=fbl.cz Received: from ktus.lan (217-115-245-101.cust.avonet.cz [217.115.245.101]) by smtp00.avonet.cz (Postfix) with ESMTP id 4MxbcS6RgZz1xrm for ; Tue, 25 Oct 2022 17:35:36 +0200 (CEST) Received: by ktus.lan (Postfix, from userid 209) id C8E3130D8C9; Tue, 25 Oct 2022 17:35:36 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00,BODY_8BITS,GIT_PATCH_0,KAM_DMARC_STATUS,NICE_REPLY_A,SPF_FAIL,SPF_HELO_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 Received: from [192.168.33.9] (217-115-245-101.cust.avonet.cz [217.115.245.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vanekt) by ktus.lan (Postfix) with ESMTPSA id ABF4530D8C5; Tue, 25 Oct 2022 17:35:34 +0200 (CEST) Message-ID: <7b3f27c0-418a-46b6-560c-30c80d20beba@fbl.cz> Date: Tue, 25 Oct 2022 17:35:34 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.1 Subject: Re: [PATCH] gdb/arm: fix IPSR field test in arm_m_exception_cache () Content-Language: en-US To: Luis Machado , gdb-patches@sourceware.org References: <1666427154-22766-1-git-send-email-vanekt@fbl.cz> From: Tomas Vanek In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit List-Id: Hi Luis, On 25/10/2022 15:22, Luis Machado wrote: > Hi Tomas, > > On 10/22/22 09:25, Tomas Vanek wrote: >> Arm v8-M Architecture Reference Manual, >> D1.2.141 IPSR, Interrupt Program Status Register reads >> "Exception, bits [8:0]" >> >> 9 bits, not 8! It is uncommon but true! >> >> Signed-off-by: Tomas Vanek >> --- >>   gdb/arm-tdep.c | 2 +- >>   1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >> index b397ca3..923447a 100644 >> --- a/gdb/arm-tdep.c >> +++ b/gdb/arm-tdep.c >> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = { >>       } >>           ULONGEST xpsr = get_frame_register_unsigned (this_frame, >> ARM_PS_REGNUM); >> -      if ((xpsr & 0xff) != 0) >> +      if ((xpsr & 0x1ff) != 0) >>       /* Handler mode: This is the mode that exceptions are handled >> in.  */ >>       arm_cache_switch_prev_sp (cache, tdep, >> tdep->m_profile_msp_s_regnum); >>         else > > Good catch. This LGTM. > > I suppose you need us to push this patch on your behalf? > Yes, please push all my patches as they are ready. Thanks     Tomas