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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Apr 2024 22:12:12.2390 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8985397c-cf2d-4efe-e819-08dc58e21b40 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM1PEPF000252DC.eurprd07.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7628 X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,FORGED_SPF_HELO,KAM_DMARC_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,TXREP,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/9/24 19:16, John Baldwin wrote: > On 4/3/24 11:16 AM, Tom Tromey wrote: >>>>>>> "Tom" == Tom Tromey writes: >> >> Tom> The background DWARF reader turns out to have a few races.  This >> Tom> series fixes one that occurs when the indexer runs at the same time as >> Tom> DWARF relocation. >> >> Tom> Most of the series is just cleanup / preparation. >> >> Tom> The main patch affects MIPS16.  I can't test this -- I tried on a MIPS >> Tom> machine in the GCC compile farm, but unfortunately the relevant >> Tom> gdb.arch test says that the processor doesn't support MIPS16.  It's >> Tom> possible this code is simply dead; I do not know. >> >> Elsewhere I mentioned that I had a different idea for this series. >> >> It seems to me that most (or maybe even all) the calls to >> dwarf2_per_objfile::adjust aren't really needed.  Many of them only >> affect lookup tables, where the adjustment isn't needed.  This includes >> all calls made by the indexer. >> >> Some of the calls (like the one in read_attribute_value) even seem to be >> wrong. >> >> So, I wrote a short series to remove these.  Unfortunately, though, it's >> hard to know for sure if the result is correct, given that I don't know >> how to test MIPS16. >> >> I could probably test some simple things ("break") by debugging gdb >> while examining (but not running) a MIPS16 program.  I'm not sure if >> that's really sufficient though. >> >> I'd appreciate some insight if you have any. > > I haven't seen anyone active with submitting MIPS patches in several years. > I no longer make use of MIPS myself (and we've removed it from FreeBSD > entirely, though I know it's still present in Linux distros).  Even when I > was working with MIPS I never tested microMIPS / MIPS16. > > OTOH, I think MIPS16 is similar to Thumb on ARM, and it might even be > using a similar trick from reading your series (setting the LSB to enter > "compressed decoding mode" vs "regular decoding mode").  I think ARM uses > special mapping symbols to mark Thumb vs non-Thumb code though instead of > depending on the LSB?  That is, I wonder why Thumb doesn't trip over this > issue the way MIPS16 does? > cc-ing Maciej, who might have a better idea on MIPS bits.