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Wed, 29 Jun 2022 10:55:34 +0000 Received: from VI1PR08MB3919.eurprd08.prod.outlook.com ([fe80::1cda:8ca1:6353:572c]) by VI1PR08MB3919.eurprd08.prod.outlook.com ([fe80::1cda:8ca1:6353:572c%4]) with mapi id 15.20.5395.014; Wed, 29 Jun 2022 10:55:34 +0000 Message-ID: <82839961-0a9a-5c8e-0442-f943373b9a81@arm.com> Date: Wed, 29 Jun 2022 11:55:30 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] gdb/arm: Only stack S16..S31 when FPU registers are secure Content-Language: en-US To: Yvan Roux , gdb-patches@sourceware.org Cc: Torbjorn SVENSSON References: <20220614144751.GA12000@gnbcxd0114.gnb.st.com> <20220629095243.GA30810@gnbcxd0114.gnb.st.com> From: Luis Machado In-Reply-To: <20220629095243.GA30810@gnbcxd0114.gnb.st.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: LO2P265CA0344.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:d::20) To VI1PR08MB3919.eurprd08.prod.outlook.com (2603:10a6:803:c4::31) MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: ae5daa9a-8677-47fa-5797-08da59bdea16 X-MS-TrafficTypeDiagnostic: AS4PR08MB8141:EE_|DBAEUR03FT003:EE_|AM6PR08MB3064:EE_ x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT003.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB3064 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 Jun 2022 10:55:51 -0000 On 6/29/22 10:52, Yvan Roux wrote: > On Tue, Jun 21, 2022 at 03:19:52PM +0100, Luis Machado wrote: >> Hi, >> >> Sorry I missed this one. >> >> On 6/14/22 15:47, Yvan Roux wrote: >>> Hi, >>> >>> The FPCCR.TS bit is used to identify if FPU registers are considered >>> non-secure or secure. If they are secure, then callee saved registers >> >> Two spaces after `.`. >> >>> (S16 to S31) are stacked on exception entry or otherwise skipped. >>> >>> Signed-off-by: Torbj�rn SVENSSON >>> Signed-off-by: Yvan Roux >>> --- >>> gdb/arch/arm.h | 6 ++++++ >>> gdb/arm-tdep.c | 9 ++++++++- >>> 2 files changed, 14 insertions(+), 1 deletion(-) >>> >>> diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h >>> index 4ad329f6f1f..de1b472fe71 100644 >>> --- a/gdb/arch/arm.h >>> +++ b/gdb/arch/arm.h >>> @@ -136,6 +136,12 @@ enum arm_m_profile_type { >>> #define XPSR_T 0x01000000 >>> +/* System control registers addresses. */ >>> + >> >> Maybe we should make it a bit more verbose. How about... >> >> /* System control registers accessible through an address. */ >> >>> +/* M-profile Floating-Point Context Control Register address, defined in ARMv7-M >>> + (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference manuals. */ >>> +#define FPCCR 0xE000EF34 >>> + >> >> Since these are effectively addresses, I wonder if we should create an enum category for >> them, with a type that is really the type used to store an address, as opposed to storing a >> register number. >> >> enum class system_register_address: CORE_ADDR >> { >> FPCCR = 0xe000ef34, >> }; >> >> What do you think? > > I agree, but I'd use an unscoped enum to avoid having to use a static_cast when > using it. > >> >>> /* Size of registers. */ >>> #define ARM_INT_REGISTER_SIZE 4 >>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c >>> index 456649afdaa..abc812817aa 100644 >>> --- a/gdb/arm-tdep.c >>> +++ b/gdb/arm-tdep.c >>> @@ -3519,6 +3519,13 @@ arm_m_exception_cache (struct frame_info *this_frame) >>> { >>> int i; >>> int fpu_regs_stack_offset; >>> + ULONGEST fpccr; >>> + bool fpccr_ts; >> >> Define the above during assignment. >> >>> + >>> + /* Read FPCCR register */ >>> + gdb_assert (safe_read_memory_unsigned_integer (FPCCR, 4, byte_order, >>> + &fpccr)); >> >> 4 -> ARM_INT_REGISTER_SIZE? >> >>> + fpccr_ts = fpccr & (1 << 26); >> >> Just a suggestion. How about having a function that extracts the bit, since we're really interested >> if the bit is set or not, and not in the position of the bit. > > There is a macro for that purpose, so let's using it ;) > >> >>> /* This code does not take into account the lazy stacking, see "Lazy >>> context save of FP state", in B1.5.7, also ARM AN298, supported >>> @@ -3538,7 +3545,7 @@ arm_m_exception_cache (struct frame_info *this_frame) >>> cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60); >>> fpu_regs_stack_offset += 4; >>> - if (tdep->have_sec_ext && !default_callee_register_stacking) >>> + if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr_ts) >>> { >>> /* Handle floating-point callee saved registers. */ >>> fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; >> > > Here is the new version of the patch: > > The FPCCR.TS bit is used to identify if FPU registers are considered > non-secure or secure. If they are secure, then callee saved registers > (S16 to S31) are stacked on exception entry or otherwise skipped. > > Signed-off-by: Torbjörn SVENSSON > --- > gdb/arch/arm.h | 9 +++++++++ > gdb/arm-tdep.c | 9 ++++++++- > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h > index 4ad329f6f1f..36757493406 100644 > --- a/gdb/arch/arm.h > +++ b/gdb/arch/arm.h > @@ -109,6 +109,15 @@ enum arm_m_profile_type { > ARM_M_TYPE_INVALID > }; > > +/* System control registers accessible through an addresses. */ > +enum system_register_address : CORE_ADDR > +{ > + /* M-profile Floating-Point Context Control Register address, defined in > + ARMv7-M (Section B3.2.2) and ARMv8-M (Section D1.2.99) reference > + manuals. */ > + FPCCR = 0xe000ef34 > +}; > + > /* Instruction condition field values. */ > #define INST_EQ 0x0 > #define INST_NE 0x1 > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index e36bde9b3da..8330e819ccb 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -3573,6 +3573,13 @@ arm_m_exception_cache (struct frame_info *this_frame) > { > int i; > int fpu_regs_stack_offset; > + ULONGEST fpccr; > + > + /* Read FPCCR register. */ > + gdb_assert (safe_read_memory_unsigned_integer (FPCCR, > + ARM_INT_REGISTER_SIZE, > + byte_order, &fpccr)); > + bool fpccr_ts = bit(fpccr,26); bit( -> bit ( > > /* This code does not take into account the lazy stacking, see "Lazy > context save of FP state", in B1.5.7, also ARM AN298, supported > @@ -3592,7 +3599,7 @@ arm_m_exception_cache (struct frame_info *this_frame) > cache->saved_regs[ARM_FPSCR_REGNUM].set_addr (unwound_sp + sp_r0_offset + 0x60); > fpu_regs_stack_offset += 4; > > - if (tdep->have_sec_ext && !default_callee_register_stacking) > + if (tdep->have_sec_ext && !default_callee_register_stacking && fpccr_ts) > { > /* Handle floating-point callee saved registers. */ > fpu_regs_stack_offset = unwound_sp + sp_r0_offset + 0x68; Otherwise LGTM. Thanks for the patch.