From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 7E3BD385AC2C; Tue, 4 Oct 2022 11:26:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7E3BD385AC2C Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id AACDD300089; Tue, 4 Oct 2022 11:26:21 +0000 (UTC) From: Tsukasa OI To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt , Andrew Burgess , Jan Beulich , Andreas Schwab Cc: binutils@sourceware.org, gdb-patches@sourceware.org Subject: [PATCH v3 2/2] gdb/riscv: Partial support for instructions up to 176-bit Date: Tue, 4 Oct 2022 11:25:57 +0000 Message-Id: <83464b09b8649525259c69c853dfa2c9575a204b.1664882725.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Oct 2022 11:26:25 -0000 Because riscv_insn_length started to support instructions up to 176-bit, we need to increase buf size to 176-bit in size. Also, that would break an assumption in riscv_insn::decode so this commit fixes it, noting that instructions longer than 64-bit are not fully supported yet. --- gdb/riscv-tdep.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 47d8f9e601b..63ebed4ff19 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr, int *len) { enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); - gdb_byte buf[8]; + gdb_byte buf[RISCV_MAX_INSN_LEN]; int instlen, status; /* All insns are at least 16 bits. */ @@ -1933,9 +1933,10 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) } else { - /* This must be a 6 or 8 byte instruction, we don't currently decode - any of these, so just ignore it. */ - gdb_assert (m_length == 6 || m_length == 8); + /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't + have full instruction bits in ival. At least, such long instructions + are not defined yet, so just ignore it. */ + gdb_assert (m_length > 0 && m_length % 2 == 0); m_opcode = OTHER; } } -- 2.34.1