Re: [PATCH 1/1] Documentation for MPX.

Re: [PATCH 1/1] Documentation for MPX.

[Eli Zaretskii]

> From: y@ecsmtp.iul.intel.com
> Cc: gdb-patches@sourceware.org, Walfred Tedeschi <walfred.tedeschi@intel.com>
> Date: Thu, 21 Nov 2013 15:02:57 +0100
> 
> From: Walfred Tedeschi <walfred.tedeschi@intel.com>
> 
> Hello Eli and Pedro,
> 
> This should complement the MPX registers check-in.
> 
> Thanks a lot for your review on the last patch series.
> Here I have tried to incorporate feedback from you both.

Thanks.  I don't know why, but I received this about a dozen times;
this is one of them, and I hope they are all identical.

> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -5558,3 +5558,5 @@ GDB now handles cross debugging.  If you are remotely debugging between
>  two different machines, type ``./configure host -target=targ''.
>  Host is the machine where GDB will run; targ is the machine
>  where the program that you are debugging will run.
> +
> + *  GDB now supports access to Intel(R) MPX registers on GNU/Linux.

OK.

> +@subsubsection Intel(R) Memory Protection Extensions (MPX).
> +
> +@item bnd0raw..bnd3raw and bnd0...bnd3 registers display.

Please use @dots{} instead of 3 literal period characters.

> +Memory Protection Extension (MPX) adds the bound registers @samp{BND0}

"Memory Protection Extension" should be in @dfn -- you are introducing
new terminology.  Also, please put here a @cindex entry for this term.

> +@footnote{Capital letters are used to distinguish between architecture
> +registers and pseudo registers.  A set of pseudo registers for the bound
> +registers is created to simplify the display.}

This footnote confused me.  Please explain what you wanted to say, and
I will suggest a better wording.

> +Architectuere registers @samp{BND0} through @samp{BND3} are
   ^^^^^^^^^^^^^
A typo.

> +@smallexample
> +	bnd0raw = {0x32, 0xffffffff8e}
> +	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64
> +@end smallexample

This will cause makeinfo to barf.  You need to escape each { and }
with a @.

> +This way the architecture value can be accessed via bnd0raw...bnd3raw.  Any change

I wonder if it wouldn't be better to use "raw value" instead of
"architecture value".

> +on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart.
                                         ^^^^^^^^^^
"reflected in".  Also, please use @dots{} here as well.

>                                                         When displaying
> +bnd0..bnd3 register with Python support also the size of the bounds is displayed.

I'd reword

  When the bnd0..bnd3 registers are displayed via Python, the display
  includes the size of the bounds.

Btw, what is "the size of the bounds"?

[PATCH v2 5/7] Adds support for thumb32 instructions recording

[Omair Javaid]

This patch adds support for recording thumb32 arm instructions.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (enum arm_record_result): New enum.
	(arm_record_unsupported_insn): New function.
	(arm_record_coproc_data_proc): Removed.
	(thumb2_record_ld_st_multiple): New function.
	(thumb2_record_ld_st_dual_ex_tbb): New function.
	(thumb2_record_data_proc_sreg_mimm): New function.
	(thumb2_record_ps_dest_generic): New function.
	(thumb2_record_branch_misc_cntrl): New function.
	(thumb2_record_str_single_data): New function.
	(thumb2_record_ld_mem_hints): New function.
	(thumb2_record_ld_word): New function.
	(thumb2_record_lmul_lmla_div): New function.
	(thumb2_record_decode_insn_handler): New function.
	(decode_insn): Add thumb32 instruction handlers.

---
 gdb/arm-tdep.c |  603 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 596 insertions(+), 7 deletions(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 2a61dbd..3747d35 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -10666,6 +10666,11 @@ sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
   return 1;
 }
 
+enum arm_record_result {
+  ARM_RECORD_SUCCESS = 0,
+  ARM_RECORD_FAILURE = 1
+};
+
 typedef enum
 {
   ARM_RECORD_STRH=1,
@@ -11908,7 +11913,7 @@ arm_record_b_bl (insn_decode_record *arm_insn_r)
 /* Handling opcode 110 insns.  */
 
 static int
-arm_record_coproc (insn_decode_record *arm_insn_r)
+arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
 {
   printf_unfiltered (_("Process record does not support instruction "
                     "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
@@ -12401,6 +12406,581 @@ thumb_record_branch (insn_decode_record *thumb_insn_r)
   return 0;     
 }
 
+/* Handler for thumb2 load/store multiple instructions.  */
+
+static int
+thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
+{
+  struct regcache *reg_cache = thumb2_insn_r->regcache;
+
+  uint32_t reg_rn, op;
+  uint32_t register_bits = 0, register_count = 0;
+  uint32_t index = 0, start_address = 0;
+  uint32_t record_buf[24], record_buf_mem[48];
+
+  ULONGEST u_regval = 0;
+
+  reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+  op = bits (thumb2_insn_r->arm_insn, 23, 24);
+
+  if (0 == op || 3 == op)
+    {
+      if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+        {
+          /* Handle RFE instruction.  */
+          record_buf[0] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+      else
+        {
+          /* Handle SRS instruction after reading banked SP.  */
+          return arm_record_unsupported_insn (thumb2_insn_r);
+        }
+    }
+  else if (1 == op || 2 == op)
+    {
+      if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+        {
+          /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions.  */
+          register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
+          while (register_bits)
+            {
+              if (register_bits & 0x00000001)
+                record_buf[index++] = register_count;
+
+              register_count++;
+              register_bits = register_bits >> 1;
+            }
+          record_buf[index++] = reg_rn;
+          record_buf[index++] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = index;
+        }
+      else
+        {
+          /* Handle STM/STMIA/STMEA and STMDB/STMFD.  */
+          register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
+          regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
+          while (register_bits)
+            {
+              if (register_bits & 0x00000001)
+                register_count++;
+
+              register_bits = register_bits >> 1;
+            }
+
+          if (1 == op)
+            {
+              /* Start address calculation for LDMDB/LDMEA.  */
+              start_address = u_regval;
+            }
+          else if (2 == op)
+            {
+              /* Start address calculation for LDMDB/LDMEA.  */
+              start_address = u_regval - register_count * 4;
+            }
+
+          thumb2_insn_r->mem_rec_count = register_count;
+          while (register_count)
+            {
+              record_buf_mem[register_count * 2 - 1] = start_address;
+              record_buf_mem[register_count * 2 - 2] = 4;
+              start_address = start_address + 4;
+              register_count--;
+            }
+          record_buf[0] = reg_rn;
+          record_buf[1] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 2;
+        }
+    }
+
+  MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+            record_buf_mem);
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 load/store (dual/exclusive) and table branch
+   instructions.  */
+
+static int
+thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
+{
+  struct regcache *reg_cache = thumb2_insn_r->regcache;
+
+  uint32_t reg_rd, reg_rn, offset_imm;
+  uint32_t reg_dest1, reg_dest2;
+  uint32_t address, offset_addr;
+  uint32_t record_buf[8], record_buf_mem[8];
+  uint32_t op1, op2, op3;
+  LONGEST s_word;
+
+  ULONGEST u_regval[2];
+
+  op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
+  op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
+  op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
+
+  if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+    {
+      if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
+        {
+          reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
+          record_buf[0] = reg_dest1;
+          record_buf[1] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 2;
+        }
+
+      if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
+        {
+          reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
+          record_buf[2] = reg_dest2;
+          thumb2_insn_r->reg_rec_count = 3;
+        }
+    }
+  else
+    {
+      reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+      regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
+
+      if (0 == op1 && 0 == op2)
+        {
+          /* Handle STREX.  */
+          offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
+          address = u_regval[0] + (offset_imm * 4);
+          record_buf_mem[0] = 4;
+          record_buf_mem[1] = address;
+          thumb2_insn_r->mem_rec_count = 1;
+          reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
+          record_buf[0] = reg_rd;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+      else if (1 == op1 && 0 == op2)
+        {
+          reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
+          record_buf[0] = reg_rd;
+          thumb2_insn_r->reg_rec_count = 1;
+          address = u_regval[0];
+          record_buf_mem[1] = address;
+
+          if (4 == op3)
+            {
+              /* Handle STREXB.  */
+              record_buf_mem[0] = 1;
+              thumb2_insn_r->mem_rec_count = 1;
+            }
+          else if (5 == op3)
+            {
+              /* Handle STREXH.  */
+              record_buf_mem[0] = 2 ;
+              thumb2_insn_r->mem_rec_count = 1;
+            }
+          else if (7 == op3)
+            {
+              /* Handle STREXD.  */
+              address = u_regval[0];
+              record_buf_mem[0] = 4;
+              record_buf_mem[2] = 4;
+              record_buf_mem[3] = address + 4;
+              thumb2_insn_r->mem_rec_count = 2;
+            }
+        }
+      else
+        {
+          offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
+
+          if (bit (thumb2_insn_r->arm_insn, 24))
+            {
+              if (bit (thumb2_insn_r->arm_insn, 23))
+                offset_addr = u_regval[0] + (offset_imm * 4);
+              else
+                offset_addr = u_regval[0] - (offset_imm * 4);
+
+              address = offset_addr;
+            }
+          else
+            address = u_regval[0];
+
+          record_buf_mem[0] = 4;
+          record_buf_mem[1] = address;
+          record_buf_mem[2] = 4;
+          record_buf_mem[3] = address + 4;
+          thumb2_insn_r->mem_rec_count = 2;
+          record_buf[0] = reg_rn;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+    }
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+            record_buf_mem);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 data processing (shift register and modified immediate)
+   instructions.  */
+
+static int
+thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t reg_rd, op;
+  uint32_t record_buf[8];
+
+  op = bits (thumb2_insn_r->arm_insn, 21, 24);
+  reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
+
+  if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
+    {
+      record_buf[0] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 1;
+    }
+  else
+    {
+      record_buf[0] = reg_rd;
+      record_buf[1] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 2;
+    }
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Generic handler for thumb2 instructions which effect destination and PS
+   registers.  */
+
+static int
+thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t reg_rd;
+  uint32_t record_buf[8];
+
+  reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
+
+  record_buf[0] = reg_rd;
+  record_buf[1] = ARM_PS_REGNUM;
+  thumb2_insn_r->reg_rec_count = 2;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 branch and miscellaneous control instructions.  */
+
+static int
+thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t op, op1, op2;
+  uint32_t record_buf[8];
+
+  op = bits (thumb2_insn_r->arm_insn, 20, 26);
+  op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
+  op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
+
+  /* Handle MSR insn.  */
+  if (!(op1 & 0x2) && 0x38 == op)
+    {
+      if (!(op2 & 0x3))
+        {
+          /* CPSR is going to be changed.  */
+          record_buf[0] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+      else
+        {
+          arm_record_unsupported_insn(thumb2_insn_r);
+          return -1;
+        }
+    }
+  else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
+    {
+      /* BLX.  */
+      record_buf[0] = ARM_PS_REGNUM;
+      record_buf[1] = ARM_LR_REGNUM;
+      thumb2_insn_r->reg_rec_count = 2;
+    }
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 store single data item instructions.  */
+
+static int
+thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
+{
+  struct regcache *reg_cache = thumb2_insn_r->regcache;
+
+  uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
+  uint32_t address, offset_addr;
+  uint32_t record_buf[8], record_buf_mem[8];
+  uint32_t op1, op2;
+
+  ULONGEST u_regval[2];
+
+  op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
+  op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
+  reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+  regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
+
+  if (bit (thumb2_insn_r->arm_insn, 23))
+    {
+      /* T2 encoding.  */
+      offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
+      offset_addr = u_regval[0] + offset_imm;
+      address = offset_addr;
+    }
+  else
+    {
+      /* T3 encoding.  */
+      if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
+        {
+          /* Handle STRB (register).  */
+          reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
+          regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
+          shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
+          offset_addr = u_regval[1] << shift_imm;
+          address = u_regval[0] + offset_addr;
+        }
+      else
+        {
+          offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
+          if (bit (thumb2_insn_r->arm_insn, 10))
+            {
+              if (bit (thumb2_insn_r->arm_insn, 9))
+                offset_addr = u_regval[0] + offset_imm;
+              else
+                offset_addr = u_regval[0] - offset_imm;
+
+              address = offset_addr;
+            }
+          else
+            address = u_regval[0];
+        }
+    }
+
+  switch (op1)
+    {
+      /* Store byte instructions.  */
+      case 4:
+      case 0:
+        record_buf_mem[0] = 1;
+      break;
+      /* Store half word instructions.  */
+      case 1:
+      case 5:
+        record_buf_mem[0] = 2;
+      break;
+      /* Store word instructions.  */
+      case 2:
+      case 6:
+        record_buf_mem[0] = 4;
+      break;
+
+      default:
+        gdb_assert_not_reached ("no decoding pattern found");
+      break;
+    }
+
+  record_buf_mem[1] = address;
+  thumb2_insn_r->mem_rec_count = 1;
+  record_buf[0] = reg_rn;
+  thumb2_insn_r->reg_rec_count = 1;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+            record_buf_mem);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 load memory hints instructions.  */
+
+static int
+thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t record_buf[8];
+  uint32_t reg_rt, reg_rn;
+
+  reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
+  reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+
+  if (ARM_PC_REGNUM != reg_rt)
+    {
+      record_buf[0] = reg_rt;
+      record_buf[1] = reg_rn;
+      record_buf[2] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 3;
+
+      REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+                record_buf);
+      return ARM_RECORD_SUCCESS;
+    }
+
+  return ARM_RECORD_FAILURE;
+}
+
+/* Handler for thumb2 load word instructions.  */
+
+static int
+thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t opcode1 = 0, opcode2 = 0;
+  uint32_t record_buf[8];
+
+  record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
+  record_buf[1] = ARM_PS_REGNUM;
+  thumb2_insn_r->reg_rec_count = 2;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 long multiply, long multiply accumulate, and
+   divide instructions.  */
+
+static int
+thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t opcode1 = 0, opcode2 = 0;
+  uint32_t record_buf[8];
+  uint32_t reg_src1 = 0;
+
+  opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
+  opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
+
+  if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
+    {
+      /* Handle SMULL, UMULL, SMULAL.  */
+      /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S).  */
+      record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
+      record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
+      record_buf[2] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 3;
+    }
+  else if (1 == opcode1 || 3 == opcode2)
+    {
+      /* Handle SDIV and UDIV.  */
+      record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
+      record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
+      record_buf[2] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 3;
+    }
+  else
+    return ARM_RECORD_FAILURE;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Decodes thumb2 instruction type and invokes its record handler.  */
+
+static unsigned int
+thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t op, op1, op2;
+
+  op = bit (thumb2_insn_r->arm_insn, 15);
+  op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
+  op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
+
+  if (op1 == 0x01)
+    {
+      if (!(op2 & 0x64 ))
+        {
+          /* Load/store multiple instruction.  */
+          return thumb2_record_ld_st_multiple (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x64) ^ 0x04))
+        {
+          /* Load/store (dual/exclusive) and table branch instruction.  */
+          return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x20) ^ 0x20))
+        {
+          /* Data-processing (shifted register).  */
+          return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
+        }
+      else if (op2 & 0x40)
+        {
+          /* Co-processor instructions.  */
+          arm_record_unsupported_insn (thumb2_insn_r);
+        }
+    }
+  else if (op1 == 0x02)
+    {
+      if (op)
+        {
+          /* Branches and miscellaneous control instructions.  */
+          return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
+        }
+      else if (op2 & 0x20)
+        {
+          /* Data-processing (plain binary immediate) instruction.  */
+          return thumb2_record_ps_dest_generic (thumb2_insn_r);
+        }
+      else
+        {
+          /* Data-processing (modified immediate).  */
+          return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
+        }
+    }
+  else if (op1 == 0x03)
+    {
+      if (!(op2 & 0x71 ))
+        {
+          /* Store single data item.  */
+          return thumb2_record_str_single_data (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x71) ^ 0x10))
+        {
+          /* Advanced SIMD or structure load/store instructions.  */
+          return arm_record_unsupported_insn (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x67) ^ 0x01))
+        {
+          /* Load byte, memory hints instruction.  */
+          return thumb2_record_ld_mem_hints (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x67) ^ 0x03))
+        {
+          /* Load halfword, memory hints instruction.  */
+          return thumb2_record_ld_mem_hints (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x67) ^ 0x05))
+        {
+          /* Load word instruction.  */
+          return thumb2_record_ld_word (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x70) ^ 0x20))
+        {
+          /* Data-processing (register) instruction.  */
+          return thumb2_record_ps_dest_generic (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x78) ^ 0x30))
+        {
+          /* Multiply, multiply accumulate, abs diff instruction.  */
+          return thumb2_record_ps_dest_generic (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x78) ^ 0x38))
+        {
+          /* Long multiply, long multiply accumulate, and divide.  */
+          return thumb2_record_lmul_lmla_div (thumb2_insn_r);
+        }
+      else if (op2 & 0x40)
+        {
+          /* Co-processor instructions.  */
+          return arm_record_unsupported_insn (thumb2_insn_r);
+        }
+   }
+
+  return -1;
+}
 
 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success 
 and positive val on fauilure.  */
@@ -12439,7 +13019,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
     arm_record_ld_st_reg_offset,        /* 011.  */
     arm_record_ld_st_multiple,          /* 100.  */
     arm_record_b_bl,                    /* 101.  */
-    arm_record_coproc,                  /* 110.  */
+    arm_record_unsupported_insn,        /* 110.  */
     arm_record_coproc_data_proc         /* 111.  */
   };
 
@@ -12490,11 +13070,20 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
     }
   else if (THUMB2_RECORD == record_type)
     {
-      printf_unfiltered (_("Process record doesnt support thumb32 instruction "
-                           "0x%0x at address %s.\n"),arm_record->arm_insn,
-                           paddress (arm_record->gdbarch, 
-                           arm_record->this_addr));
-      ret = -1;
+      /* As thumb does not have condition codes, we set negative.  */
+      arm_record->cond = -1;
+
+      /* Swap first half of 32bit thumb instruction with second half.  */
+      arm_record->arm_insn = (arm_record->arm_insn >> 16) |
+                             (arm_record->arm_insn << 16);
+
+      insn_id = thumb2_record_decode_insn_handler (arm_record);
+
+      if (insn_id != ARM_RECORD_SUCCESS)
+        {
+          arm_record_unsupported_insn(arm_record);
+          ret = -1;
+        }
     }
   else
     {
-- 
1.7.9.5

[PATCH v2 0/7] ARM record/replay and reverse debugging improvements

[Omair Javaid]

This patch series improves gdb process record and reverse debugging
capabilities for arm targets. Here is the list of 7 patches in this series 
and their description:

  [PATCH v2 1/7] Fix for memory record corruption due to 64bit addresses
  [PATCH v2 2/7] Fix for bugs in push and ldm instructions decoding
  [PATCH v2 3/7] Fix for bug in pop instruction decoding
  [PATCH v2 4/7] Adds support for recording system call instructions
  [PATCH v2 5/7] Adds support for thumb32 instructions recording
  [PATCH v2 6/7] Updates configure.tgt and enables gdb.reverse testsuite
  [PATCH v2 7/7] Adds a NEWS entry for arm record/replay improvements

 gdb/NEWS                  |    4 +
 gdb/arm-linux-tdep.c      |  248 +++++++++++++++-
 gdb/arm-tdep.c            |  718 ++++++++++++++++++++++++++++++++++++++++-----
 gdb/arm-tdep.h            |    4 +-
 gdb/configure.tgt         |    2 +-
 gdb/testsuite/lib/gdb.exp |    6 +-
 6 files changed, 905 insertions(+), 77 deletions(-)

-- 
1.7.9.5

[PATCH v2 3/7] Fix for bug in pop instruction decoding

[Omair Javaid]

This patch fixes thumb push instruction recording by replacing base register
from pc to sp.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (thumb_record_misc): Update to use sp as base register for
	push instruction recording.

---
 gdb/arm-tdep.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 24bacf8..f7a214f 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -12212,7 +12212,7 @@ thumb_record_misc (insn_decode_record *thumb_insn_r)
     {
       /* PUSH.  */
       register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
-      regcache_raw_read_unsigned (reg_cache, ARM_PC_REGNUM, &u_regval);
+      regcache_raw_read_unsigned (reg_cache, ARM_SP_REGNUM, &u_regval);
       while (register_bits)
         {
           if (register_bits & 0x00000001)
-- 
1.7.9.5

[PATCH v2 4/7] Adds support for recording system call instructions

[Omair Javaid]

This patch adds support for process record/replay system call recording
for arm targets.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* arm-linux-tdep.c: Include "record-full.h" and
	"linux-record.h".
	(struct arm_linux_record_tdep): Declare.
	(arm_canonicalize_syscall): New function.
	(arm_all_but_pc_registers_record): New function.
	(arm_linux_syscall_record): New function.
	(arm_linux_init_abi): Add syscall recording constructs.
	* arm-tdep.c (thumb_record_ldm_stm_swi): Update thumb syscall decoding.
	(arm_record_coproc_data_proc): Update arm syscall decoding.
	* arm-tdep.h (struct gdbarch_tdep) <arm_swi_record>: Remove.
	<arm_syscall_record>: New field.

---
 gdb/arm-linux-tdep.c |  248 +++++++++++++++++++++++++++++++++++++++++++++++++-
 gdb/arm-tdep.c       |   50 ++++++----
 gdb/arm-tdep.h       |    4 +-
 3 files changed, 280 insertions(+), 22 deletions(-)

diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index 7546d34..e7a4338 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -44,6 +44,9 @@
 #include "gdbthread.h"
 #include "symfile.h"
 
+#include "record-full.h"
+#include "linux-record.h"
+
 #include "cli/cli-utils.h"
 #include "stap-probe.h"
 #include "parser-defs.h"
@@ -1231,6 +1234,92 @@ arm_stap_parse_special_token (struct gdbarch *gdbarch,
   return 1;
 }
 
+/* ARM process record-replay constructs; syscall, signal etc.  */
+
+struct linux_record_tdep arm_linux_record_tdep;
+
+/* arm_canonicalize_syscall maps from the native arm Linux set
+   of syscall ids into a canonical set of syscall ids used by
+   process record.  */
+
+static enum gdb_syscall
+arm_canonicalize_syscall (int syscall)
+{
+  enum { sys_process_vm_writev = 377 };
+
+  if (syscall <= gdb_sys_sched_getaffinity)
+    return syscall;
+  else if (syscall >= 243 && syscall <= 247 )
+    return syscall + 2;
+  else if (syscall >= 248 && syscall <= 253 )
+    return syscall + 4;
+
+  return -1;
+}
+
+/* Record all registers but PC register for process-record.  */
+
+static int
+arm_all_but_pc_registers_record (struct regcache *regcache)
+{
+  int i;
+
+  for (i = 0; i < ARM_PC_REGNUM; i++)
+    {
+      if (record_full_arch_list_add_reg (regcache, ARM_A1_REGNUM + i))
+        return -1;
+    }
+
+  if (record_full_arch_list_add_reg (regcache, ARM_PS_REGNUM))
+    return -1;
+
+  return 0;
+}
+
+/* Handler for arm system call instruction recording.  */
+
+static int
+arm_linux_syscall_record (struct regcache *regcache, unsigned long svc_number)
+{
+  int ret = 0;
+  enum gdb_syscall syscall_gdb;
+
+  syscall_gdb = arm_canonicalize_syscall (svc_number);
+
+  if (syscall_gdb < 0)
+    {
+      printf_unfiltered (_("Process record and replay target doesn't "
+                           "support syscall number %s\n"),
+                           plongest (svc_number));
+      return -1;
+    }
+
+  if (syscall_gdb == gdb_sys_sigreturn
+      || syscall_gdb == gdb_sys_rt_sigreturn)
+   {
+     if (arm_all_but_pc_registers_record (regcache))
+       return -1;
+     return 0;
+   }
+
+  ret = record_linux_system_call (syscall_gdb, regcache,
+                                  &arm_linux_record_tdep);
+  if (ret != 0)
+    return ret;
+
+  /* Record the return value of the system call.  */
+  if (record_full_arch_list_add_reg (regcache, ARM_A1_REGNUM))
+    return -1;
+  /* Record LR.  */
+  if (record_full_arch_list_add_reg (regcache, ARM_LR_REGNUM))
+    return -1;
+  /* Record CPSR.  */
+  if (record_full_arch_list_add_reg (regcache, ARM_PS_REGNUM))
+    return -1;
+
+  return 0;
+}
+
 static void
 arm_linux_init_abi (struct gdbarch_info info,
 		    struct gdbarch *gdbarch)
@@ -1350,7 +1439,164 @@ arm_linux_init_abi (struct gdbarch_info info,
   set_gdbarch_get_syscall_number (gdbarch, arm_linux_get_syscall_number);
 
   /* Syscall record.  */
-  tdep->arm_swi_record = NULL;
+  tdep->arm_syscall_record = arm_linux_syscall_record;
+
+  /* Initialize the arm_linux_record_tdep.  */
+  /* These values are the size of the type that will be used in a system
+     call.  They are obtained from Linux Kernel source.  */
+  arm_linux_record_tdep.size_pointer
+    = gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size__old_kernel_stat = 32;
+  arm_linux_record_tdep.size_tms = 16;
+  arm_linux_record_tdep.size_loff_t = 8;
+  arm_linux_record_tdep.size_flock = 16;
+  arm_linux_record_tdep.size_oldold_utsname = 45;
+  arm_linux_record_tdep.size_ustat = 20;
+  arm_linux_record_tdep.size_old_sigaction = 140;
+  arm_linux_record_tdep.size_old_sigset_t = 128;
+  arm_linux_record_tdep.size_rlimit = 8;
+  arm_linux_record_tdep.size_rusage = 72;
+  arm_linux_record_tdep.size_timeval = 8;
+  arm_linux_record_tdep.size_timezone = 8;
+  arm_linux_record_tdep.size_old_gid_t = 2;
+  arm_linux_record_tdep.size_old_uid_t = 2;
+  arm_linux_record_tdep.size_fd_set = 128;
+  arm_linux_record_tdep.size_dirent = 268;
+  arm_linux_record_tdep.size_dirent64 = 276;
+  arm_linux_record_tdep.size_statfs = 64;
+  arm_linux_record_tdep.size_statfs64 = 84;
+  arm_linux_record_tdep.size_sockaddr = 16;
+  arm_linux_record_tdep.size_int
+    = gdbarch_int_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size_long
+    = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size_ulong
+    = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size_msghdr = 28;
+  arm_linux_record_tdep.size_itimerval = 16;
+  arm_linux_record_tdep.size_stat = 88;
+  arm_linux_record_tdep.size_old_utsname = 325;
+  arm_linux_record_tdep.size_sysinfo = 64;
+  arm_linux_record_tdep.size_msqid_ds = 88;
+  arm_linux_record_tdep.size_shmid_ds = 84;
+  arm_linux_record_tdep.size_new_utsname = 390;
+  arm_linux_record_tdep.size_timex = 128;
+  arm_linux_record_tdep.size_mem_dqinfo = 24;
+  arm_linux_record_tdep.size_if_dqblk = 68;
+  arm_linux_record_tdep.size_fs_quota_stat = 68;
+  arm_linux_record_tdep.size_timespec = 8;
+  arm_linux_record_tdep.size_pollfd = 8;
+  arm_linux_record_tdep.size_NFS_FHSIZE = 32;
+  arm_linux_record_tdep.size_knfsd_fh = 132;
+  arm_linux_record_tdep.size_TASK_COMM_LEN = 16;
+  arm_linux_record_tdep.size_sigaction = 140;
+  arm_linux_record_tdep.size_sigset_t = 8;
+  arm_linux_record_tdep.size_siginfo_t = 128;
+  arm_linux_record_tdep.size_cap_user_data_t = 12;
+  arm_linux_record_tdep.size_stack_t = 12;
+  arm_linux_record_tdep.size_off_t = arm_linux_record_tdep.size_long;
+  arm_linux_record_tdep.size_stat64 = 96;
+  arm_linux_record_tdep.size_gid_t = 2;
+  arm_linux_record_tdep.size_uid_t = 2;
+  arm_linux_record_tdep.size_PAGE_SIZE = 4096;
+  arm_linux_record_tdep.size_flock64 = 24;
+  arm_linux_record_tdep.size_user_desc = 16;
+  arm_linux_record_tdep.size_io_event = 32;
+  arm_linux_record_tdep.size_iocb = 64;
+  arm_linux_record_tdep.size_epoll_event = 12;
+  arm_linux_record_tdep.size_itimerspec
+    = arm_linux_record_tdep.size_timespec * 2;
+  arm_linux_record_tdep.size_mq_attr = 32;
+  arm_linux_record_tdep.size_siginfo = 128;
+  arm_linux_record_tdep.size_termios = 36;
+  arm_linux_record_tdep.size_termios2 = 44;
+  arm_linux_record_tdep.size_pid_t = 4;
+  arm_linux_record_tdep.size_winsize = 8;
+  arm_linux_record_tdep.size_serial_struct = 60;
+  arm_linux_record_tdep.size_serial_icounter_struct = 80;
+  arm_linux_record_tdep.size_hayes_esp_config = 12;
+  arm_linux_record_tdep.size_size_t = 4;
+  arm_linux_record_tdep.size_iovec = 8;
+
+  /* These values are the second argument of system call "sys_ioctl".
+     They are obtained from Linux Kernel source.  */
+  arm_linux_record_tdep.ioctl_TCGETS = 0x5401;
+  arm_linux_record_tdep.ioctl_TCSETS = 0x5402;
+  arm_linux_record_tdep.ioctl_TCSETSW = 0x5403;
+  arm_linux_record_tdep.ioctl_TCSETSF = 0x5404;
+  arm_linux_record_tdep.ioctl_TCGETA = 0x5405;
+  arm_linux_record_tdep.ioctl_TCSETA = 0x5406;
+  arm_linux_record_tdep.ioctl_TCSETAW = 0x5407;
+  arm_linux_record_tdep.ioctl_TCSETAF = 0x5408;
+  arm_linux_record_tdep.ioctl_TCSBRK = 0x5409;
+  arm_linux_record_tdep.ioctl_TCXONC = 0x540a;
+  arm_linux_record_tdep.ioctl_TCFLSH = 0x540b;
+  arm_linux_record_tdep.ioctl_TIOCEXCL = 0x540c;
+  arm_linux_record_tdep.ioctl_TIOCNXCL = 0x540d;
+  arm_linux_record_tdep.ioctl_TIOCSCTTY = 0x540e;
+  arm_linux_record_tdep.ioctl_TIOCGPGRP = 0x540f;
+  arm_linux_record_tdep.ioctl_TIOCSPGRP = 0x5410;
+  arm_linux_record_tdep.ioctl_TIOCOUTQ = 0x5411;
+  arm_linux_record_tdep.ioctl_TIOCSTI = 0x5412;
+  arm_linux_record_tdep.ioctl_TIOCGWINSZ = 0x5413;
+  arm_linux_record_tdep.ioctl_TIOCSWINSZ = 0x5414;
+  arm_linux_record_tdep.ioctl_TIOCMGET = 0x5415;
+  arm_linux_record_tdep.ioctl_TIOCMBIS = 0x5416;
+  arm_linux_record_tdep.ioctl_TIOCMBIC = 0x5417;
+  arm_linux_record_tdep.ioctl_TIOCMSET = 0x5418;
+  arm_linux_record_tdep.ioctl_TIOCGSOFTCAR = 0x5419;
+  arm_linux_record_tdep.ioctl_TIOCSSOFTCAR = 0x541a;
+  arm_linux_record_tdep.ioctl_FIONREAD = 0x541b;
+  arm_linux_record_tdep.ioctl_TIOCINQ = arm_linux_record_tdep.ioctl_FIONREAD;
+  arm_linux_record_tdep.ioctl_TIOCLINUX = 0x541c;
+  arm_linux_record_tdep.ioctl_TIOCCONS = 0x541d;
+  arm_linux_record_tdep.ioctl_TIOCGSERIAL = 0x541e;
+  arm_linux_record_tdep.ioctl_TIOCSSERIAL = 0x541f;
+  arm_linux_record_tdep.ioctl_TIOCPKT = 0x5420;
+  arm_linux_record_tdep.ioctl_FIONBIO = 0x5421;
+  arm_linux_record_tdep.ioctl_TIOCNOTTY = 0x5422;
+  arm_linux_record_tdep.ioctl_TIOCSETD = 0x5423;
+  arm_linux_record_tdep.ioctl_TIOCGETD = 0x5424;
+  arm_linux_record_tdep.ioctl_TCSBRKP = 0x5425;
+  arm_linux_record_tdep.ioctl_TIOCTTYGSTRUCT = 0x5426;
+  arm_linux_record_tdep.ioctl_TIOCSBRK = 0x5427;
+  arm_linux_record_tdep.ioctl_TIOCCBRK = 0x5428;
+  arm_linux_record_tdep.ioctl_TIOCGSID = 0x5429;
+  arm_linux_record_tdep.ioctl_TCGETS2 = 0x802c542a;
+  arm_linux_record_tdep.ioctl_TCSETS2 = 0x402c542b;
+  arm_linux_record_tdep.ioctl_TCSETSW2 = 0x402c542c;
+  arm_linux_record_tdep.ioctl_TCSETSF2 = 0x402c542d;
+  arm_linux_record_tdep.ioctl_TIOCGPTN = 0x80045430;
+  arm_linux_record_tdep.ioctl_TIOCSPTLCK = 0x40045431;
+  arm_linux_record_tdep.ioctl_FIONCLEX = 0x5450;
+  arm_linux_record_tdep.ioctl_FIOCLEX = 0x5451;
+  arm_linux_record_tdep.ioctl_FIOASYNC = 0x5452;
+  arm_linux_record_tdep.ioctl_TIOCSERCONFIG = 0x5453;
+  arm_linux_record_tdep.ioctl_TIOCSERGWILD = 0x5454;
+  arm_linux_record_tdep.ioctl_TIOCSERSWILD = 0x5455;
+  arm_linux_record_tdep.ioctl_TIOCGLCKTRMIOS = 0x5456;
+  arm_linux_record_tdep.ioctl_TIOCSLCKTRMIOS = 0x5457;
+  arm_linux_record_tdep.ioctl_TIOCSERGSTRUCT = 0x5458;
+  arm_linux_record_tdep.ioctl_TIOCSERGETLSR = 0x5459;
+  arm_linux_record_tdep.ioctl_TIOCSERGETMULTI = 0x545a;
+  arm_linux_record_tdep.ioctl_TIOCSERSETMULTI = 0x545b;
+  arm_linux_record_tdep.ioctl_TIOCMIWAIT = 0x545c;
+  arm_linux_record_tdep.ioctl_TIOCGICOUNT = 0x545d;
+  arm_linux_record_tdep.ioctl_TIOCGHAYESESP = 0x545e;
+  arm_linux_record_tdep.ioctl_TIOCSHAYESESP = 0x545f;
+  arm_linux_record_tdep.ioctl_FIOQSIZE = 0x5460;
+
+  /* These values are the second argument of system call "sys_fcntl"
+     and "sys_fcntl64".  They are obtained from Linux Kernel source.  */
+  arm_linux_record_tdep.fcntl_F_GETLK = 5;
+  arm_linux_record_tdep.fcntl_F_GETLK64 = 12;
+  arm_linux_record_tdep.fcntl_F_SETLK64 = 13;
+  arm_linux_record_tdep.fcntl_F_SETLKW64 = 14;
+
+  arm_linux_record_tdep.arg1 = ARM_A1_REGNUM + 1;
+  arm_linux_record_tdep.arg2 = ARM_A1_REGNUM + 2;
+  arm_linux_record_tdep.arg3 = ARM_A1_REGNUM + 3;
+  arm_linux_record_tdep.arg4 = ARM_A1_REGNUM + 3;
 }
 
 /* Provide a prototype to silence -Wmissing-prototypes.  */
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index f7a214f..2a61dbd 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11925,27 +11925,38 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
   struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
   struct regcache *reg_cache = arm_insn_r->regcache;
   uint32_t ret = 0; /* function return value: -1:record failure ;  0:success  */
-
-  /* Handle SWI insn; system call would be handled over here.  */
+  ULONGEST u_regval = 0;
 
   arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
+
+  /* Handle arm SWI/SVC system call instructions.  */
   if (15 == arm_insn_r->opcode)
-  {
-    /* Handle arm syscall insn.  */
-    if (tdep->arm_swi_record != NULL)
-      {
-        ret = tdep->arm_swi_record(reg_cache);
-      }
-    else
-      {
-        printf_unfiltered (_("no syscall record support\n"));
-        ret = -1;
-      }
-  }
+    {
+      if (tdep->arm_syscall_record != NULL)
+        {
+          ULONGEST svc_operand, svc_number;
+
+          svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
+
+          if (svc_operand)  /* OABI.  */
+            svc_number = svc_operand - 0x900000;
+          else /* EABI.  */
+            regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
+
+          ret = tdep->arm_syscall_record (reg_cache, svc_number);
+        }
+      else
+        {
+          printf_unfiltered (_("no syscall record support\n"));
+          ret = -1;
+        }
+    }
+  else
+    {
+      arm_record_unsupported_insn (arm_insn_r);
+      ret = -1;
+    }
 
-  printf_unfiltered (_("Process record does not support instruction "
-                        "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
-                        paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
   return ret;
 }
 
@@ -12336,9 +12347,10 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
   else if (0x1F == opcode1)
     {
         /* Handle arm syscall insn.  */
-        if (tdep->arm_swi_record != NULL)
+        if (tdep->arm_syscall_record != NULL)
           {
-            ret = tdep->arm_swi_record(reg_cache);
+            regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
+            ret = tdep->arm_syscall_record (reg_cache, u_regval);
           }
         else
           {
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index a1a2be5..b584a43 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -205,8 +205,8 @@ struct gdbarch_tdep
      instruction.  */
   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 
-   /* Parse swi insn args, sycall record.  */
-  int (*arm_swi_record) (struct regcache *regcache);
+   /* syscall record.  */
+  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
 };
 
 /* Structures used for displaced stepping.  */
-- 
1.7.9.5

[PATCH v2 7/7] Adds a NEWS entry for arm record/replay improvements

[Omair Javaid]

This patch adds a news entry about improvements in record-replay and
reverse debugging support for arm*-linux* targets.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* NEWS: Add note on improved process record-replay on arm*-linux*
	targets.

---
 gdb/NEWS |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/gdb/NEWS b/gdb/NEWS
index 10834df..bcf3e09 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -3,6 +3,10 @@
 
 *** Changes since GDB 7.6
 
+* Improved support of process record-replay and reverse debugging on
+  arm*-linux* targets.  Support for thumb32 and syscall instructions
+  recording has been added.
+
 * GDB now supports Fission DWP file format version 2.
   http://gcc.gnu.org/wiki/DebugFission
 
-- 
1.7.9.5

[PATCH v2 1/7] Fix for memory record corruption due to 64bit addresses

[Omair Javaid]

This patch changes record memory address type to unsigned 32bit integers.
On targets where CORE_ADDR configures to become a unsigned 64bit value the
arm process record code fails resulting in various testsuite failures.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (struct arm_mem_r) <addr>: Change type to unit32_t.

---
 gdb/arm-tdep.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 7c78a61..223a7db 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -10618,7 +10618,7 @@ vfp - VFP co-processor."),
 struct arm_mem_r
 {
   uint32_t len;    /* Record length.  */
-  CORE_ADDR addr;  /* Memory address.  */
+  uint32_t addr;   /* Memory address.  */
 };
 
 /* ARM instruction record contains opcode of current insn
-- 
1.7.9.5

[PATCH v2 2/7] Fix for bugs in push and ldm instructions decoding

[Omair Javaid]

This patch corrects the register numbers and removes multiple loops in
recording procedure of instructions involving multiple registers.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (thumb_record_misc): Update to correct logical error while
	recording ldm, ldmia and pop instructions.


---
 gdb/arm-tdep.c |   61 +++++++++++++++++---------------------------------------
 1 file changed, 18 insertions(+), 43 deletions(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 223a7db..24bacf8 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11786,26 +11786,15 @@ arm_record_ld_st_multiple (insn_decode_record *arm_insn_r)
       while (register_bits)
       {
         if (register_bits & 0x00000001)
-          register_list[register_count++] = 1;
+          record_buf[index++] = register_count;
         register_bits = register_bits >> 1;
+        register_count++;
       }
 
         /* Extra space for Base Register and CPSR; wihtout optimization.  */
-        record_buf[register_count] = reg_src1;
-        record_buf[register_count + 1] = ARM_PS_REGNUM;
-        arm_insn_r->reg_rec_count = register_count + 2;
-
-        for (register_count = 0; register_count < no_of_regs; register_count++)
-          {
-            if  (register_list[register_count])
-              {
-                /* Register_count gives total no of registers
-                and dually working as reg number.  */
-                record_buf[index] = register_count;
-                index++;
-              }
-          }
-
+        record_buf[index++] = reg_src1;
+        record_buf[index++] = ARM_PS_REGNUM;
+        arm_insn_r->reg_rec_count = index;
     }
   else
     {
@@ -12209,22 +12198,15 @@ thumb_record_misc (insn_decode_record *thumb_insn_r)
       /* POP.  */
       register_bits = bits (thumb_insn_r->arm_insn, 0, 7);
       while (register_bits)
-        {
-          if (register_bits & 0x00000001)
-            register_list[register_count++] = 1;
-          register_bits = register_bits >> 1;
-        }
-      record_buf[register_count] = ARM_PS_REGNUM;
-      record_buf[register_count + 1] = ARM_SP_REGNUM;
-      thumb_insn_r->reg_rec_count = register_count + 2;
-      for (register_count = 0; register_count < 8; register_count++)
-        {
-          if  (register_list[register_count])
-            {
-              record_buf[index] = register_count;
-              index++;
-            }
-        }
+      {
+        if (register_bits & 0x00000001)
+          record_buf[index++] = register_count;
+        register_bits = register_bits >> 1;
+        register_count++;
+      }
+      record_buf[index++] = ARM_PS_REGNUM;
+      record_buf[index++] = ARM_SP_REGNUM;
+      thumb_insn_r->reg_rec_count = index;
     }
   else if (10 == opcode2)
     {
@@ -12321,19 +12303,12 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
       while (register_bits)
         {
           if (register_bits & 0x00000001)
-            register_list[register_count++] = 1;
+            record_buf[index++] = register_count;
           register_bits = register_bits >> 1;
+          register_count++;
         }
-      record_buf[register_count] = reg_src1;
-      thumb_insn_r->reg_rec_count = register_count + 1;
-      for (register_count = 0; register_count < 8; register_count++)
-        {
-          if (register_list[register_count])
-            {
-              record_buf[index] = register_count;
-              index++;
-            }
-        }
+      record_buf[index++] = reg_src1;
+      thumb_insn_r->reg_rec_count = index;
     }
   else if (0 == opcode2)
     {
-- 
1.7.9.5

[PATCH v2 6/7] Updates configure.tgt and enables gdb.reverse testsuite

[Omair Javaid]

This patch adds linux-record.o to gdb_target_obs in configure.tgt and
enables gdb.reverse testsuite for arm*-linux* targets.

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* configure.tgt: Add linux-record.o to gdb_target_obs.

gdb/testsuite:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* lib/gdb.exp (supports_process_record): Return true for arm*-linux*.

---
 gdb/configure.tgt         |    2 +-
 gdb/testsuite/lib/gdb.exp |    6 ++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index ea0faf1..5410f72 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -89,7 +89,7 @@ arm*-wince-pe | arm*-*-mingw32ce*)
 arm*-*-linux*)
 	# Target: ARM based machine running GNU/Linux
 	gdb_target_obs="arm-tdep.o arm-linux-tdep.o glibc-tdep.o \
-			solib-svr4.o symfile-mem.o linux-tdep.o"
+			solib-svr4.o symfile-mem.o linux-tdep.o linux-record.o"
 	build_gdbserver=yes
 	;;
 arm*-*-netbsd* | arm*-*-knetbsd*-gnu)
diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp
index bde4e48..047aefb 100644
--- a/gdb/testsuite/lib/gdb.exp
+++ b/gdb/testsuite/lib/gdb.exp
@@ -1774,7 +1774,8 @@ proc supports_process_record {} {
 	return [target_info gdb,use_precord]
     }
 
-    if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"] } {
+    if { [istarget "arm*-*-linux*"] || [istarget "x86_64-*-linux*"]
+         || [istarget "i\[34567\]86-*-linux*"] } {
 	return 1
     }
 
@@ -1789,7 +1790,8 @@ proc supports_reverse {} {
 	return [target_info gdb,can_reverse]
     }
 
-    if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"] } {
+    if { [istarget "arm*-*-linux*"] || [istarget "x86_64-*-linux*"]
+         || [istarget "i\[34567\]86-*-linux*"] } {
 	return 1
     }
 
-- 
1.7.9.5

Re: [PATCH v2 7/7] Adds a NEWS entry for arm record/replay improvements

[Eli Zaretskii]

> From: Omair Javaid <omair.javaid@linaro.org>
> Cc: patches@linaro.org
> Date: Sat,  4 Jan 2014 00:15:36 +0500
> 
> This patch adds a news entry about improvements in record-replay and
> reverse debugging support for arm*-linux* targets.
> 
> gdb:
> 
> 2014-01-03  Omair Javaid  <omair.javaid@linaro.org>
> 
> 	* NEWS: Add note on improved process record-replay on arm*-linux*
> 	targets.

OK.

Re: [PATCH v2 6/7] Updates configure.tgt and enables gdb.reverse testsuite

[Yao Qi]

Hi,
We should mention change in proc supports_reverse too.

On 01/04/2014 03:15 AM, Omair Javaid wrote:
> 	* lib/gdb.exp (supports_process_record): Return true for arm*-linux*.

	(supports_reverse): Likewise.

-- 
Yao (齐尧)

Re: [PATCH v2 2/7] Fix for bugs in push and ldm instructions decoding

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:
> This patch corrects the register numbers and removes multiple loops in
> recording procedure of instructions involving multiple registers.
> 

OK, thanks.

-- 
Pedro Alves

Re: [PATCH v2 1/7] Fix for memory record corruption due to 64bit addresses

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:
> This patch changes record memory address type to unsigned 32bit integers.
> On targets where CORE_ADDR configures to become a unsigned 64bit value the
> arm process record code fails resulting in various testsuite failures.
> 
> gdb:
> 
> 2014-01-03  Omair Javaid  <omair.javaid@linaro.org>
> 
> 	* arm-tdep.c (struct arm_mem_r) <addr>: Change type to unit32_t.

uint32_t.

Other than that looks fine.

Thanks,
-- 
Pedro Alves

Re: [PATCH v2 3/7] Fix for bug in pop instruction decoding

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:
> This patch fixes thumb push instruction recording by replacing base register
> from pc to sp.

OK.

-- 
Pedro Alves

Re: [PATCH v2 5/7] Adds support for thumb32 instructions recording

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:
> +  switch (op1)
> +    {
> +      /* Store byte instructions.  */
> +      case 4:
> +      case 0:
> +        record_buf_mem[0] = 1;
> +      break;

"break;" should be aligned with the above statement,
not with "case".  Several instances of this.

> +      /* Swap first half of 32bit thumb instruction with second half.  */
> +      arm_record->arm_insn = (arm_record->arm_insn >> 16) |
> +                             (arm_record->arm_insn << 16);

'|' goes on the next line. But then you'd need to wrap the whole
thing with an extra set of parens.  Write instead:

      arm_record->arm_insn
         = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);

> +
> +      insn_id = thumb2_record_decode_insn_handler (arm_record);
> +
> +      if (insn_id != ARM_RECORD_SUCCESS)
> +        {
> +          arm_record_unsupported_insn(arm_record);

Missing space before parens.

> +          ret = -1;
> +        }
>      }
>    else

Otherwise looks fine to me.

Thanks,
-- 
Pedro Alves

Re: [PATCH v2 4/7] Adds support for recording system call instructions

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:
> +
> +  ret = record_linux_system_call (syscall_gdb, regcache,
> +                                  &arm_linux_record_tdep);

This new call must mean this patch breaks the build until
patch 6 is applied:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* configure.tgt: Add linux-record.o to gdb_target_obs.

as record_linux_system_call is defined in linux-record.c.

Please split that hunk from patch 6, and merge it into
this one instead.  The series (and therefore the resulting
gdb history) should build and remain functional at each
incremental step, to avoid bisecting problems.

> +/* ARM process record-replay constructs; syscall, signal etc.  */

Should be ':' instead of ';'.

> +
> +struct linux_record_tdep arm_linux_record_tdep;

Other than that, the patch looks fine to me.

-- 
Pedro Alves

Re: [PATCH v2 0/7] ARM record/replay and reverse debugging improvements

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:
> This patch series improves gdb process record and reverse debugging
> capabilities for arm targets. Here is the list of 7 patches in this series 
> and their description:

Thanks a lot of re-splitting the series and sending it like this.
It really makes it a lot easier to digest.  Much appreciated.

-- 
Pedro Alves

Re: [PATCH v2 5/7] Adds support for thumb32 instructions recording

[Omair Javaid]

On 01/07/2014 12:52 AM, Pedro Alves wrote:
> On 01/03/2014 07:15 PM, Omair Javaid wrote:
>> +  switch (op1)
>> +    {
>> +      /* Store byte instructions.  */
>> +      case 4:
>> +      case 0:
>> +        record_buf_mem[0] = 1;
>> +      break;
> 
> "break;" should be aligned with the above statement,
> not with "case".  Several instances of this.
> 
>> +      /* Swap first half of 32bit thumb instruction with second half.  */
>> +      arm_record->arm_insn = (arm_record->arm_insn >> 16) |
>> +                             (arm_record->arm_insn << 16);
> 
> '|' goes on the next line. But then you'd need to wrap the whole
> thing with an extra set of parens.  Write instead:
> 
>       arm_record->arm_insn
>          = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
> 
>> +
>> +      insn_id = thumb2_record_decode_insn_handler (arm_record);
>> +
>> +      if (insn_id != ARM_RECORD_SUCCESS)
>> +        {
>> +          arm_record_unsupported_insn(arm_record);
> 
> Missing space before parens.
> 
>> +          ret = -1;
>> +        }
>>      }
>>    else
> 
> Otherwise looks fine to me.
> 
> Thanks,
> 

Updated patch after incorporating suggestions:

gdb:

2014-01-09  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (enum arm_record_result): New enum.
	(arm_record_unsupported_insn): New function.
	(arm_record_coproc_data_proc): Removed.
	(thumb2_record_ld_st_multiple): New function.
	(thumb2_record_ld_st_dual_ex_tbb): New function.
	(thumb2_record_data_proc_sreg_mimm): New function.
	(thumb2_record_ps_dest_generic): New function.
	(thumb2_record_branch_misc_cntrl): New function.
	(thumb2_record_str_single_data): New function.
	(thumb2_record_ld_mem_hints): New function.
	(thumb2_record_ld_word): New function.
	(thumb2_record_lmul_lmla_div): New function.
	(thumb2_record_decode_insn_handler): New function.
	(decode_insn): Add thumb32 instruction handlers.

---
 gdb/arm-tdep.c |  603 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 596 insertions(+), 7 deletions(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 7c78a61..bcd76b2 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -10666,6 +10666,11 @@ sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
   return 1;
 }
 
+enum arm_record_result {
+  ARM_RECORD_SUCCESS = 0,
+  ARM_RECORD_FAILURE = 1
+};
+
 typedef enum
 {
   ARM_RECORD_STRH=1,
@@ -11919,7 +11924,7 @@ arm_record_b_bl (insn_decode_record *arm_insn_r)
 /* Handling opcode 110 insns.  */
 
 static int
-arm_record_coproc (insn_decode_record *arm_insn_r)
+arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
 {
   printf_unfiltered (_("Process record does not support instruction "
                     "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
@@ -12414,6 +12419,581 @@ thumb_record_branch (insn_decode_record *thumb_insn_r)
   return 0;     
 }
 
+/* Handler for thumb2 load/store multiple instructions.  */
+
+static int
+thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
+{
+  struct regcache *reg_cache = thumb2_insn_r->regcache;
+
+  uint32_t reg_rn, op;
+  uint32_t register_bits = 0, register_count = 0;
+  uint32_t index = 0, start_address = 0;
+  uint32_t record_buf[24], record_buf_mem[48];
+
+  ULONGEST u_regval = 0;
+
+  reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+  op = bits (thumb2_insn_r->arm_insn, 23, 24);
+
+  if (0 == op || 3 == op)
+    {
+      if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+        {
+          /* Handle RFE instruction.  */
+          record_buf[0] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+      else
+        {
+          /* Handle SRS instruction after reading banked SP.  */
+          return arm_record_unsupported_insn (thumb2_insn_r);
+        }
+    }
+  else if (1 == op || 2 == op)
+    {
+      if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+        {
+          /* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions.  */
+          register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
+          while (register_bits)
+            {
+              if (register_bits & 0x00000001)
+                record_buf[index++] = register_count;
+
+              register_count++;
+              register_bits = register_bits >> 1;
+            }
+          record_buf[index++] = reg_rn;
+          record_buf[index++] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = index;
+        }
+      else
+        {
+          /* Handle STM/STMIA/STMEA and STMDB/STMFD.  */
+          register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
+          regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
+          while (register_bits)
+            {
+              if (register_bits & 0x00000001)
+                register_count++;
+
+              register_bits = register_bits >> 1;
+            }
+
+          if (1 == op)
+            {
+              /* Start address calculation for LDMDB/LDMEA.  */
+              start_address = u_regval;
+            }
+          else if (2 == op)
+            {
+              /* Start address calculation for LDMDB/LDMEA.  */
+              start_address = u_regval - register_count * 4;
+            }
+
+          thumb2_insn_r->mem_rec_count = register_count;
+          while (register_count)
+            {
+              record_buf_mem[register_count * 2 - 1] = start_address;
+              record_buf_mem[register_count * 2 - 2] = 4;
+              start_address = start_address + 4;
+              register_count--;
+            }
+          record_buf[0] = reg_rn;
+          record_buf[1] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 2;
+        }
+    }
+
+  MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+            record_buf_mem);
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 load/store (dual/exclusive) and table branch
+   instructions.  */
+
+static int
+thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
+{
+  struct regcache *reg_cache = thumb2_insn_r->regcache;
+
+  uint32_t reg_rd, reg_rn, offset_imm;
+  uint32_t reg_dest1, reg_dest2;
+  uint32_t address, offset_addr;
+  uint32_t record_buf[8], record_buf_mem[8];
+  uint32_t op1, op2, op3;
+  LONGEST s_word;
+
+  ULONGEST u_regval[2];
+
+  op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
+  op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
+  op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
+
+  if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
+    {
+      if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
+        {
+          reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
+          record_buf[0] = reg_dest1;
+          record_buf[1] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 2;
+        }
+
+      if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
+        {
+          reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
+          record_buf[2] = reg_dest2;
+          thumb2_insn_r->reg_rec_count = 3;
+        }
+    }
+  else
+    {
+      reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+      regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
+
+      if (0 == op1 && 0 == op2)
+        {
+          /* Handle STREX.  */
+          offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
+          address = u_regval[0] + (offset_imm * 4);
+          record_buf_mem[0] = 4;
+          record_buf_mem[1] = address;
+          thumb2_insn_r->mem_rec_count = 1;
+          reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
+          record_buf[0] = reg_rd;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+      else if (1 == op1 && 0 == op2)
+        {
+          reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
+          record_buf[0] = reg_rd;
+          thumb2_insn_r->reg_rec_count = 1;
+          address = u_regval[0];
+          record_buf_mem[1] = address;
+
+          if (4 == op3)
+            {
+              /* Handle STREXB.  */
+              record_buf_mem[0] = 1;
+              thumb2_insn_r->mem_rec_count = 1;
+            }
+          else if (5 == op3)
+            {
+              /* Handle STREXH.  */
+              record_buf_mem[0] = 2 ;
+              thumb2_insn_r->mem_rec_count = 1;
+            }
+          else if (7 == op3)
+            {
+              /* Handle STREXD.  */
+              address = u_regval[0];
+              record_buf_mem[0] = 4;
+              record_buf_mem[2] = 4;
+              record_buf_mem[3] = address + 4;
+              thumb2_insn_r->mem_rec_count = 2;
+            }
+        }
+      else
+        {
+          offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
+
+          if (bit (thumb2_insn_r->arm_insn, 24))
+            {
+              if (bit (thumb2_insn_r->arm_insn, 23))
+                offset_addr = u_regval[0] + (offset_imm * 4);
+              else
+                offset_addr = u_regval[0] - (offset_imm * 4);
+
+              address = offset_addr;
+            }
+          else
+            address = u_regval[0];
+
+          record_buf_mem[0] = 4;
+          record_buf_mem[1] = address;
+          record_buf_mem[2] = 4;
+          record_buf_mem[3] = address + 4;
+          thumb2_insn_r->mem_rec_count = 2;
+          record_buf[0] = reg_rn;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+    }
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+            record_buf_mem);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 data processing (shift register and modified immediate)
+   instructions.  */
+
+static int
+thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t reg_rd, op;
+  uint32_t record_buf[8];
+
+  op = bits (thumb2_insn_r->arm_insn, 21, 24);
+  reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
+
+  if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
+    {
+      record_buf[0] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 1;
+    }
+  else
+    {
+      record_buf[0] = reg_rd;
+      record_buf[1] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 2;
+    }
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Generic handler for thumb2 instructions which effect destination and PS
+   registers.  */
+
+static int
+thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t reg_rd;
+  uint32_t record_buf[8];
+
+  reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
+
+  record_buf[0] = reg_rd;
+  record_buf[1] = ARM_PS_REGNUM;
+  thumb2_insn_r->reg_rec_count = 2;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 branch and miscellaneous control instructions.  */
+
+static int
+thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t op, op1, op2;
+  uint32_t record_buf[8];
+
+  op = bits (thumb2_insn_r->arm_insn, 20, 26);
+  op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
+  op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
+
+  /* Handle MSR insn.  */
+  if (!(op1 & 0x2) && 0x38 == op)
+    {
+      if (!(op2 & 0x3))
+        {
+          /* CPSR is going to be changed.  */
+          record_buf[0] = ARM_PS_REGNUM;
+          thumb2_insn_r->reg_rec_count = 1;
+        }
+      else
+        {
+          arm_record_unsupported_insn(thumb2_insn_r);
+          return -1;
+        }
+    }
+  else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
+    {
+      /* BLX.  */
+      record_buf[0] = ARM_PS_REGNUM;
+      record_buf[1] = ARM_LR_REGNUM;
+      thumb2_insn_r->reg_rec_count = 2;
+    }
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 store single data item instructions.  */
+
+static int
+thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
+{
+  struct regcache *reg_cache = thumb2_insn_r->regcache;
+
+  uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
+  uint32_t address, offset_addr;
+  uint32_t record_buf[8], record_buf_mem[8];
+  uint32_t op1, op2;
+
+  ULONGEST u_regval[2];
+
+  op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
+  op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
+  reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+  regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
+
+  if (bit (thumb2_insn_r->arm_insn, 23))
+    {
+      /* T2 encoding.  */
+      offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
+      offset_addr = u_regval[0] + offset_imm;
+      address = offset_addr;
+    }
+  else
+    {
+      /* T3 encoding.  */
+      if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
+        {
+          /* Handle STRB (register).  */
+          reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
+          regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
+          shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
+          offset_addr = u_regval[1] << shift_imm;
+          address = u_regval[0] + offset_addr;
+        }
+      else
+        {
+          offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
+          if (bit (thumb2_insn_r->arm_insn, 10))
+            {
+              if (bit (thumb2_insn_r->arm_insn, 9))
+                offset_addr = u_regval[0] + offset_imm;
+              else
+                offset_addr = u_regval[0] - offset_imm;
+
+              address = offset_addr;
+            }
+          else
+            address = u_regval[0];
+        }
+    }
+
+  switch (op1)
+    {
+      /* Store byte instructions.  */
+      case 4:
+      case 0:
+        record_buf_mem[0] = 1;
+        break;
+      /* Store half word instructions.  */
+      case 1:
+      case 5:
+        record_buf_mem[0] = 2;
+        break;
+      /* Store word instructions.  */
+      case 2:
+      case 6:
+        record_buf_mem[0] = 4;
+        break;
+
+      default:
+        gdb_assert_not_reached ("no decoding pattern found");
+        break;
+    }
+
+  record_buf_mem[1] = address;
+  thumb2_insn_r->mem_rec_count = 1;
+  record_buf[0] = reg_rn;
+  thumb2_insn_r->reg_rec_count = 1;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
+            record_buf_mem);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 load memory hints instructions.  */
+
+static int
+thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t record_buf[8];
+  uint32_t reg_rt, reg_rn;
+
+  reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
+  reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+
+  if (ARM_PC_REGNUM != reg_rt)
+    {
+      record_buf[0] = reg_rt;
+      record_buf[1] = reg_rn;
+      record_buf[2] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 3;
+
+      REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+                record_buf);
+      return ARM_RECORD_SUCCESS;
+    }
+
+  return ARM_RECORD_FAILURE;
+}
+
+/* Handler for thumb2 load word instructions.  */
+
+static int
+thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t opcode1 = 0, opcode2 = 0;
+  uint32_t record_buf[8];
+
+  record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
+  record_buf[1] = ARM_PS_REGNUM;
+  thumb2_insn_r->reg_rec_count = 2;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Handler for thumb2 long multiply, long multiply accumulate, and
+   divide instructions.  */
+
+static int
+thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t opcode1 = 0, opcode2 = 0;
+  uint32_t record_buf[8];
+  uint32_t reg_src1 = 0;
+
+  opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
+  opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
+
+  if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
+    {
+      /* Handle SMULL, UMULL, SMULAL.  */
+      /* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S).  */
+      record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
+      record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
+      record_buf[2] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 3;
+    }
+  else if (1 == opcode1 || 3 == opcode2)
+    {
+      /* Handle SDIV and UDIV.  */
+      record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
+      record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
+      record_buf[2] = ARM_PS_REGNUM;
+      thumb2_insn_r->reg_rec_count = 3;
+    }
+  else
+    return ARM_RECORD_FAILURE;
+
+  REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
+            record_buf);
+  return ARM_RECORD_SUCCESS;
+}
+
+/* Decodes thumb2 instruction type and invokes its record handler.  */
+
+static unsigned int
+thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
+{
+  uint32_t op, op1, op2;
+
+  op = bit (thumb2_insn_r->arm_insn, 15);
+  op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
+  op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
+
+  if (op1 == 0x01)
+    {
+      if (!(op2 & 0x64 ))
+        {
+          /* Load/store multiple instruction.  */
+          return thumb2_record_ld_st_multiple (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x64) ^ 0x04))
+        {
+          /* Load/store (dual/exclusive) and table branch instruction.  */
+          return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x20) ^ 0x20))
+        {
+          /* Data-processing (shifted register).  */
+          return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
+        }
+      else if (op2 & 0x40)
+        {
+          /* Co-processor instructions.  */
+          arm_record_unsupported_insn (thumb2_insn_r);
+        }
+    }
+  else if (op1 == 0x02)
+    {
+      if (op)
+        {
+          /* Branches and miscellaneous control instructions.  */
+          return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
+        }
+      else if (op2 & 0x20)
+        {
+          /* Data-processing (plain binary immediate) instruction.  */
+          return thumb2_record_ps_dest_generic (thumb2_insn_r);
+        }
+      else
+        {
+          /* Data-processing (modified immediate).  */
+          return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
+        }
+    }
+  else if (op1 == 0x03)
+    {
+      if (!(op2 & 0x71 ))
+        {
+          /* Store single data item.  */
+          return thumb2_record_str_single_data (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x71) ^ 0x10))
+        {
+          /* Advanced SIMD or structure load/store instructions.  */
+          return arm_record_unsupported_insn (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x67) ^ 0x01))
+        {
+          /* Load byte, memory hints instruction.  */
+          return thumb2_record_ld_mem_hints (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x67) ^ 0x03))
+        {
+          /* Load halfword, memory hints instruction.  */
+          return thumb2_record_ld_mem_hints (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x67) ^ 0x05))
+        {
+          /* Load word instruction.  */
+          return thumb2_record_ld_word (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x70) ^ 0x20))
+        {
+          /* Data-processing (register) instruction.  */
+          return thumb2_record_ps_dest_generic (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x78) ^ 0x30))
+        {
+          /* Multiply, multiply accumulate, abs diff instruction.  */
+          return thumb2_record_ps_dest_generic (thumb2_insn_r);
+        }
+      else if (!((op2 & 0x78) ^ 0x38))
+        {
+          /* Long multiply, long multiply accumulate, and divide.  */
+          return thumb2_record_lmul_lmla_div (thumb2_insn_r);
+        }
+      else if (op2 & 0x40)
+        {
+          /* Co-processor instructions.  */
+          return arm_record_unsupported_insn (thumb2_insn_r);
+        }
+   }
+
+  return -1;
+}
 
 /* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success 
 and positive val on fauilure.  */
@@ -12452,7 +13032,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
     arm_record_ld_st_reg_offset,        /* 011.  */
     arm_record_ld_st_multiple,          /* 100.  */
     arm_record_b_bl,                    /* 101.  */
-    arm_record_coproc,                  /* 110.  */
+    arm_record_unsupported_insn,        /* 110.  */
     arm_record_coproc_data_proc         /* 111.  */
   };
 
@@ -12503,11 +13083,20 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
     }
   else if (THUMB2_RECORD == record_type)
     {
-      printf_unfiltered (_("Process record doesnt support thumb32 instruction "
-                           "0x%0x at address %s.\n"),arm_record->arm_insn,
-                           paddress (arm_record->gdbarch, 
-                           arm_record->this_addr));
-      ret = -1;
+      /* As thumb does not have condition codes, we set negative.  */
+      arm_record->cond = -1;
+
+      /* Swap first half of 32bit thumb instruction with second half.  */
+      arm_record->arm_insn
+        = (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
+
+      insn_id = thumb2_record_decode_insn_handler (arm_record);
+
+      if (insn_id != ARM_RECORD_SUCCESS)
+        {
+          arm_record_unsupported_insn (arm_record);
+          ret = -1;
+        }
     }
   else
     {
-- 
1.7.9.5

Re: [PATCH v2 1/7] Fix for memory record corruption due to 64bit addresses

[Omair Javaid]

On 01/07/2014 12:50 AM, Pedro Alves wrote:
> On 01/03/2014 07:15 PM, Omair Javaid wrote:
>> This patch changes record memory address type to unsigned 32bit integers.
>> On targets where CORE_ADDR configures to become a unsigned 64bit value the
>> arm process record code fails resulting in various testsuite failures.
>>
>> gdb:
>>
>> 2014-01-03  Omair Javaid  <omair.javaid@linaro.org>
>>
>> 	* arm-tdep.c (struct arm_mem_r) <addr>: Change type to unit32_t.
> 
> uint32_t.
> 
> Other than that looks fine.
> 
> Thanks,
> 

Made the required change:

gdb:

2014-01-03  Omair Javaid  <omair.javaid@linaro.org>

	* arm-tdep.c (struct arm_mem_r) <addr>: Change type to uint32_t.

---
 gdb/arm-tdep.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 7c78a61..223a7db 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -10618,7 +10618,7 @@ vfp - VFP co-processor."),
 struct arm_mem_r
 {
   uint32_t len;    /* Record length.  */
-  CORE_ADDR addr;  /* Memory address.  */
+  uint32_t addr;   /* Memory address.  */
 };
 
 /* ARM instruction record contains opcode of current insn
-- 
1.7.9.5

Re: [PATCH v2 4/7] Adds support for recording system call instructions

[Omair Javaid]

On 01/07/2014 12:52 AM, Pedro Alves wrote:
> On 01/03/2014 07:15 PM, Omair Javaid wrote:
>> +
>> +  ret = record_linux_system_call (syscall_gdb, regcache,
>> +                                  &arm_linux_record_tdep);
> 
> This new call must mean this patch breaks the build until
> patch 6 is applied:
> 
> 2014-01-03  Omair Javaid  <omair.javaid@linaro.org>
> 
> 	* configure.tgt: Add linux-record.o to gdb_target_obs.
> 
> as record_linux_system_call is defined in linux-record.c.
> 
> Please split that hunk from patch 6, and merge it into
> this one instead.  The series (and therefore the resulting
> gdb history) should build and remain functional at each
> incremental step, to avoid bisecting problems.
> 
>> +/* ARM process record-replay constructs; syscall, signal etc.  */
> 
> Should be ':' instead of ';'.
> 
>> +
>> +struct linux_record_tdep arm_linux_record_tdep;
> 
> Other than that, the patch looks fine to me.
> 

Patch updated after incorporating suggestions.

gdb:

2014-01-09  Omair Javaid  <omair.javaid@linaro.org>

	* arm-linux-tdep.c: Include "record-full.h" and "linux-record.h".
	(struct arm_linux_record_tdep): Declare.
	(arm_canonicalize_syscall): New function.
	(arm_all_but_pc_registers_record): New function.
	(arm_linux_syscall_record): New function.
	(arm_linux_init_abi): Add syscall recording constructs.
	* arm-tdep.c (thumb_record_ldm_stm_swi): Update thumb syscall decoding.
	(arm_record_coproc_data_proc): Update arm syscall decoding.
	* arm-tdep.h (struct gdbarch_tdep) <arm_swi_record>: Remove.
	<arm_syscall_record>: New field.
	* configure.tgt: Add linux-record.o to gdb_target_obs.

---
 gdb/arm-linux-tdep.c |  248 +++++++++++++++++++++++++++++++++++++++++++++++++-
 gdb/arm-tdep.c       |   50 ++++++----
 gdb/arm-tdep.h       |    4 +-
 gdb/configure.tgt    |    2 +-
 4 files changed, 281 insertions(+), 23 deletions(-)

diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index 7546d34..bf797ec 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -44,6 +44,9 @@
 #include "gdbthread.h"
 #include "symfile.h"
 
+#include "record-full.h"
+#include "linux-record.h"
+
 #include "cli/cli-utils.h"
 #include "stap-probe.h"
 #include "parser-defs.h"
@@ -1231,6 +1234,92 @@ arm_stap_parse_special_token (struct gdbarch *gdbarch,
   return 1;
 }
 
+/* ARM process record-replay constructs: syscall, signal etc.  */
+
+struct linux_record_tdep arm_linux_record_tdep;
+
+/* arm_canonicalize_syscall maps from the native arm Linux set
+   of syscall ids into a canonical set of syscall ids used by
+   process record.  */
+
+static enum gdb_syscall
+arm_canonicalize_syscall (int syscall)
+{
+  enum { sys_process_vm_writev = 377 };
+
+  if (syscall <= gdb_sys_sched_getaffinity)
+    return syscall;
+  else if (syscall >= 243 && syscall <= 247 )
+    return syscall + 2;
+  else if (syscall >= 248 && syscall <= 253 )
+    return syscall + 4;
+
+  return -1;
+}
+
+/* Record all registers but PC register for process-record.  */
+
+static int
+arm_all_but_pc_registers_record (struct regcache *regcache)
+{
+  int i;
+
+  for (i = 0; i < ARM_PC_REGNUM; i++)
+    {
+      if (record_full_arch_list_add_reg (regcache, ARM_A1_REGNUM + i))
+        return -1;
+    }
+
+  if (record_full_arch_list_add_reg (regcache, ARM_PS_REGNUM))
+    return -1;
+
+  return 0;
+}
+
+/* Handler for arm system call instruction recording.  */
+
+static int
+arm_linux_syscall_record (struct regcache *regcache, unsigned long svc_number)
+{
+  int ret = 0;
+  enum gdb_syscall syscall_gdb;
+
+  syscall_gdb = arm_canonicalize_syscall (svc_number);
+
+  if (syscall_gdb < 0)
+    {
+      printf_unfiltered (_("Process record and replay target doesn't "
+                           "support syscall number %s\n"),
+                           plongest (svc_number));
+      return -1;
+    }
+
+  if (syscall_gdb == gdb_sys_sigreturn
+      || syscall_gdb == gdb_sys_rt_sigreturn)
+   {
+     if (arm_all_but_pc_registers_record (regcache))
+       return -1;
+     return 0;
+   }
+
+  ret = record_linux_system_call (syscall_gdb, regcache,
+                                  &arm_linux_record_tdep);
+  if (ret != 0)
+    return ret;
+
+  /* Record the return value of the system call.  */
+  if (record_full_arch_list_add_reg (regcache, ARM_A1_REGNUM))
+    return -1;
+  /* Record LR.  */
+  if (record_full_arch_list_add_reg (regcache, ARM_LR_REGNUM))
+    return -1;
+  /* Record CPSR.  */
+  if (record_full_arch_list_add_reg (regcache, ARM_PS_REGNUM))
+    return -1;
+
+  return 0;
+}
+
 static void
 arm_linux_init_abi (struct gdbarch_info info,
 		    struct gdbarch *gdbarch)
@@ -1350,7 +1439,164 @@ arm_linux_init_abi (struct gdbarch_info info,
   set_gdbarch_get_syscall_number (gdbarch, arm_linux_get_syscall_number);
 
   /* Syscall record.  */
-  tdep->arm_swi_record = NULL;
+  tdep->arm_syscall_record = arm_linux_syscall_record;
+
+  /* Initialize the arm_linux_record_tdep.  */
+  /* These values are the size of the type that will be used in a system
+     call.  They are obtained from Linux Kernel source.  */
+  arm_linux_record_tdep.size_pointer
+    = gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size__old_kernel_stat = 32;
+  arm_linux_record_tdep.size_tms = 16;
+  arm_linux_record_tdep.size_loff_t = 8;
+  arm_linux_record_tdep.size_flock = 16;
+  arm_linux_record_tdep.size_oldold_utsname = 45;
+  arm_linux_record_tdep.size_ustat = 20;
+  arm_linux_record_tdep.size_old_sigaction = 140;
+  arm_linux_record_tdep.size_old_sigset_t = 128;
+  arm_linux_record_tdep.size_rlimit = 8;
+  arm_linux_record_tdep.size_rusage = 72;
+  arm_linux_record_tdep.size_timeval = 8;
+  arm_linux_record_tdep.size_timezone = 8;
+  arm_linux_record_tdep.size_old_gid_t = 2;
+  arm_linux_record_tdep.size_old_uid_t = 2;
+  arm_linux_record_tdep.size_fd_set = 128;
+  arm_linux_record_tdep.size_dirent = 268;
+  arm_linux_record_tdep.size_dirent64 = 276;
+  arm_linux_record_tdep.size_statfs = 64;
+  arm_linux_record_tdep.size_statfs64 = 84;
+  arm_linux_record_tdep.size_sockaddr = 16;
+  arm_linux_record_tdep.size_int
+    = gdbarch_int_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size_long
+    = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size_ulong
+    = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT;
+  arm_linux_record_tdep.size_msghdr = 28;
+  arm_linux_record_tdep.size_itimerval = 16;
+  arm_linux_record_tdep.size_stat = 88;
+  arm_linux_record_tdep.size_old_utsname = 325;
+  arm_linux_record_tdep.size_sysinfo = 64;
+  arm_linux_record_tdep.size_msqid_ds = 88;
+  arm_linux_record_tdep.size_shmid_ds = 84;
+  arm_linux_record_tdep.size_new_utsname = 390;
+  arm_linux_record_tdep.size_timex = 128;
+  arm_linux_record_tdep.size_mem_dqinfo = 24;
+  arm_linux_record_tdep.size_if_dqblk = 68;
+  arm_linux_record_tdep.size_fs_quota_stat = 68;
+  arm_linux_record_tdep.size_timespec = 8;
+  arm_linux_record_tdep.size_pollfd = 8;
+  arm_linux_record_tdep.size_NFS_FHSIZE = 32;
+  arm_linux_record_tdep.size_knfsd_fh = 132;
+  arm_linux_record_tdep.size_TASK_COMM_LEN = 16;
+  arm_linux_record_tdep.size_sigaction = 140;
+  arm_linux_record_tdep.size_sigset_t = 8;
+  arm_linux_record_tdep.size_siginfo_t = 128;
+  arm_linux_record_tdep.size_cap_user_data_t = 12;
+  arm_linux_record_tdep.size_stack_t = 12;
+  arm_linux_record_tdep.size_off_t = arm_linux_record_tdep.size_long;
+  arm_linux_record_tdep.size_stat64 = 96;
+  arm_linux_record_tdep.size_gid_t = 2;
+  arm_linux_record_tdep.size_uid_t = 2;
+  arm_linux_record_tdep.size_PAGE_SIZE = 4096;
+  arm_linux_record_tdep.size_flock64 = 24;
+  arm_linux_record_tdep.size_user_desc = 16;
+  arm_linux_record_tdep.size_io_event = 32;
+  arm_linux_record_tdep.size_iocb = 64;
+  arm_linux_record_tdep.size_epoll_event = 12;
+  arm_linux_record_tdep.size_itimerspec
+    = arm_linux_record_tdep.size_timespec * 2;
+  arm_linux_record_tdep.size_mq_attr = 32;
+  arm_linux_record_tdep.size_siginfo = 128;
+  arm_linux_record_tdep.size_termios = 36;
+  arm_linux_record_tdep.size_termios2 = 44;
+  arm_linux_record_tdep.size_pid_t = 4;
+  arm_linux_record_tdep.size_winsize = 8;
+  arm_linux_record_tdep.size_serial_struct = 60;
+  arm_linux_record_tdep.size_serial_icounter_struct = 80;
+  arm_linux_record_tdep.size_hayes_esp_config = 12;
+  arm_linux_record_tdep.size_size_t = 4;
+  arm_linux_record_tdep.size_iovec = 8;
+
+  /* These values are the second argument of system call "sys_ioctl".
+     They are obtained from Linux Kernel source.  */
+  arm_linux_record_tdep.ioctl_TCGETS = 0x5401;
+  arm_linux_record_tdep.ioctl_TCSETS = 0x5402;
+  arm_linux_record_tdep.ioctl_TCSETSW = 0x5403;
+  arm_linux_record_tdep.ioctl_TCSETSF = 0x5404;
+  arm_linux_record_tdep.ioctl_TCGETA = 0x5405;
+  arm_linux_record_tdep.ioctl_TCSETA = 0x5406;
+  arm_linux_record_tdep.ioctl_TCSETAW = 0x5407;
+  arm_linux_record_tdep.ioctl_TCSETAF = 0x5408;
+  arm_linux_record_tdep.ioctl_TCSBRK = 0x5409;
+  arm_linux_record_tdep.ioctl_TCXONC = 0x540a;
+  arm_linux_record_tdep.ioctl_TCFLSH = 0x540b;
+  arm_linux_record_tdep.ioctl_TIOCEXCL = 0x540c;
+  arm_linux_record_tdep.ioctl_TIOCNXCL = 0x540d;
+  arm_linux_record_tdep.ioctl_TIOCSCTTY = 0x540e;
+  arm_linux_record_tdep.ioctl_TIOCGPGRP = 0x540f;
+  arm_linux_record_tdep.ioctl_TIOCSPGRP = 0x5410;
+  arm_linux_record_tdep.ioctl_TIOCOUTQ = 0x5411;
+  arm_linux_record_tdep.ioctl_TIOCSTI = 0x5412;
+  arm_linux_record_tdep.ioctl_TIOCGWINSZ = 0x5413;
+  arm_linux_record_tdep.ioctl_TIOCSWINSZ = 0x5414;
+  arm_linux_record_tdep.ioctl_TIOCMGET = 0x5415;
+  arm_linux_record_tdep.ioctl_TIOCMBIS = 0x5416;
+  arm_linux_record_tdep.ioctl_TIOCMBIC = 0x5417;
+  arm_linux_record_tdep.ioctl_TIOCMSET = 0x5418;
+  arm_linux_record_tdep.ioctl_TIOCGSOFTCAR = 0x5419;
+  arm_linux_record_tdep.ioctl_TIOCSSOFTCAR = 0x541a;
+  arm_linux_record_tdep.ioctl_FIONREAD = 0x541b;
+  arm_linux_record_tdep.ioctl_TIOCINQ = arm_linux_record_tdep.ioctl_FIONREAD;
+  arm_linux_record_tdep.ioctl_TIOCLINUX = 0x541c;
+  arm_linux_record_tdep.ioctl_TIOCCONS = 0x541d;
+  arm_linux_record_tdep.ioctl_TIOCGSERIAL = 0x541e;
+  arm_linux_record_tdep.ioctl_TIOCSSERIAL = 0x541f;
+  arm_linux_record_tdep.ioctl_TIOCPKT = 0x5420;
+  arm_linux_record_tdep.ioctl_FIONBIO = 0x5421;
+  arm_linux_record_tdep.ioctl_TIOCNOTTY = 0x5422;
+  arm_linux_record_tdep.ioctl_TIOCSETD = 0x5423;
+  arm_linux_record_tdep.ioctl_TIOCGETD = 0x5424;
+  arm_linux_record_tdep.ioctl_TCSBRKP = 0x5425;
+  arm_linux_record_tdep.ioctl_TIOCTTYGSTRUCT = 0x5426;
+  arm_linux_record_tdep.ioctl_TIOCSBRK = 0x5427;
+  arm_linux_record_tdep.ioctl_TIOCCBRK = 0x5428;
+  arm_linux_record_tdep.ioctl_TIOCGSID = 0x5429;
+  arm_linux_record_tdep.ioctl_TCGETS2 = 0x802c542a;
+  arm_linux_record_tdep.ioctl_TCSETS2 = 0x402c542b;
+  arm_linux_record_tdep.ioctl_TCSETSW2 = 0x402c542c;
+  arm_linux_record_tdep.ioctl_TCSETSF2 = 0x402c542d;
+  arm_linux_record_tdep.ioctl_TIOCGPTN = 0x80045430;
+  arm_linux_record_tdep.ioctl_TIOCSPTLCK = 0x40045431;
+  arm_linux_record_tdep.ioctl_FIONCLEX = 0x5450;
+  arm_linux_record_tdep.ioctl_FIOCLEX = 0x5451;
+  arm_linux_record_tdep.ioctl_FIOASYNC = 0x5452;
+  arm_linux_record_tdep.ioctl_TIOCSERCONFIG = 0x5453;
+  arm_linux_record_tdep.ioctl_TIOCSERGWILD = 0x5454;
+  arm_linux_record_tdep.ioctl_TIOCSERSWILD = 0x5455;
+  arm_linux_record_tdep.ioctl_TIOCGLCKTRMIOS = 0x5456;
+  arm_linux_record_tdep.ioctl_TIOCSLCKTRMIOS = 0x5457;
+  arm_linux_record_tdep.ioctl_TIOCSERGSTRUCT = 0x5458;
+  arm_linux_record_tdep.ioctl_TIOCSERGETLSR = 0x5459;
+  arm_linux_record_tdep.ioctl_TIOCSERGETMULTI = 0x545a;
+  arm_linux_record_tdep.ioctl_TIOCSERSETMULTI = 0x545b;
+  arm_linux_record_tdep.ioctl_TIOCMIWAIT = 0x545c;
+  arm_linux_record_tdep.ioctl_TIOCGICOUNT = 0x545d;
+  arm_linux_record_tdep.ioctl_TIOCGHAYESESP = 0x545e;
+  arm_linux_record_tdep.ioctl_TIOCSHAYESESP = 0x545f;
+  arm_linux_record_tdep.ioctl_FIOQSIZE = 0x5460;
+
+  /* These values are the second argument of system call "sys_fcntl"
+     and "sys_fcntl64".  They are obtained from Linux Kernel source.  */
+  arm_linux_record_tdep.fcntl_F_GETLK = 5;
+  arm_linux_record_tdep.fcntl_F_GETLK64 = 12;
+  arm_linux_record_tdep.fcntl_F_SETLK64 = 13;
+  arm_linux_record_tdep.fcntl_F_SETLKW64 = 14;
+
+  arm_linux_record_tdep.arg1 = ARM_A1_REGNUM + 1;
+  arm_linux_record_tdep.arg2 = ARM_A1_REGNUM + 2;
+  arm_linux_record_tdep.arg3 = ARM_A1_REGNUM + 3;
+  arm_linux_record_tdep.arg4 = ARM_A1_REGNUM + 3;
 }
 
 /* Provide a prototype to silence -Wmissing-prototypes.  */
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index bcd76b2..57669d6 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -11941,27 +11941,38 @@ arm_record_coproc_data_proc (insn_decode_record *arm_insn_r)
   struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch);
   struct regcache *reg_cache = arm_insn_r->regcache;
   uint32_t ret = 0; /* function return value: -1:record failure ;  0:success  */
-
-  /* Handle SWI insn; system call would be handled over here.  */
+  ULONGEST u_regval = 0;
 
   arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27);
+
+  /* Handle arm SWI/SVC system call instructions.  */
   if (15 == arm_insn_r->opcode)
-  {
-    /* Handle arm syscall insn.  */
-    if (tdep->arm_swi_record != NULL)
-      {
-        ret = tdep->arm_swi_record(reg_cache);
-      }
-    else
-      {
-        printf_unfiltered (_("no syscall record support\n"));
-        ret = -1;
-      }
-  }
+    {
+      if (tdep->arm_syscall_record != NULL)
+        {
+          ULONGEST svc_operand, svc_number;
+
+          svc_operand = (0x00ffffff & arm_insn_r->arm_insn);
+
+          if (svc_operand)  /* OABI.  */
+            svc_number = svc_operand - 0x900000;
+          else /* EABI.  */
+            regcache_raw_read_unsigned (reg_cache, 7, &svc_number);
+
+          ret = tdep->arm_syscall_record (reg_cache, svc_number);
+        }
+      else
+        {
+          printf_unfiltered (_("no syscall record support\n"));
+          ret = -1;
+        }
+    }
+  else
+    {
+      arm_record_unsupported_insn (arm_insn_r);
+      ret = -1;
+    }
 
-  printf_unfiltered (_("Process record does not support instruction "
-                        "0x%0x at address %s.\n"),arm_insn_r->arm_insn,
-                        paddress (arm_insn_r->gdbarch, arm_insn_r->this_addr));
   return ret;
 }
 
@@ -12366,9 +12377,10 @@ thumb_record_ldm_stm_swi (insn_decode_record *thumb_insn_r)
   else if (0x1F == opcode1)
     {
         /* Handle arm syscall insn.  */
-        if (tdep->arm_swi_record != NULL)
+        if (tdep->arm_syscall_record != NULL)
           {
-            ret = tdep->arm_swi_record(reg_cache);
+            regcache_raw_read_unsigned (reg_cache, 7, &u_regval);
+            ret = tdep->arm_syscall_record (reg_cache, u_regval);
           }
         else
           {
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index a1a2be5..b584a43 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -205,8 +205,8 @@ struct gdbarch_tdep
      instruction.  */
   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 
-   /* Parse swi insn args, sycall record.  */
-  int (*arm_swi_record) (struct regcache *regcache);
+   /* syscall record.  */
+  int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number);
 };
 
 /* Structures used for displaced stepping.  */
diff --git a/gdb/configure.tgt b/gdb/configure.tgt
index ea0faf1..5410f72 100644
--- a/gdb/configure.tgt
+++ b/gdb/configure.tgt
@@ -89,7 +89,7 @@ arm*-wince-pe | arm*-*-mingw32ce*)
 arm*-*-linux*)
 	# Target: ARM based machine running GNU/Linux
 	gdb_target_obs="arm-tdep.o arm-linux-tdep.o glibc-tdep.o \
-			solib-svr4.o symfile-mem.o linux-tdep.o"
+			solib-svr4.o symfile-mem.o linux-tdep.o linux-record.o"
 	build_gdbserver=yes
 	;;
 arm*-*-netbsd* | arm*-*-knetbsd*-gnu)
-- 
1.7.9.5

Re: [PATCH v2 6/7] Updates configure.tgt and enables gdb.reverse testsuite

[Omair Javaid]

On 01/05/2014 07:27 PM, Yao Qi wrote:
> Hi,
> We should mention change in proc supports_reverse too.
> 
> On 01/04/2014 03:15 AM, Omair Javaid wrote:
>> 	* lib/gdb.exp (supports_process_record): Return true for arm*-linux*.
> 
> 	(supports_reverse): Likewise.
> 

Patch updated after incorporating suggestions:

gdb/testsuite:

2014-01-09  Omair Javaid  <omair.javaid@linaro.org>

	* lib/gdb.exp (supports_process_record): Return true for arm*-linux*.
	(supports_reverse): Likewise.
---
 gdb/testsuite/lib/gdb.exp |    6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/gdb/testsuite/lib/gdb.exp b/gdb/testsuite/lib/gdb.exp
index bde4e48..047aefb 100644
--- a/gdb/testsuite/lib/gdb.exp
+++ b/gdb/testsuite/lib/gdb.exp
@@ -1774,7 +1774,8 @@ proc supports_process_record {} {
 	return [target_info gdb,use_precord]
     }
 
-    if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"] } {
+    if { [istarget "arm*-*-linux*"] || [istarget "x86_64-*-linux*"]
+         || [istarget "i\[34567\]86-*-linux*"] } {
 	return 1
     }
 
@@ -1789,7 +1790,8 @@ proc supports_reverse {} {
 	return [target_info gdb,can_reverse]
     }
 
-    if { [istarget "x86_64-*-linux*"] || [istarget "i\[34567\]86-*-linux*"] } {
+    if { [istarget "arm*-*-linux*"] || [istarget "x86_64-*-linux*"]
+         || [istarget "i\[34567\]86-*-linux*"] } {
 	return 1
     }
 
-- 
1.7.9.5

Re: [PATCH v2 1/7] Fix for memory record corruption due to 64bit addresses

[Pedro Alves]

On 01/09/2014 10:35 AM, Omair Javaid wrote:
> On 01/07/2014 12:50 AM, Pedro Alves wrote:
>> On 01/03/2014 07:15 PM, Omair Javaid wrote:
>>> This patch changes record memory address type to unsigned 32bit integers.
>>> On targets where CORE_ADDR configures to become a unsigned 64bit value the
>>> arm process record code fails resulting in various testsuite failures.

...

> gdb:
> 
> 2014-01-03  Omair Javaid  <omair.javaid@linaro.org>
> 
> 	* arm-tdep.c (struct arm_mem_r) <addr>: Change type to uint32_t.

OK.

-- 
Pedro Alves

Re: [PATCH v2 5/7] Adds support for thumb32 instructions recording

[Pedro Alves]

On 01/09/2014 10:33 AM, Omair Javaid wrote:
> +enum arm_record_result {

'{' goes on the next line.  Otherwise OK.  Please push.

Thanks,
-- 
Pedro Alves

Re: [PATCH v2 6/7] Updates configure.tgt and enables gdb.reverse testsuite

[Pedro Alves]

On 01/09/2014 10:59 AM, Omair Javaid wrote:
> 
> On 01/05/2014 07:27 PM, Yao Qi wrote:
>> Hi,
>> We should mention change in proc supports_reverse too.
>>
>> On 01/04/2014 03:15 AM, Omair Javaid wrote:
>>> 	* lib/gdb.exp (supports_process_record): Return true for arm*-linux*.
>>
>> 	(supports_reverse): Likewise.
>>
> 
> Patch updated after incorporating suggestions:
> 
> gdb/testsuite:
> 
> 2014-01-09  Omair Javaid  <omair.javaid@linaro.org>
> 
> 	* lib/gdb.exp (supports_process_record): Return true for arm*-linux*.
> 	(supports_reverse): Likewise.

OK.

-- 
Pedro Alves

Re: [PATCH v2 7/7] Adds a NEWS entry for arm record/replay improvements

[Pedro Alves]

On 01/03/2014 07:15 PM, Omair Javaid wrote:

> --- a/gdb/NEWS
> +++ b/gdb/NEWS
> @@ -3,6 +3,10 @@
>  
>  *** Changes since GDB 7.6
>  
> +* Improved support of process record-replay and reverse debugging on
> +  arm*-linux* targets.  Support for thumb32 and syscall instructions
> +  recording has been added.

Note that this will need to be moved to the "Changes since 7.7"
section.

-- 
Pedro Alves

Re: [PATCH v2 5/7] Adds support for thumb32 instructions recording

[Omair Javaid]

I don't have committ rights for push. Kindly add me to committers list.

Thanks!

On 9 January 2014 16:23, Pedro Alves <palves@redhat.com> wrote:
> On 01/09/2014 10:33 AM, Omair Javaid wrote:
>> +enum arm_record_result {
>
> '{' goes on the next line.  Otherwise OK.  Please push.
>
> Thanks,
> --
> Pedro Alves
>

Re: [PATCH v2 4/7] Adds support for recording system call instructions

[Pedro Alves]

On 01/09/2014 10:49 AM, Omair Javaid wrote:

> 2014-01-09  Omair Javaid  <omair.javaid@linaro.org>
> ...
> 	* configure.tgt: Add linux-record.o to gdb_target_obs.

Should mention which target got that:

	* configure.tgt (arm*-*-linux*): Add linux-record.o to
	gdb_target_obs.


> +  if (syscall <= gdb_sys_sched_getaffinity)
> +    return syscall;
> +  else if (syscall >= 243 && syscall <= 247 )
> +    return syscall + 2;
> +  else if (syscall >= 248 && syscall <= 253 )

Spurious spaces before ).

Otherwise OK, please push.

Thanks,
-- 
Pedro Alves

Re: [PATCH v2 5/7] Adds support for thumb32 instructions recording

[Will Newton]

On 9 January 2014 11:34, Omair Javaid <omair.javaid@linaro.org> wrote:

Hi Omair,

> I don't have committ rights for push. Kindly add me to committers list.
>
> Thanks!
>
> On 9 January 2014 16:23, Pedro Alves <palves@redhat.com> wrote:
>> On 01/09/2014 10:33 AM, Omair Javaid wrote:
>>> +enum arm_record_result {
>>
>> '{' goes on the next line.  Otherwise OK.  Please push.

I have applied these patches on your behalf. I made the small changes
suggested on list and tweaked the commit messages slightly.

I'd like to recommend Omair be given commit privileges for future
patches if the maintainers agree.

Thanks,

-- 
Will Newton
Toolchain Working Group, Linaro

Re: [PATCH v2 5/7] Adds support for thumb32 instructions recording

[Tom Tromey]

Will> I'd like to recommend Omair be given commit privileges for future
Will> patches if the maintainers agree.

The rule is just if you have an assignment and have submitted one good
patch, then you can get write-after-approval access.  I'll send email
about the details.

Once you have your account it is customary to write a patch to
MAINTAINERS, adding yourself to the write-after-approval section; then
post the patch (w/ ChangeLog) as an FYI, then check it in.

Tom

[PATCH 1/1] Documentation for MPX.

[Walfred Tedeschi]

Hello Eli and Pedro,

This should complement the MPX registers check-in.

Thanks a lot for your review on the last patch series.
Here I have tried to incorporate feedback from you both.


Bestregards,
-Fred


2013-1X-XX  Walfred Tedeschi  <walfred.tedeschi@intel.com>

	* NEWS:  Add section for Intel(R) Architecture Instructions
	Extesions mentioning MPX.
doc/
	* gdb.texinfo (i386 Features): Add MPX feature registers.
	(x86 Specific featuresx86 Architecture-specific Issues): Adds
	a subsubsection for MPX and describes the display of the
	boundary registers.


---
 gdb/NEWS            |    2 ++
 gdb/doc/gdb.texinfo |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/gdb/NEWS b/gdb/NEWS
index 9fc3638..fdb33d4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5558,3 +5558,5 @@ GDB now handles cross debugging.  If you are remotely debugging between
 two different machines, type ``./configure host -target=targ''.
 Host is the machine where GDB will run; targ is the machine
 where the program that you are debugging will run.
+
+ *  GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index d854f46..6041b4a 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -21363,6 +21363,42 @@ be returned in a register.
 @kindex show struct-convention
 Show the current setting of the convention to return @code{struct}s
 from functions.
+
+@subsubsection Intel(R) Memory Protection Extensions (MPX).
+
+@item bnd0raw..bnd3raw and bnd0...bnd3 registers display.
+Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
+@footnote{Capital letters are used to distinguish between architecture
+registers and pseudo registers.  A set of pseudo registers for the bound
+registers is created to simplify the display.} through @samp{BND3}.  Bound
+registers store a pair of 64-bit values which are the lower bound and upper
+bound.  Bounds are effective addresses or memory locations.  The upper bounds
+are architecturally represented in 1's complement form.  A bound having lower
+bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
+access to the entire address space.
+
+Architectuere registers @samp{BND0} through @samp{BND3} are
+represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.
+Pseudo registers @samp{bnd0} through @samp{bnd3} display the upper bound
+performing the complement of one operation on the upper bound value, i.e.@
+when upper bound in @samp{bnd0raw} is 0 in the @value{GDBN} @samp{bnd0} it will
+be @code{0xfff...}.  In this sense it can also be noted that the upper bounds are
+inclusive.
+
+As an example, assume that the register BND0 holds bounds for a pointer having
+access allowed for the range between 0x32 and 0x71.  The values present on
+bnd0raw and bnd registers are presented as follows:
+
+@smallexample
+	bnd0raw = {0x32, 0xffffffff8e}
+	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64
+@end smallexample
+
+This way the architecture value can be accessed via bnd0raw...bnd3raw.  Any change
+on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart.  When displaying
+bnd0..bnd3 register with Python support also the size of the bounds is displayed.
+
+
 @end table
 
 @node Alpha
@@ -43138,6 +43174,16 @@ describe the upper 128 bits of @sc{ymm} registers:
 @samp{ymm0h} through @samp{ymm15h} for amd64
 @end itemize
 
+The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
+Memory Protection Extension (MPX).  It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64.
+@item
+@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64.
+@end itemize
+
 The @samp{org.gnu.gdb.i386.linux} feature is optional.  It should
 describe a single register, @samp{orig_eax}.
 
-- 
1.7.6.5

[PATCH 1/1] Documentation for MPX.

[Walfred Tedeschi]

Hello Eli and Pedro,

This should complement the MPX registers check-in in terms of documentation.
Here I have tried to incorporate feedback from you both.


Thanks a lot for your review on the former patch series.

Best regards,
-Fred


2013-1X-XX  Walfred Tedeschi  <walfred.tedeschi@intel.com>

	* NEWS:  Add section for Intel(R) Architecture Instructions
	Extesions mentioning MPX.
doc/
	* gdb.texinfo (i386 Features): Add MPX feature registers.
	(x86 Specific featuresx86 Architecture-specific Issues): Adds
	a subsubsection for MPX and describes the display of the
	boundary registers.


---
 gdb/NEWS            |    2 ++
 gdb/doc/gdb.texinfo |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/gdb/NEWS b/gdb/NEWS
index 9fc3638..fdb33d4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5558,3 +5558,5 @@ GDB now handles cross debugging.  If you are remotely debugging between
 two different machines, type ``./configure host -target=targ''.
 Host is the machine where GDB will run; targ is the machine
 where the program that you are debugging will run.
+
+ *  GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index d854f46..6041b4a 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -21363,6 +21363,42 @@ be returned in a register.
 @kindex show struct-convention
 Show the current setting of the convention to return @code{struct}s
 from functions.
+
+@subsubsection Intel(R) Memory Protection Extensions (MPX).
+
+@item bnd0raw..bnd3raw and bnd0...bnd3 registers display.
+Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
+@footnote{Capital letters are used to distinguish between architecture
+registers and pseudo registers.  A set of pseudo registers for the bound
+registers is created to simplify the display.} through @samp{BND3}.  Bound
+registers store a pair of 64-bit values which are the lower bound and upper
+bound.  Bounds are effective addresses or memory locations.  The upper bounds
+are architecturally represented in 1's complement form.  A bound having lower
+bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
+access to the entire address space.
+
+Architectuere registers @samp{BND0} through @samp{BND3} are
+represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.
+Pseudo registers @samp{bnd0} through @samp{bnd3} display the upper bound
+performing the complement of one operation on the upper bound value, i.e.@
+when upper bound in @samp{bnd0raw} is 0 in the @value{GDBN} @samp{bnd0} it will
+be @code{0xfff...}.  In this sense it can also be noted that the upper bounds are
+inclusive.
+
+As an example, assume that the register BND0 holds bounds for a pointer having
+access allowed for the range between 0x32 and 0x71.  The values present on
+bnd0raw and bnd registers are presented as follows:
+
+@smallexample
+	bnd0raw = {0x32, 0xffffffff8e}
+	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64
+@end smallexample
+
+This way the architecture value can be accessed via bnd0raw...bnd3raw.  Any change
+on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart.  When displaying
+bnd0..bnd3 register with Python support also the size of the bounds is displayed.
+
+
 @end table
 
 @node Alpha
@@ -43138,6 +43174,16 @@ describe the upper 128 bits of @sc{ymm} registers:
 @samp{ymm0h} through @samp{ymm15h} for amd64
 @end itemize
 
+The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
+Memory Protection Extension (MPX).  It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64.
+@item
+@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64.
+@end itemize
+
 The @samp{org.gnu.gdb.i386.linux} feature is optional.  It should
 describe a single register, @samp{orig_eax}.
 
-- 
1.7.6.5

[PATCH 1/1] Documentation for MPX.

[y]

From: Walfred Tedeschi <walfred.tedeschi@intel.com>

Hello Eli and Pedro,

This should complement the MPX registers check-in.

Thanks a lot for your review on the last patch series.
Here I have tried to incorporate feedback from you both.


Bestregards,
-Fred


2013-1X-XX  Walfred Tedeschi  <walfred.tedeschi@intel.com>

	* NEWS:  Add section for Intel(R) Architecture Instructions
	Extesions mentioning MPX.
doc/
	* gdb.texinfo (i386 Features): Add MPX feature registers.
	(x86 Specific featuresx86 Architecture-specific Issues): Adds
	a subsubsection for MPX and describes the display of the
	boundary registers.


---
 gdb/NEWS            |    2 ++
 gdb/doc/gdb.texinfo |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/gdb/NEWS b/gdb/NEWS
index 9fc3638..fdb33d4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5558,3 +5558,5 @@ GDB now handles cross debugging.  If you are remotely debugging between
 two different machines, type ``./configure host -target=targ''.
 Host is the machine where GDB will run; targ is the machine
 where the program that you are debugging will run.
+
+ *  GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index d854f46..6041b4a 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -21363,6 +21363,42 @@ be returned in a register.
 @kindex show struct-convention
 Show the current setting of the convention to return @code{struct}s
 from functions.
+
+@subsubsection Intel(R) Memory Protection Extensions (MPX).
+
+@item bnd0raw..bnd3raw and bnd0...bnd3 registers display.
+Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
+@footnote{Capital letters are used to distinguish between architecture
+registers and pseudo registers.  A set of pseudo registers for the bound
+registers is created to simplify the display.} through @samp{BND3}.  Bound
+registers store a pair of 64-bit values which are the lower bound and upper
+bound.  Bounds are effective addresses or memory locations.  The upper bounds
+are architecturally represented in 1's complement form.  A bound having lower
+bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
+access to the entire address space.
+
+Architectuere registers @samp{BND0} through @samp{BND3} are
+represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.
+Pseudo registers @samp{bnd0} through @samp{bnd3} display the upper bound
+performing the complement of one operation on the upper bound value, i.e.@
+when upper bound in @samp{bnd0raw} is 0 in the @value{GDBN} @samp{bnd0} it will
+be @code{0xfff...}.  In this sense it can also be noted that the upper bounds are
+inclusive.
+
+As an example, assume that the register BND0 holds bounds for a pointer having
+access allowed for the range between 0x32 and 0x71.  The values present on
+bnd0raw and bnd registers are presented as follows:
+
+@smallexample
+	bnd0raw = {0x32, 0xffffffff8e}
+	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64
+@end smallexample
+
+This way the architecture value can be accessed via bnd0raw...bnd3raw.  Any change
+on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart.  When displaying
+bnd0..bnd3 register with Python support also the size of the bounds is displayed.
+
+
 @end table
 
 @node Alpha
@@ -43138,6 +43174,16 @@ describe the upper 128 bits of @sc{ymm} registers:
 @samp{ymm0h} through @samp{ymm15h} for amd64
 @end itemize
 
+The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
+Memory Protection Extension (MPX).  It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64.
+@item
+@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64.
+@end itemize
+
 The @samp{org.gnu.gdb.i386.linux} feature is optional.  It should
 describe a single register, @samp{orig_eax}.
 
-- 
1.7.6.5

[PATCH 1/1] Documentation for MPX.

[y]

From: Walfred Tedeschi <walfred.tedeschi@intel.com>

Hello Eli and Pedro,

This should complement the MPX registers check-in in terms of documentation.
Here I have tried to incorporate feedback from you both.


Thanks a lot for your review on the former patch series.

Best regards,
-Fred


2013-1X-XX  Walfred Tedeschi  <walfred.tedeschi@intel.com>

	* NEWS:  Add section for Intel(R) Architecture Instructions
	Extesions mentioning MPX.
doc/
	* gdb.texinfo (i386 Features): Add MPX feature registers.
	(x86 Specific featuresx86 Architecture-specific Issues): Adds
	a subsubsection for MPX and describes the display of the
	boundary registers.


---
 gdb/NEWS            |    2 ++
 gdb/doc/gdb.texinfo |   46 ++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/gdb/NEWS b/gdb/NEWS
index 9fc3638..fdb33d4 100644
--- a/gdb/NEWS
+++ b/gdb/NEWS
@@ -5558,3 +5558,5 @@ GDB now handles cross debugging.  If you are remotely debugging between
 two different machines, type ``./configure host -target=targ''.
 Host is the machine where GDB will run; targ is the machine
 where the program that you are debugging will run.
+
+ *  GDB now supports access to Intel(R) MPX registers on GNU/Linux.
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index d854f46..6041b4a 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -21363,6 +21363,42 @@ be returned in a register.
 @kindex show struct-convention
 Show the current setting of the convention to return @code{struct}s
 from functions.
+
+@subsubsection Intel(R) Memory Protection Extensions (MPX).
+
+@item bnd0raw..bnd3raw and bnd0...bnd3 registers display.
+Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
+@footnote{Capital letters are used to distinguish between architecture
+registers and pseudo registers.  A set of pseudo registers for the bound
+registers is created to simplify the display.} through @samp{BND3}.  Bound
+registers store a pair of 64-bit values which are the lower bound and upper
+bound.  Bounds are effective addresses or memory locations.  The upper bounds
+are architecturally represented in 1's complement form.  A bound having lower
+bound = 0, and upper bound = 0 (1's complement of all bits set) will allow
+access to the entire address space.
+
+Architectuere registers @samp{BND0} through @samp{BND3} are
+represented in @value{GDBN} as @samp{bnd0raw} through @samp{bnd3raw}.
+Pseudo registers @samp{bnd0} through @samp{bnd3} display the upper bound
+performing the complement of one operation on the upper bound value, i.e.@
+when upper bound in @samp{bnd0raw} is 0 in the @value{GDBN} @samp{bnd0} it will
+be @code{0xfff...}.  In this sense it can also be noted that the upper bounds are
+inclusive.
+
+As an example, assume that the register BND0 holds bounds for a pointer having
+access allowed for the range between 0x32 and 0x71.  The values present on
+bnd0raw and bnd registers are presented as follows:
+
+@smallexample
+	bnd0raw = {0x32, 0xffffffff8e}
+	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64
+@end smallexample
+
+This way the architecture value can be accessed via bnd0raw...bnd3raw.  Any change
+on bnd0..bnd3 or bnd0raw...bnd3raw is reflect on its counterpart.  When displaying
+bnd0..bnd3 register with Python support also the size of the bounds is displayed.
+
+
 @end table
 
 @node Alpha
@@ -43138,6 +43174,16 @@ describe the upper 128 bits of @sc{ymm} registers:
 @samp{ymm0h} through @samp{ymm15h} for amd64
 @end itemize
 
+The @samp{org.gnu.gdb.i386.mpx} is an optional feature representing Intel(R)
+Memory Protection Extension (MPX).  It should describe the following registers:
+
+@itemize @minus
+@item
+@samp{bnd0raw} through @samp{bnd3raw} for i386 and amd64.
+@item
+@samp{bndcfgu} and @samp{bndstatus} for i386 and amd64.
+@end itemize
+
 The @samp{org.gnu.gdb.i386.linux} feature is optional.  It should
 describe a single register, @samp{orig_eax}.
 
-- 
1.7.6.5