From: Eli Zaretskii <eliz@gnu.org>
To: Luis Machado <luis.machado@arm.com>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH v3 17/17] [gdb/docs] sme: Document SME registers and features
Date: Fri, 19 May 2023 14:20:32 +0300 [thread overview]
Message-ID: <83lehktvnj.fsf@gnu.org> (raw)
In-Reply-To: <20230519102508.14020-18-luis.machado@arm.com> (message from Luis Machado via Gdb-patches on Fri, 19 May 2023 11:25:08 +0100)
> Date: Fri, 19 May 2023 11:25:08 +0100
> From: Luis Machado via Gdb-patches <gdb-patches@sourceware.org>
>
> Updates since v2:
>
> - More adjustments based on reviews.
> - Fixed incorrect number of tile pseudo-registers.
> - Fixed naming of tile slice pseudo-registers.
> - More detail about SME and how gdb implements it.
> - Attempted to clarify the text a bit more.
>
> Updates since v1:
>
> - Made SME text more thorough.
> - Adjusted text based on upstream reviews.
> - Fixed documentation errors (missing itemization for SME registers).
>
> Provide documentation for the SME feature and other information that
> should be useful for users that need to debug a SME-capable target.
Thanks. This part of the patch has numerous inconsistencies in
letter-case and markup of register names, see below.
> +The @code{za} register state can be either active or inactive, if it is not in
> +use.
"@code{ZA}", upper-case.
> +@var{svl}: The streaming vector length, in bytes. It defines the size of each
> +dimension of the 2-dimensional square @code{za} matrix. The total size of
> +@code{za} is therefore @var{svl} by @var{svl}.
Same here.
> +The @code{za} register is a 2-dimensional square @var{svl} by @var{svl}
And here.
> +If the user wants to index the @code{za} register as a matrix, it is possible
> +to reference @code{za} as @code{za[@var{i}][@var{j}]}, where @var{i} is the
> +row number and @var{j} is the column number.
And here.
> +The @var{svg} register always contains the streaming vector granule
^^^^^^^^^
"@code{SVG}"
> +(@var{svg}) for the current thread. From @var{svg} we can easily derive
Same here.
> +The @code{svcr} pseudo-register (streaming vector control register) is a status
Same here: "@code{SVCR}"
> +If the @sc{za} bit is 1, it means the @code{za} register is being used and
^^^^^^^^^
"@code{ZA}", upper-case.
> +For convenience and simplicity, if the @sc{za} bit is 0, the @code{za}
> +register and all of its pseudo-registers will read as zero.
Same here.
> +If @var{svl} changes during the execution of a program, then the @code{za}
> +register size and the bits in the @code{svcr} pseudo-register will be updated
> +to reflect it.
And here.
> +It is possible for users to change @var{svl} during the execution of a
> +program by modifying the @var{svg} register value.
^^^^^^^^^
"@code{SVG}"
> +Whenever the @var{svg} register is modified with a new value, the
Same here.
> +@item The @code{za} register will have a new size and its state will be
"@code{ZA}"
> +@sc{sm} bit was 0 prior to modifying the @var{svg} register, there will be no
^^^^^^^^^
"@code{SVG}"
> +The possible values for the @var{svg} register are 2, 4, 8, 16, 32. These
Same here.
> +The minimum size of the @code{za} register is 16 x 16 (256) bytes, and the
"@code{ZA}"
> +maximum size is 256 x 256 (65536) bytes. In streaming mode, with bit @sc{sm}
> +set, the size of the @code{za} register is the size of all the SVE @code{z}
Same here, and also "@code{Z}", upper-case.
> +The @code{za} register can also be accessed using tiles and tile slices.
"@code{ZA}"
> +Tile pseudo-registers are square, 2-dimensional sub-arrays of elements within
> +the @code{za} register.
Same here.
> +There is a total of 31 @code{za} tile pseudo-registers. They are
> +@code{za0b}, @code{za0h} through @code{za1h}, @code{zas0} through @code{zas3},
> +@code{zad0} through @code{zad7} and @code{zaq0} through @code{zaq15}.
Same here: all the register names should be in upper-case.
> +Tile slice pseudo-registers are vectors of horizontally or vertically
> +contiguous elements within the @code{za} register.
"@code{ZA}"
> +The tile slice pseudo-registers have the following naming pattern:
> +@code{za<@var{tile number}><@var{direction}><@var{qualifier}>
> +<@var{slice number}>}.
Same here.
> +When listing all the available registers, users will see the
> +currently-available @code{za} pseudo-registers. Pseudo-registers that don't
And here.
> +account the @code{svcr} pseudo-register bits nor the @code{za} register
And here.
> +contents. @xref{Calling}
^^
Two spaces there.
> +The @url{https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#the-za-lazy-saving-scheme,
> +lazy saving scheme} involving the @code{tpidr2} register is not yet supported
> +by @value{GDBN}, though the @code{tpidr2} register is known and supported
> +by @value{GDBN}.
Please up-case the names of the registers here.
> +@value{GDBN} showing incorrect values for the @code{za} register and
"@code{ZA}"
> +The @samp{org.gnu.gdb.aarch64.sme} feature is optional. If present,
> +it should contain registers @samp{za}, @samp{svg} and @samp{svcr}.
Since you use @code, not @samp, for register markup elsewhere, please
use @code here as well. Also, please up-case the names of the
registers.
> +@samp{za} is a register represented by a vector of @var{svl}x@var{svl}
^^^^^^^^^
"@code{ZA}"
> +@samp{svg} is a 64-bit register containing the value of @var{svg}. @xref{svg}.
^^^^^^^^^^
"@code{SVG}"
> +@samp{svcr} is a 64-bit status pseudo-register with two valid bits. Bit 0
^^^^^^^^^^^
"@code{SVCR}"
> +Bit 1 (@sc{za}) shows whether the @code{za} register state is active (in use) or
^^^^^^^^^
"@code{ZA}"
> +The rest of the unused bits of the @samp{svcr} pseudo-register is undefined
^^^^^^^^^^^
"@code{SVCR}"
Reviewed-By: Eli Zaretskii <eliz@gnu.org>
next prev parent reply other threads:[~2023-05-19 11:20 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 10:24 [PATCH v2 00/17] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-05-19 10:24 ` [PATCH v2 01/17] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Luis Machado
2023-05-19 10:24 ` [PATCH v2 02/17] [gdb/aarch64] refactor: Rename SVE-specific files Luis Machado
2023-05-19 10:24 ` [PATCH v2 03/17] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers Luis Machado
2023-05-19 10:24 ` [PATCH v2 04/17] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target Luis Machado
2023-05-19 10:24 ` [PATCH v2 05/17] [gdb/aarch64] sme: Enable SME registers and pseudo-registers Luis Machado
2023-05-19 10:24 ` [PATCH v2 06/17] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically Luis Machado
2023-05-19 10:24 ` [PATCH v2 07/17] [gdbserver/aarch64] sme: Add support for SME Luis Machado
2023-05-19 10:24 ` [PATCH v2 08/17] [gdb/aarch64] sve: Fix signal frame z/v register restore Luis Machado
2023-05-19 10:25 ` [PATCH v2 09/17] [gdb/aarch64] sme: Signal frame support Luis Machado
2023-05-19 10:25 ` [PATCH v2 10/17] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes Luis Machado
2023-05-19 10:25 ` [PATCH v2 11/17] [gdb/aarch64] sme: Support TPIDR2 signal frame context Luis Machado
2023-05-19 10:25 ` [PATCH v2 12/17] [binutils/aarch64] sme: Core file support Luis Machado
2023-05-19 10:25 ` [PATCH v2 13/17] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Luis Machado
2023-05-19 10:25 ` [PATCH v2 14/17] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Luis Machado
2023-05-19 10:25 ` [PATCH v2 15/17] [gdb/aarch64] sme: Core file support for Linux Luis Machado
2023-05-19 10:25 ` [PATCH v2 16/17] [gdb/testsuite] sme: Add SVE/SME testcases Luis Machado
2023-05-19 10:25 ` [PATCH v3 17/17] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-05-19 11:20 ` Eli Zaretskii [this message]
2023-06-30 12:10 ` Luis Machado
-- strict thread matches above, loose matches on Subject: below --
2023-04-11 4:26 [PATCH " Luis Machado
2023-04-17 17:19 ` [PATCH,v3 " Luis Machado
2023-04-22 9:21 ` Eli Zaretskii
2023-04-26 15:00 ` Luis Machado
2023-04-26 16:11 ` Eli Zaretskii
2023-04-27 8:35 ` Luis Machado
2023-04-27 9:10 ` Eli Zaretskii
2023-04-27 9:12 ` Luis Machado
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