Re: [PATCH] gdb/riscv: Add target description support

[Eli Zaretskii <eliz@gnu.org>]

> Date: Wed, 21 Nov 2018 11:23:35 +0000
> From: Andrew Burgess <andrew.burgess@embecosm.com>
> Cc: gdb-patches@sourceware.org, Palmer Dabbelt <palmer@sifive.com>,
> 	John Baldwin <jhb@freebsd.org>
> 
> Eli,
> 
> I believe I still need a doc review before I can merge this patch.
> Could I ask you to take a look please.

Sorry, I thought I already did.  See below.

> +The @samp{org.gnu.gdb.riscv.fpu} feature is optional.  If present it
                                                                    ^
Please insert a comma where shown.

> +should contain registers @samp{f0} through @samp{f31}, @samp{fflags},
> +@samp{frm}, and @samp{fcsr}.  As with the cpu feature either the
                                                        ^
And here.

> +The @samp{org.gnu.gdb.riscv.virtual} feature is optional.  If present
                                                                        ^
And here.

> +it should contain registers that are not backed by real registers on
> +the target but are instead virtual, where the register value is
             ^
And here.

> +derived from other target state.  In many ways these are like GDBs
                                                                 ^^^^
@value{GDBN}s

> +The @samp{org.gnu.gdb.riscv.csr} feature is optional.  If present it
                                                                    ^
Need a comma there.

OK with these nits fixed.

Thanks.