From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24168 invoked by alias); 22 Apr 2016 14:58:10 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 24154 invoked by uid 89); 22 Apr 2016 14:58:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf0-f172.google.com Received: from mail-pf0-f172.google.com (HELO mail-pf0-f172.google.com) (209.85.192.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 22 Apr 2016 14:58:00 +0000 Received: by mail-pf0-f172.google.com with SMTP id 184so42346718pff.0 for ; Fri, 22 Apr 2016 07:57:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:references:date:in-reply-to :message-id:user-agent:mime-version:content-transfer-encoding; bh=SoCxUAHsGtLppkE3UKd8ANIINpLr9GvrkO6mbbfFHkU=; b=DRbNKq6jf9bv4Ij250DHhSRH6sw1Pxvok5PbCyM5zQb/eOU3kR7pWYQobS6mB1kPD5 ctd2mXDQqGVQfthRVZ5vnkg3R71yWUqPgha9BuwsoknWkF1SSU5COF94suET3pIEq/AE PLh6m0XaqdN7wZhU/8QPUwEl/7kHrTcxdSgT8yIaVunuxROnPFXK91AI3DwqEHR4ixLR +xcbnuJJrA+pbKgj48Qunig0iup/ALSihR/qnQGetro5pBio5bH++093/hcjcHEK+40t wMVXKKcZy6hmjtDUNCw7O8LK6LMJ6et9s5KIue13rlPaXYzDnJva7C8U5RIf5bUApCGy hJxw== X-Gm-Message-State: AOPr4FV42f9o3f5Zd0t7oBiIqR/aHnvoXO/28CRjBMYc3ng/0ReeSKpYXA5PoUlSPEIFFg== X-Received: by 10.98.24.78 with SMTP id 75mr29505666pfy.52.1461337078075; Fri, 22 Apr 2016 07:57:58 -0700 (PDT) Received: from E107787-LIN (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id j62sm9126366pfb.15.2016.04.22.07.57.55 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 22 Apr 2016 07:57:57 -0700 (PDT) From: Yao Qi To: Pedro Alves Cc: Yao Qi , gdb-patches@sourceware.org Subject: Re: [PATCH] [ARM] Clear reserved bits in CPSR References: <1461320654-22274-1-git-send-email-yao.qi@linaro.org> <571A22B8.8050002@redhat.com> Date: Fri, 22 Apr 2016 14:58:00 -0000 In-Reply-To: <571A22B8.8050002@redhat.com> (Pedro Alves's message of "Fri, 22 Apr 2016 14:10:16 +0100") Message-ID: <86pothhesg.fsf@gmail.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/24.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2016-04/txt/msg00529.txt.bz2 Pedro Alves writes: > No comments on the ARM specifics, but I think it's clearer to write > this as: > > regs[ARM_CPSR_GREGNUM] &=3D 0xff0fffff; Fixed. Patch is pushed in. --=20 Yao (=E9=BD=90=E5=B0=A7) =46rom 3539aa13fbcadd930b0b6d8a97f9f125f02a73dc Mon Sep 17 00:00:00 2001 From: Yao Qi Date: Fri, 22 Apr 2016 15:53:05 +0100 Subject: [PATCH] [ARM] Clear reserved bits in CPSR Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not zero if the arm program runs on aarch64-linux. AArch64 tracer gets PSTATE from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE. I think kernel should clear these bits when it is read through ptrace, but the fix in user space is still needed. This patch fixes these two fails, -FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on= insn 0:vldr d7, [r11, #-12] -FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on= insn 0:vldr d7, [r7] gdb: 2016-04-22 Yao Qi * aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR bits 20 to 23. gdb/gdbserver: 2016-04-22 Yao Qi * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20 to 23. diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 8b6a7da..e9321db 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2016-04-22 Yao Qi + + * aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR + bits 20 to 23. + 2016-04-22 Joel Brobecker =20 * MAINTAINER: Remove myself as AIX Maintainer. diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c index 568dfa6..72bf644 100644 --- a/gdb/aarch32-linux-nat.c +++ b/gdb/aarch32-linux-nat.c @@ -37,7 +37,11 @@ aarch32_gp_regcache_supply (struct regcache *regcache, u= int32_t *regs, regcache_raw_supply (regcache, regno, ®s[regno]); =20 if (arm_apcs_32) - regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + { + /* Clear reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] &=3D 0xff0fffff; + regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM= ]); + } else regcache_raw_supply (regcache, ARM_PS_REGNUM, ®s[ARM_PC_REGNUM]); =20 diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog index e0ed616..a7ffbf8 100644 --- a/gdb/gdbserver/ChangeLog +++ b/gdb/gdbserver/ChangeLog @@ -1,5 +1,10 @@ 2016-04-22 Yao Qi =20 + * linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20 + to 23. + +2016-04-22 Yao Qi + * linux-low.c (lwp_signal_can_be_delivered): Don't deliver signal when stepping over breakpoint with software single step. diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch3= 2-low.c index 0c4b140..e6971d5 100644 --- a/gdb/gdbserver/linux-aarch32-low.c +++ b/gdb/gdbserver/linux-aarch32-low.c @@ -77,6 +77,7 @@ arm_store_gregset (struct regcache *regcache, const void = *buf) int i; char zerobuf[8]; const uint32_t *regs =3D (const uint32_t *) buf; + uint32_t cpsr =3D regs[ARM_CPSR_GREGNUM]; =20 memset (zerobuf, 0, 8); for (i =3D ARM_A1_REGNUM; i <=3D ARM_PC_REGNUM; i++) @@ -85,7 +86,9 @@ arm_store_gregset (struct regcache *regcache, const void = *buf) for (; i < ARM_PS_REGNUM; i++) supply_register (regcache, i, zerobuf); =20 - supply_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + /* Clear reserved bits bit 20 to bit 23. */ + cpsr &=3D 0xff0fffff; + supply_register (regcache, ARM_PS_REGNUM, &cpsr); } =20 /* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */