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[143.159.223.185]) by smtp.gmail.com with ESMTPSA id l35-20020a05600c1d2300b004161af729f4sm15630047wms.31.2024.04.15.01.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Apr 2024 01:56:33 -0700 (PDT) From: Andrew Burgess To: Bernd Edlinger , "gdb-patches@sourceware.org" Subject: Re: [PATCH] sim: riscv: Fix confusion with c.jal vs. c.addiw In-Reply-To: References: Date: Mon, 15 Apr 2024 09:56:33 +0100 Message-ID: <877cgzhum6.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Bernd Edlinger writes: > There was apparently a confusion which cpu model uses > compressed JAL and which ADDIW. Fixed that in execute_c, > case MATCH_C_JAL | MATCH_C_ADDIW. > > Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer > instructions") Thanks for splitting this off. This looks good. Approved-By: Andrew Burgess Thanks, Andrew > --- > sim/riscv/sim-main.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index adff99921c6..9fd2cc70657 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -1016,9 +1016,9 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); > break; > case MATCH_C_JAL | MATCH_C_ADDIW: > - /* JAL and ADDIW have the same mask but are only available on RV64 or > - RV32 respectively. */ > - if (RISCV_XLEN (cpu) == 64) > + /* JAL and ADDIW have the same mask but are only available on RV32 or > + RV64 respectively. */ > + if (RISCV_XLEN (cpu) == 32) > { > imm = EXTRACT_CJTYPE_IMM (iw); > TRACE_INSN (cpu, "c.jal %" PRIxTW, > @@ -1027,7 +1027,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > pc = riscv_cpu->pc + imm; > TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); > } > - else if (RISCV_XLEN (cpu) == 32) > + else if (RISCV_XLEN (cpu) == 64) > { > imm = EXTRACT_CITYPE_IMM (iw); > TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW, > -- > 2.39.2