* [PATCH V4 2/3] sim: eBPF simulator
2020-07-10 12:25 [PATCH V4 0/3] eBPF support Jose E. Marchesi
2020-07-10 12:25 ` [PATCH V4 1/3] gdb: support for eBPF Jose E. Marchesi
@ 2020-07-10 12:25 ` Jose E. Marchesi
2020-07-12 8:25 ` Andrew Burgess
2020-07-10 12:25 ` [PATCH V4 3/3] sim: generated files for the " Jose E. Marchesi
2 siblings, 1 reply; 10+ messages in thread
From: Jose E. Marchesi @ 2020-07-10 12:25 UTC (permalink / raw)
To: gdb-patches
This patch introduces the basics of an instruction-simulator for eBPF.
The simulator is based on CGEN.
sim/ChangeLog:
2020-07-10 Jose E. Marchesi <jose.marchesi@oracle.com>
David Faust <david.faust@oracle.com>
* configure.tgt (sim_arch): Add entry for bpf-*-*.
* configure: Regenerate.
* MAINTAINERS: Add maintainer for the BPF simulator.
* bpf/Makefile.in: New file.
* bpf/bpf-helpers.c: Likewise.
* bpf/bpf-helpers.def: Likewise.
* bpf/bpf-helpers.h: Likewise.
* bpf/bpf-sim.h: Likewise.
* bpf/bpf.c: Likewise.
* bpf/config.in: Likewise.
* bpf/configure.ac: Likewise.
* bpf/decode.h: Likewise.
* bpf/eng.h: Likewise.
* bpf/mloop.in: Likewise.
* bpf/sim-if.c: Likewise.
* bpf/sim-main.h: Likewise.
* bpf/traps.c: Likewise.
* bpf/configure: Generate.
* bpf/aclocal.m4: Likewise.
sim/testsuite/ChangeLog:
2020-07-10 David Faust <david.faust@oracle.com>
Jose E. Marchesi <jose.marchesi@oracle.com>
* configure: Regenerate.
* sim/bpf/allinsn.exp: New file.
* sim/bpf/alu.s: Likewise.
* sim/bpf/alu32.s: Likewise.
* sim/bpf/endbe.s: Likewise.
* sim/bpf/endle.s: Likewise.
* sim/bpf/jmp.s: Likewise.
* sim/bpf/jmp32.s: Likewise.
* sim/bpf/ldabs.s: Likewise.
* sim/bpf/mem.s: Likewise.
* sim/bpf/mov.s: Likewise.
* sim/bpf/testutils.inc: Likewise.
* sim/bpf/xadd.s: Likewise.
---
sim/ChangeLog | 23 +
sim/MAINTAINERS | 1 +
sim/bpf/Makefile.in | 205 +
sim/bpf/aclocal.m4 | 119 +
sim/bpf/bpf-helpers.c | 175 +
sim/bpf/bpf-helpers.def | 194 +
sim/bpf/bpf-helpers.h | 31 +
sim/bpf/bpf-sim.h | 31 +
sim/bpf/bpf.c | 327 +
sim/bpf/config.in | 248 +
sim/bpf/configure | 15942 ++++++++++++++++++++++++++
sim/bpf/configure.ac | 13 +
sim/bpf/decode.h | 37 +
sim/bpf/eng.h | 24 +
sim/bpf/mloop.in | 165 +
sim/bpf/sim-if.c | 216 +
sim/bpf/sim-main.h | 51 +
sim/bpf/traps.c | 33 +
sim/configure | 8 +
sim/configure.tgt | 3 +
sim/testsuite/ChangeLog | 17 +
sim/testsuite/configure | 9 +-
sim/testsuite/sim/bpf/allinsn.exp | 26 +
sim/testsuite/sim/bpf/alu.s | 109 +
sim/testsuite/sim/bpf/alu32.s | 99 +
sim/testsuite/sim/bpf/endbe.s | 46 +
sim/testsuite/sim/bpf/endle.s | 43 +
sim/testsuite/sim/bpf/jmp.s | 120 +
sim/testsuite/sim/bpf/jmp32.s | 120 +
sim/testsuite/sim/bpf/ldabs.s | 87 +
sim/testsuite/sim/bpf/mem.s | 56 +
sim/testsuite/sim/bpf/mov.s | 54 +
sim/testsuite/sim/bpf/testutils.inc | 38 +
sim/testsuite/sim/bpf/xadd.s | 44 +
34 files changed, 18711 insertions(+), 3 deletions(-)
create mode 100644 sim/bpf/Makefile.in
create mode 100644 sim/bpf/aclocal.m4
create mode 100644 sim/bpf/bpf-helpers.c
create mode 100644 sim/bpf/bpf-helpers.def
create mode 100644 sim/bpf/bpf-helpers.h
create mode 100644 sim/bpf/bpf-sim.h
create mode 100644 sim/bpf/bpf.c
create mode 100644 sim/bpf/config.in
create mode 100755 sim/bpf/configure
create mode 100644 sim/bpf/configure.ac
create mode 100644 sim/bpf/decode.h
create mode 100644 sim/bpf/eng.h
create mode 100644 sim/bpf/mloop.in
create mode 100644 sim/bpf/sim-if.c
create mode 100644 sim/bpf/sim-main.h
create mode 100644 sim/bpf/traps.c
create mode 100644 sim/testsuite/sim/bpf/allinsn.exp
create mode 100644 sim/testsuite/sim/bpf/alu.s
create mode 100644 sim/testsuite/sim/bpf/alu32.s
create mode 100644 sim/testsuite/sim/bpf/endbe.s
create mode 100644 sim/testsuite/sim/bpf/endle.s
create mode 100644 sim/testsuite/sim/bpf/jmp.s
create mode 100644 sim/testsuite/sim/bpf/jmp32.s
create mode 100644 sim/testsuite/sim/bpf/ldabs.s
create mode 100644 sim/testsuite/sim/bpf/mem.s
create mode 100644 sim/testsuite/sim/bpf/mov.s
create mode 100644 sim/testsuite/sim/bpf/testutils.inc
create mode 100644 sim/testsuite/sim/bpf/xadd.s
diff --git a/sim/MAINTAINERS b/sim/MAINTAINERS
index 4ca67cfd1d..7dcd88422c 100644
--- a/sim/MAINTAINERS
+++ b/sim/MAINTAINERS
@@ -17,6 +17,7 @@ aarch64 Nick Clifton <nickc@redhat.com>
aarch64 Jim Wilson <wilson@tuliptree.org>
arm Nick Clifton <nickc@redhat.com>
bfin Mike Frysinger <vapier@gentoo.org>
+bpf Jose E. Marchesi <jose.marchesi@oracle.com>
cr16 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
frv Dave Brolley <brolley@redhat.com>
ft32 James Bowman <james.bowman@ftdichip.com>
diff --git a/sim/bpf/Makefile.in b/sim/bpf/Makefile.in
new file mode 100644
index 0000000000..b12bb6a7d5
--- /dev/null
+++ b/sim/bpf/Makefile.in
@@ -0,0 +1,205 @@
+# Makefile template for configure for the eBPF simulator
+# Copyright (C) 2019 Free Software Foundation, Inc.
+#
+# This file is part of GDB, the GNU debugger.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+## COMMON_PRE_CONFIG_FRAG
+
+CGEN_STD_OBJS = cgen-run.o cgen-scache.o cgen-trace.o cgen-utils.o
+BPF_GEN_OBJS = arch.o cpu.o \
+ decode-le.o decode-be.o \
+ sem-le.o sem-be.o \
+ mloop-le.o mloop-be.o
+BPF_HAND_OBJS = bpf.o sim-if.o traps.o bpf-helpers.o
+
+SIM_OBJS = \
+ $(SIM_NEW_COMMON_OBJS) \
+ $(CGEN_STD_OBJS) \
+ $(BPF_GEN_OBJS) \
+ $(BPF_HAND_OBJS)
+
+SIM_EXTRA_DEPS = \
+ $(CGEN_INCLUDE_DEPS) \
+ arch.h \
+ bpf-sim.h \
+ $(srcdir)/../../opcodes/bpf-desc.h \
+ $(srcdir)/../../opcodes/bpf-opc.h
+
+SIM_EXTRA_CLEAN = bpf-clean
+
+## COMMON_POST_CONFIG_FRAG
+
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAIN = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+# BPF headers
+
+BPF_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ $(SIM_EXTRA_DEPS) \
+ cpu.h cpuall.h \
+ decode-le.h decode-be.h \
+ defs-le.h defs-be.h \
+ eng-le.h eng-be.h \
+ config.h
+
+# Dependencies for binaries from CGEN generated source
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+cpu.o: cpu.c $(BPF_INCLUDE_DEPS)
+decode-le.o: decode-le.c $(BPF_INCLUDE_DEPS)
+decode-be.o: decode-be.c $(BPF_INCLUDE_DEPS)
+# XXX sem-switch.o: sem-switch.c $(BPF_INCLUDE_DEPS)
+# XXX model.o: model.c $(BPF_INCLUDE_DEPS)
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h eng.h
+ $(COMPILE) $<
+ $(POSTCOMPILE)
+
+traps.o: traps.c $(SIM_MAIN_DEPS) eng.h
+ $(COMPILE) $<
+ $(POSTCOMPILE)
+
+mloop-le.o: mloop-le.c $(BPF_INCLUDE_DEPS)
+ $(CC) -c mloop-le.c $(ALL_CFLAGS) -DWANT_ISA_EBPFLE
+mloop-be.o: mloop-be.c $(BPF_INCLUDE_DEPS)
+ $(CC) -c mloop-be.c $(ALL_CFLAGS) -DWANT_ISA_EBPFBE
+
+decode-le.o: decode-le.c $(BPF_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/decode-le.c $(ALL_CFLAGS) -DWANT_ISA_EBPFLE
+decode-be.o: decode-be.c $(BPF_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/decode-be.c $(ALL_CFLAGS) -DWANT_ISA_EBPFBE
+
+sem-le.o: sem-le.c $(BPF_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/sem-le.c $(ALL_CFLAGS) -DWANT_ISA_EBPFLE
+sem-be.o: sem-be.c $(BPF_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/sem-be.c $(ALL_CFLAGS) -DWANT_ISA_EBPFBE
+
+arch = bpf
+
+CGEN_COMMON_DEPS = \
+ $(CGEN_READ_SCM) \
+ $(srcdir)/../../cpu/bpf.cpu \
+ $(srcdir)/../../cpu/bpf.opc \
+ Makefile
+
+stamp-arch: $(CGEN_COMMON_DEPS) $(CGEN_ARCH_SCM)
+ $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) \
+ mach=bpf cpu=bpfbf \
+ archfile=$(srcdir)/../../cpu/bpf.cpu \
+ FLAGS="with-scache"
+ touch $@
+$(srcdir)/arch.h $(srcdir)/arch.c $(srcdir)/cpuall.h: $(CGEN_MAINT) stamp-arch
+ @true
+
+stamp-cpu: $(CGEN_COMMON_DEPS) $(CGEN_CPU_SCM)
+ $(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
+ isa=ebpfle,ebpfbe cpu=bpfbf mach=bpf \
+ archfile=$(srcdir)/../../cpu/bpf.cpu \
+ FLAGS="with-multiple-isa with-scache"
+ rm -f $(srcdir)/model.c
+ touch $@
+$(srcdir)/cpu.h $(srcdir)/cpu.c $(srcdir)/model.c: $(CGEN_MAINT) stamp-cpu
+ @true
+
+# We need to generate a group of files per ISA.
+# For eBPF little-endian:
+# defs-le.h
+# sem-le.c, decode-le.c, decode-le.h
+# $(objdir)/mloop-le.c $(objdir)/eng-le.h
+# For eBPF big-endian:
+# defs-be.h
+# sem-be.c, decode-be.c, decode-be.h
+# $(objdir)/mloop-be.c $(objdir)/eng-le.h
+#
+# The rules below take care of that.
+
+stamp-defs-le: $(CGEN_COMMON_DEPS) $(CGEN_CPU_SCM)
+ $(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
+ isa=ebpfle cpu=bpfbf mach=bpf \
+ archfile=$(srcdir)/../../cpu/bpf.cpu \
+ FLAGS="with-scache" \
+ SUFFIX="-le"
+ touch $@
+$(srcdir)/defs-le.h: $(CGEN_MAINT) stamp-defs-le
+ @true
+
+
+stamp-defs-be: $(CGEN_COMMON_DEPS) $(CGEN_CPU_SCM)
+ $(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
+ isa=ebpfbe cpu=bpfbf mach=bpf \
+ archfile=$(srcdir)/../../cpu/bpf.cpu \
+ FLAGS="with-scache" \
+ SUFFIX="-be"
+ touch $@
+$(srcdir)/defs-be.h: $(CGEN_MAINT) stamp-defs-be
+ @true
+
+stamp-decode-le: $(CGEN_COMMON_DEPS) $(CGEN_CPU_SCM) $(GEN_DECODE_SCM)
+ $(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
+ isa=ebpfle cpu=bpfbf mach=bpf \
+ archfile=$(srcdir)/../../cpu/bpf.cpu \
+ FLAGS="with-scache" \
+ SUFFIX="-le" \
+ EXTRAFILES="$(CGEN_CPU_SEM)"
+ touch $@
+$(srcdir)/sem-le.c $(srcdir)/decode-le.c $(srcdir)/decode-le.h: \
+ $(CGEN_MAINT) stamp-decode-le
+ @true
+
+
+stamp-decode-be: $(CGEN_COMMON_DEPS) $(CGEN_CPU_SCM) $(GEN_DECODE_SCM)
+ $(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
+ isa=ebpfbe cpu=bpfbf mach=bpf \
+ archfile=$(srcdir)/../../cpu/bpf.cpu \
+ FLAGS="with-scache" \
+ SUFFIX="-be" \
+ EXTRAFILES="$(CGEN_CPU_SEM)"
+ touch $@
+$(srcdir)/sem-be.c $(srcdir)/decode-be.c $(srcdir)/decode-be.h: \
+ $(CGEN_MAINT) stamp-decode-be
+ @true
+
+# Note the following files are generated in objdir, not srcdir.
+
+stamp-mloop: stamp-mloop-le stamp-mloop-be
+
+stamp-mloop-le: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+ -mono -scache -prefix bpfbf_ebpfle -cpu bpfbf \
+ -infile $(srcdir)/mloop.in
+ $(SHELL) $(srcroot)/move-if-change eng.hin eng-le.h
+ $(SHELL) $(srcroot)/move-if-change mloop.cin mloop-le.c
+ touch $@
+mloop-le.c eng-le.h: stamp-mloop-le
+ @true
+
+stamp-mloop-be: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+ $(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+ -mono -scache -prefix bpfbf_ebpfbe -cpu bpfbf \
+ -infile $(srcdir)/mloop.in
+ $(SHELL) $(srcroot)/move-if-change eng.hin eng-be.h
+ $(SHELL) $(srcroot)/move-if-change mloop.cin mloop-be.c
+ touch $@
+mloop-be.c eng-be.h: stamp-mloop-be
+ @true
+
+.PHONY = bpf-clean
+
+bpf-clean:
+ rm -f stamp-arch stamp-cpu stamp-decode stamp-defs stamp-mloop
diff --git a/sim/bpf/aclocal.m4 b/sim/bpf/aclocal.m4
new file mode 100644
index 0000000000..e9f11c775c
--- /dev/null
+++ b/sim/bpf/aclocal.m4
@@ -0,0 +1,119 @@
+# generated automatically by aclocal 1.15.1 -*- Autoconf -*-
+
+# Copyright (C) 1996-2017 Free Software Foundation, Inc.
+
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
+# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+# PARTICULAR PURPOSE.
+
+m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])])
+# AM_CONDITIONAL -*- Autoconf -*-
+
+# Copyright (C) 1997-2017 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_CONDITIONAL(NAME, SHELL-CONDITION)
+# -------------------------------------
+# Define a conditional.
+AC_DEFUN([AM_CONDITIONAL],
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+if $2; then
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+AC_CONFIG_COMMANDS_PRE(
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+ AC_MSG_ERROR([[conditional "$1" was never defined.
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+
+# Copyright (C) 2003-2017 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
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+rmdir .tst 2>/dev/null
+AC_SUBST([am__leading_dot])])
+
+# Add --enable-maintainer-mode option to configure. -*- Autoconf -*-
+# From Jim Meyering
+
+# Copyright (C) 1996-2017 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# AM_MAINTAINER_MODE([DEFAULT-MODE])
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+# Control maintainer-specific portions of Makefiles.
+# Default is to disable them, unless 'enable' is passed literally.
+# For symmetry, 'disable' may be passed as well. Anyway, the user
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+AC_DEFUN([AM_MAINTAINER_MODE],
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+AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles])
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+ AC_ARG_ENABLE([maintainer-mode],
+ [AS_HELP_STRING([--]am_maintainer_other[-maintainer-mode],
+ am_maintainer_other[ make rules and dependencies not useful
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+ AM_CONDITIONAL([MAINTAINER_MODE], [test $USE_MAINTAINER_MODE = yes])
+ MAINT=$MAINTAINER_MODE_TRUE
+ AC_SUBST([MAINT])dnl
+]
+)
+
+# Copyright (C) 2006-2017 Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# _AM_SUBST_NOTMAKE(VARIABLE)
+# ---------------------------
+# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in.
+# This macro is traced by Automake.
+AC_DEFUN([_AM_SUBST_NOTMAKE])
+
+# AM_SUBST_NOTMAKE(VARIABLE)
+# --------------------------
+# Public sister of _AM_SUBST_NOTMAKE.
+AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)])
+
diff --git a/sim/bpf/bpf-helpers.c b/sim/bpf/bpf-helpers.c
new file mode 100644
index 0000000000..8d979e0fe0
--- /dev/null
+++ b/sim/bpf/bpf-helpers.c
@@ -0,0 +1,175 @@
+/* Emulation of eBPF helpers.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* BPF programs rely on the existence of several helper functions,
+ which are provided by the kernel. This simulator provides an
+ implementation of the helpers, which can be customized by the
+ user. */
+
+#define WANT_CPU_BPFBF
+#define WANT_CPU bpfbf
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+#include "cpu.h"
+
+/* bpf_trace_printk is a printk-like facility for debugging.
+
+ In the kernel, it appends a line to the Linux's tracing debugging
+ interface.
+
+ In this simulator, it uses the simulator's tracing interface
+ instead.
+
+ The format tags recognized by this helper are:
+ %d, %i, %u, %x, %ld, %li, %lu, %lx, %lld, %lli, %llu, %llx,
+ %p, %s
+
+ A maximum of three tags are supported.
+
+ This helper returns the number of bytes written, or a negative
+ value in case of failure. */
+
+int
+bpf_trace_printk (SIM_CPU *current_cpu)
+{
+ va_list ap;
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ DI fmt_address;
+ uint32_t size, tags_processed;
+ size_t i, bytes_written = 0;
+
+ /* The first argument is the format string, which is passed as a
+ pointer in %r1. */
+ fmt_address = GET_H_GPR (1);
+
+ /* The second argument is the length of the format string, as an
+ unsigned 32-bit number in %r2. */
+ size = GET_H_GPR (2);
+
+ /* Read the format string from the memory pointed by %r2, printing
+ out the stuff as we go. There is a maximum of three format tags
+ supported, which are read from %r3, %r4 and %r5 respectively. */
+ for (i = 0, tags_processed = 0; i < size;)
+ {
+ QI c = GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
+ fmt_address + i);
+
+ switch (c)
+ {
+ case '%':
+ /* Check we are not exceeding the limit of three format
+ tags. */
+ if (tags_processed > 2)
+ return -1; /* XXX look for kernel error code. */
+
+ /* Depending on the kind of tag, extract the value from the
+ proper argument. */
+ if (i++ >= size)
+ return -1; /* XXX look for kernel error code. */
+
+ UDI value = GET_H_GPR (3 + tags_processed);
+
+ switch ((GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
+ fmt_address + i)))
+ {
+ case 'd':
+ trace_printf (sd, current_cpu, "%d", value);
+ break;
+ case 'i':
+ trace_printf (sd, current_cpu, "%i", value);
+ break;
+ case 'u':
+ trace_printf (sd, current_cpu, "%u", value);
+ break;
+ case 'x':
+ trace_printf (sd, current_cpu, "%x", value);
+ break;
+ case 'l':
+ {
+ if (i++ >= size)
+ return -1;
+ switch (GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
+ fmt_address + i))
+ {
+ case 'd':
+ trace_printf (sd, current_cpu, "%ld", value);
+ break;
+ case 'i':
+ trace_printf (sd, current_cpu, "%li", value);
+ break;
+ case 'u':
+ trace_printf (sd, current_cpu, "%lu", value);
+ break;
+ case 'x':
+ trace_printf (sd, current_cpu, "%lx", value);
+ break;
+ case 'l':
+ {
+ if (i++ >= size)
+ return -1;
+ switch (GETMEMUQI (current_cpu, CPU_PC_GET (current_cpu),
+ fmt_address + i)) {
+ case 'd':
+ trace_printf (sd, current_cpu, "%lld", value);
+ break;
+ case 'i':
+ trace_printf (sd, current_cpu, "%lli", value);
+ break;
+ case 'u':
+ trace_printf (sd, current_cpu, "%llu", value);
+ break;
+ case 'x':
+ trace_printf (sd, current_cpu, "%llx", value);
+ break;
+ default:
+ assert (0);
+ break;
+ }
+ break;
+ }
+ default:
+ assert (0);
+ break;
+ }
+ break;
+ }
+ default:
+ /* XXX completeme */
+ assert (0);
+ break;
+ }
+
+ tags_processed++;
+ i++;
+ break;
+ case '\0':
+ i = size;
+ break;
+ default:
+ trace_printf (sd, current_cpu, "%c", c);
+ bytes_written++;
+ i++;
+ break;
+ }
+ }
+
+ return bytes_written;
+}
diff --git a/sim/bpf/bpf-helpers.def b/sim/bpf/bpf-helpers.def
new file mode 100644
index 0000000000..6106ac794a
--- /dev/null
+++ b/sim/bpf/bpf-helpers.def
@@ -0,0 +1,194 @@
+/* BPF helpers database.
+ Copyright (C) 2019-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulator.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+/* This file contains the definition of the helpers that are available
+ to BPF programs.
+
+ The primary source for information on kernel helpers is the
+ linux/include/uapi/linux/bpf.h file in the Linux source tree.
+ Please keep this database in sync.
+
+ The first column is the first kernel version featuring the helper
+ function. This should be an enumerate from bpf_kernel_version,
+ defined in bpf-opts.h. Note that the backend assumes that helpers
+ never get deprecated in the kernel. If that eventually happens,
+ then we will need to use a bitmask here instead of an enumerate.
+
+ The second column is the constant-name for the helper.
+ The third column is the program-name of the helper.
+
+ The fourth column is a list of names describing the types of the
+ values returned and accepted by the helper, in one of these forms:
+
+ TYPES (type1, type2, ..., 0)
+ VTYPES (type1, type2, ..., 0)
+
+ VTYPES should be used should the helper accept a variable number of
+ arguments, TYPES otherwise. The valid type names are:
+
+ `vt' for void.
+ `it' for signed int.
+ `ut' for unsigned int.
+ `pt' for void*.
+ `cpt' for const void*.
+ `st' for short int.
+ `ust' for unsigned short int.
+ `cst' for const char *.
+ `ullt' for unsigned long long.
+ `llt' for long long.
+ `u32t' for uint32.
+ `u64t' for uint64.
+
+ In types descriptions, the firt entry corresponds to the value
+ returned by the helper. Subsequent names correspond to the helper
+ arguments. Finally, a 0 should close the list.
+
+ VERY IMPORTANT: the helper entries should be listed in the same
+ order than in the definition of __BPF_FUNC_MAPPER in
+ linux/include/uapi/linux/bpf.h! */
+
+DEF_HELPER (LINUX_V4_0, MAP_LOOKUP_ELEM, map_lookup_elem, TYPES (pt, pt, pt, 0))
+DEF_HELPER (LINUX_V4_0, MAP_UPDATE_ELEM, map_update_elem, TYPES (it, pt, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V4_0, MAP_DELETE_ELEM, map_delete_elem, TYPES (it, pt, pt, 0))
+DEF_HELPER (LINUX_V4_1, PROBE_READ, probe_read, TYPES (it, pt, ut, cpt, 0))
+DEF_HELPER (LINUX_V4_1, KTIME_GET_NS, ktime_get_ns, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_1, TRACE_PRINTK, trace_printk, VTYPES (it, cst, it, 0))
+DEF_HELPER (LINUX_V4_1, GET_PRANDOM_U32, get_prandom_u32, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_1, GET_SMP_PROCESSOR_ID, get_smp_processor_id, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_1, SKB_STORE_BYTES, skb_store_bytes, TYPES (it, pt, it, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_1, L3_CSUM_REPLACE, l3_csum_replace, TYPES (it, pt, it, it ,it ,it, 0))
+DEF_HELPER (LINUX_V4_1, L4_CSUM_REPLACE, l4_csum_replace, TYPES (it, pt, it, it, it, it, 0))
+DEF_HELPER (LINUX_V4_2, TAIL_CALL, tail_call, TYPES (vt, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_2, CLONE_REDIRECT, clone_redirect, TYPES (it, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_2, GET_CURRENT_PID_TGID, get_current_pid_tgid, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_2, GET_CURRENT_UID_GID, get_current_uid_gid, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_2, GET_CURRENT_COMM, get_current_comm, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_3, GET_CGROUP_CLASSID, get_cgroup_classid, TYPES (it, pt, 0))
+DEF_HELPER (LINUX_V4_3, SKB_VLAN_PUSH, skb_vlan_push, TYPES (it, pt, st, ust, 0))
+DEF_HELPER (LINUX_V4_3, SKB_VLAN_POP, skb_vlan_pop, TYPES (it, pt, 0))
+DEF_HELPER (LINUX_V4_3, SKB_GET_TUNNEL_KEY, skb_get_tunnel_key, TYPES (it, pt, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_3, SKB_SET_TUNNEL_KEY, skb_set_tunnel_key, TYPES (it, pt, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_3, PERF_EVENT_READ, perf_event_read, TYPES (ullt, pt, ullt, 0))
+DEF_HELPER (LINUX_V4_4, REDIRECT, redirect, TYPES (it, it, it, 0))
+DEF_HELPER (LINUX_V4_4, GET_ROUTE_REALM, get_route_realm, TYPES (ut, pt, 0))
+DEF_HELPER (LINUX_V4_4, PERF_EVENT_OUTPUT, perf_event_output, \
+ TYPES (it, pt, pt, ullt, pt, it, 0))
+DEF_HELPER (LINUX_V4_5, SKB_LOAD_BYTES, skb_load_bytes, TYPES (it, pt, it, pt, it, 0))
+DEF_HELPER (LINUX_V4_6, GET_STACKID, get_stackid, TYPES (it, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_6, CSUM_DIFF, csum_diff, TYPES (it, pt, it, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_6, SKB_GET_TUNNEL_OPT, skb_get_tunnel_opt, TYPES (it, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_6, SKB_SET_TUNNEL_OPT, skb_set_tunnel_opt, TYPES (it, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_8, SKB_CHANGE_PROTO, skb_change_proto, TYPES (it, pt, st, u64t, 0))
+DEF_HELPER (LINUX_V4_8, SKB_CHANGE_TYPE, skb_change_type, TYPES (it, pt, u32t, 0))
+DEF_HELPER (LINUX_V4_8, SKB_UNDER_CGROUP, skb_under_cgroup, TYPES (it, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_8, GET_HASH_RECALC, get_hash_recalc, TYPES (ut, pt, 0))
+DEF_HELPER (LINUX_V4_8, GET_CURRENT_TASK, get_current_task, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_8, PROBE_WRITE_USER, probe_write_user, TYPES (it, pt, cpt, ut, 0))
+DEF_HELPER (LINUX_V4_9, CURRENT_TASK_UNDER_CGROUP, current_task_under_cgroup, \
+ TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_9, SKB_CHANGE_TAIL, skb_change_tail, TYPES (it, pt, ut, u64t, 0))
+DEF_HELPER (LINUX_V4_9, SKB_PULL_DATA, skb_pull_data, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_9, CSUM_UPDATE, csum_update, TYPES (llt, pt, u32t, 0))
+DEF_HELPER (LINUX_V4_9, SET_HASH_INVALID, set_hash_invalid, TYPES (vt, pt, 0))
+DEF_HELPER (LINUX_V4_10, GET_NUMA_NODE_ID, get_numa_node_id, TYPES (it, 0))
+DEF_HELPER (LINUX_V4_10, SKB_CHANGE_HEAD, skb_change_head, TYPES (it, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_10, XDP_ADJUST_HEAD, xdp_adjust_head, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_11, PROBE_READ_STR, probe_read_str, TYPES (it, pt, u32t, cpt, 0))
+DEF_HELPER (LINUX_V4_12, GET_SOCKET_COOKIE, get_socket_cookie, TYPES (it, pt, 0))
+DEF_HELPER (LINUX_V4_12, GET_SOCKET_UID, get_socket_uid, TYPES (ut, pt, 0))
+DEF_HELPER (LINUX_V4_13, SET_HASH, set_hash, TYPES (ut, pt, u32t, 0))
+DEF_HELPER (LINUX_V4_13, SETSOCKOPT, setsockopt, TYPES (it, pt, it, it, pt, it, 0))
+DEF_HELPER (LINUX_V4_13, SKB_ADJUST_ROOM, skb_adjust_room, TYPES (it, pt, st, u32t, ullt, 0))
+DEF_HELPER (LINUX_V4_14, REDIRECT_MAP, redirect_map, TYPES (it, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_14, SK_REDIRECT_MAP, sk_redirect_map, TYPES (it, pt, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_14, SOCK_MAP_UPDATE, sock_map_update, TYPES (it, pt, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V4_15, XDP_ADJUST_META, xdp_adjust_meta, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_15, PERF_EVENT_READ_VALUE, perf_event_read_value,
+ TYPES (it, pt, ullt, pt, ut, 0))
+DEF_HELPER (LINUX_V4_15, PERF_PROG_READ_VALUE, perf_prog_read_value,
+ TYPES (it, pt, pt, ut, 0))
+DEF_HELPER (LINUX_V4_15, GETSOCKOPT, getsockopt, TYPES (it, pt, it, it, pt, it, 0))
+
+DEF_HELPER (LINUX_V4_16, OVERRIDE_RETURN, override_return, TYPES (it, pt, ult, 0))
+DEF_HELPER (LINUX_V4_16, SOCK_OPS_CB_FLAGS_SET, sock_ops_cb_flags_set, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_17, MSG_REDIRECT_MAP, msg_redirect_map, TYPES (it, pt, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_17, MSG_APPLY_BYTES, msg_apply_bytes, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_17, MSG_CORK_BYTES, msg_cork_bytes, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_17, MSG_PULL_DATA, msg_pull_data, TYPES (it, pt, it, it, it, 0))
+DEF_HELPER (LINUX_V4_17, BIND, bind, TYPES (it, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_18, XDP_ADJUST_TAIL, xdp_adjust_tail, TYPES (it, pt, it, 0))
+DEF_HELPER (LINUX_V4_18, SKB_GET_XFRM_STATE,
+ skb_get_xfrm_state, TYPES (it, pt, it, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_18, GET_STACK, get_stack, TYPES (it, pt, pt, it, it, 0))
+DEF_HELPER (LINUX_V4_18, SKB_LOAD_BYTES_RELATIVE, skb_load_bytes_relative,
+ TYPES (it, pt, it, pt, it, ut, 0))
+DEF_HELPER (LINUX_V4_18, FIB_LOOKUP, fib_lookup, TYPES (it, pt, pt, it, ut, 0))
+DEF_HELPER (LINUX_V4_18, SOCK_HASH_UPDATE, sock_hash_update, TYPES (it, pt, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V4_18, MSG_REDIRECT_HASH, msg_redirect_hash, TYPES (it, pt, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_18, SK_REDIRECT_HASH, sk_redirect_hash, TYPES (it, pt, pt, pt, it, 0))
+DEF_HELPER (LINUX_V4_18, LWT_PUSH_ENCAP, lwt_push_encap, TYPES (it, pt, ut, pt, ut, 0))
+DEF_HELPER (LINUX_V4_18, LWT_SEG6_STORE_BYTES, lwt_seg6_store_bytes,
+ TYPES (it, pt, ut, pt, ut, 0))
+DEF_HELPER (LINUX_V4_18, LWT_SEG6_ADJUST_SRH, lwt_seg6_adjust_srh, TYPES (it, pt, ut, ut, 0))
+DEF_HELPER (LINUX_V4_18, LWT_SEG6_ACTION, lwt_seg6_action, TYPES (it, pt, ut, pt, ut, 0))
+DEF_HELPER (LINUX_V4_18, RC_REPEAT, rc_repeat, TYPES (it, pt, 0))
+DEF_HELPER (LINUX_V4_18, RC_KEYDOWN, rc_keydown, TYPES (it, pt, ut, ullt, ut, 0))
+DEF_HELPER (LINUX_V4_18, SKB_CGROUP_ID, skb_cgroup_id, TYPES (ullt, pt, 0))
+DEF_HELPER (LINUX_V4_18, GET_CURRENT_CGROUP_ID, get_current_cgroup_id, TYPES (ullt, 0))
+DEF_HELPER (LINUX_V4_19, GET_LOCAL_STORAGE, get_local_storage, TYPES (pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V4_19, SK_SELECT_REUSEPORT, sk_select_reuseport,
+ TYPES (it, pt, pt, pt, ut, 0))
+DEF_HELPER (LINUX_V4_19, SKB_ANCESTOR_CGROUP_ID, skb_ancestor_cgroup_id,
+ TYPES (ullt, pt, it, 0))
+DEF_HELPER (LINUX_V4_20, SK_LOOKUP_TCP, sk_lookup_tcp, TYPES (pt, pt, pt, it, ullt, ullt, 0))
+DEF_HELPER (LINUX_V4_20, SK_LOOKUP_UDP, sk_lookup_udp, TYPES (pt, pt, pt, it, ullt, ullt, 0))
+DEF_HELPER (LINUX_V4_20, SK_RELEASE, sk_release, TYPES (it, pt, 0))
+DEF_HELPER (LINUX_V4_20, MAP_PUSH_ELEM, map_push_elem, TYPES (it, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V4_20, MAP_POP_ELEM, map_pop_elem, TYPES (it, pt, pt, 0))
+DEF_HELPER (LINUX_V4_20, MAP_PEEK_ELEM, map_peek_elem, TYPES (it, pt, pt, 0))
+DEF_HELPER (LINUX_V4_20, MSG_PUSH_DATA, msg_push_data, TYPES (it, pt, it, it, it, 0))
+DEF_HELPER (LINUX_V5_0, MSG_POP_DATA, msg_pop_data, TYPES (it, pt, it, it, it, 0))
+DEF_HELPER (LINUX_V5_0, RC_POINTER_REL, rc_pointer_rel, TYPES (it, pt, it, it, 0))
+DEF_HELPER (LINUX_V5_1, SPIN_LOCK, spin_lock, TYPES (vt, pt, 0))
+DEF_HELPER (LINUX_V5_1, SPIN_UNLOCK, spin_unlock, TYPES (vt, pt, 0))
+DEF_HELPER (LINUX_V5_1, SK_FULLSOCK, sk_fullsock, TYPES (pt, pt, 0))
+DEF_HELPER (LINUX_V5_1, TCP_SOCK, tcp_sock, TYPES (pt, pt, 0))
+DEF_HELPER (LINUX_V5_1, SKB_ECN_SET_CE, skb_ecn_set_ce, TYPES (it, pt, 0))
+DEF_HELPER (LINUX_V5_1, GET_LISTENER_SOCK, get_listener_sock, TYPES (pt, pt, 0))
+DEF_HELPER (LINUX_V5_2, SKC_LOOKUP_TCP, skc_lookup_tcp,
+ TYPES (pt, pt, pt, u32t, u64t, u64t, 0))
+DEF_HELPER (LINUX_V5_2, TCP_CHECK_SYNCOOKIE, tcp_check_syncookie,
+ TYPES (it, pt, pt, u32t, pt, u32t, 0))
+DEF_HELPER (LINUX_V5_2, SYSCTL_GET_NAME, sysctl_get_name, TYPES (it, pt, pt, ullt, u64t, 0))
+DEF_HELPER (LINUX_V5_2, SYSCTL_GET_CURRENT_VALUE, sysctl_get_current_value,
+ TYPES (it, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V5_2, SYSCTL_GET_NEW_VALUE, sysctl_get_new_value,
+ TYPES (it, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V5_2, SYSCTL_SET_NEW_VALUE, sysctl_set_new_value,
+ TYPES (it, pt, pt, ullt, 0))
+DEF_HELPER (LINUX_V5_2, STRTOL, strtol, TYPES (it, cst, ullt, u64t, pt, 0))
+DEF_HELPER (LINUX_V5_2, STRTOUL, strtoul, TYPES (it, pt, ullt, u64t, pt, 0))
+DEF_HELPER (LINUX_V5_2, SK_STORAGE_GET, sk_storage_get, TYPES (pt, pt, pt, pt, u64t, 0))
+DEF_HELPER (LINUX_V5_2, SK_STORAGE_DELETE, sk_storage_delete, TYPES (it, pt, pt, 0))
+
+/*
+Local variables:
+mode:c
+End:
+*/
diff --git a/sim/bpf/bpf-helpers.h b/sim/bpf/bpf-helpers.h
new file mode 100644
index 0000000000..fe9413f266
--- /dev/null
+++ b/sim/bpf/bpf-helpers.h
@@ -0,0 +1,31 @@
+/* Emulation of eBPF helpers. Interface.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef BPF_HELPERS_H
+#define BPF_HELPERS_H
+
+enum bpf_kernel_helper
+ {
+#define DEF_HELPER(kver, name, fn, types) name,
+#include "bpf-helpers.def"
+#undef DEF_HELPER
+ };
+
+/* void bpf_trace_printk (const char *fmt); */
+
+#endif /* ! BPF_HELPERS_H */
diff --git a/sim/bpf/bpf-sim.h b/sim/bpf/bpf-sim.h
new file mode 100644
index 0000000000..6b5c275cd5
--- /dev/null
+++ b/sim/bpf/bpf-sim.h
@@ -0,0 +1,31 @@
+/* eBPF simulator support code header
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef BPF_SIM_H
+#define BPF_SIM_H
+
+void bpfbf_insn_before (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
+void bpfbf_insn_after (sim_cpu* current_cpu, SEM_PC vpc, const IDESC *idesc);
+
+DI bpfbf_endbe (SIM_CPU *, DI, UINT);
+DI bpfbf_endle (SIM_CPU *, DI, UINT);
+DI bpfbf_skb_data_offset (SIM_CPU *);
+VOID bpfbf_call (SIM_CPU *, INT, UINT);
+VOID bpfbf_exit (SIM_CPU *);
+
+#endif /* ! BPF_SIM_H */
diff --git a/sim/bpf/bpf.c b/sim/bpf/bpf.c
new file mode 100644
index 0000000000..766b7ddc1c
--- /dev/null
+++ b/sim/bpf/bpf.c
@@ -0,0 +1,327 @@
+/* eBPF simulator support code
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#define WANT_CPU_BPFBF
+#define WANT_CPU bpfbf
+
+#include "sim-main.h"
+#include "sim-fpu.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+#include "cpuall.h"
+#include "decode.h"
+
+#include "defs-le.h" /* For SCACHE */
+
+/* It is not possible to include both defs-le.h and defs-be.h due to
+ duplicated definitions, so we need a bunch of forward declarations
+ here. */
+extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *);
+extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *);
+
+uint64_t skb_data_offset;
+
+IDESC *bpf_idesc_le;
+IDESC *bpf_idesc_be;
+
+
+int
+bpfbf_fetch_register (SIM_CPU *current_cpu,
+ int rn,
+ unsigned char *buf,
+ int len)
+{
+ if (rn == 11)
+ SETTDI (buf, CPU_PC_GET (current_cpu));
+ else if (0 <= rn && rn < 10)
+ SETTDI (buf, GET_H_GPR (rn));
+ else
+ return 0;
+
+ return len;
+}
+
+int
+bpfbf_store_register (SIM_CPU *current_cpu,
+ int rn,
+ unsigned char *buf,
+ int len)
+{
+ if (rn == 11)
+ CPU_PC_SET (current_cpu, GETTDI (buf));
+ else if (0 <= rn && rn < 10)
+ SET_H_GPR (rn, GETTDI (buf));
+ else
+ return 0;
+
+ return len;
+}
+
+void
+bpfbf_model_insn_before (SIM_CPU *current_cpu, int first_p)
+{
+ /* XXX */
+}
+
+void
+bpfbf_model_insn_after (SIM_CPU *current_cpu, int first_p)
+{
+ /* XXX */
+}
+
+\f
+/***** Instruction helpers. *****/
+
+/* The semantic routines for most instructions are expressed in RTL in
+ the cpu/bpf.cpu file, and automatically translated to C in the
+ sem-*.c files in this directory.
+
+ However, some of the semantic routines make use of helper C
+ functions. This happens when the semantics of the instructions
+ can't be expressed in RTL alone in a satisfactory way, or not at
+ all.
+
+ The following functions implement these C helpers. */
+
+DI
+bpfbf_endle (SIM_CPU *current_cpu, DI value, UINT bitsize)
+{
+ switch (bitsize)
+ {
+ case 16: return endian_h2le_2(endian_t2h_2(value));
+ case 32: return endian_h2le_4(endian_t2h_4(value));
+ case 64: return endian_h2le_8(endian_t2h_8(value));
+ default: assert(0);
+ }
+ return value;
+}
+
+DI
+bpfbf_endbe (SIM_CPU *current_cpu, DI value, UINT bitsize)
+{
+ switch (bitsize)
+ {
+ case 16: return endian_h2be_2(endian_t2h_2(value));
+ case 32: return endian_h2be_4(endian_t2h_4(value));
+ case 64: return endian_h2be_8(endian_t2h_8(value));
+ default: assert(0);
+ }
+ return value;
+}
+
+DI
+bpfbf_skb_data_offset (SIM_CPU *current_cpu)
+{
+ /* Simply return the user-configured value.
+ This will be 0 if it has not been set. */
+ return skb_data_offset;
+}
+
+
+VOID
+bpfbf_call (SIM_CPU *current_cpu, INT disp32, UINT src)
+{
+ /* eBPF supports two kind of CALL instructions: the so called pseudo
+ calls ("bpf to bpf") and external calls ("bpf to helper").
+
+ Both kind of calls use the same instruction (CALL). However,
+ external calls are constructed by passing a constant argument to
+ the instruction, that identifies the helper, whereas pseudo calls
+ result from expressions involving symbols.
+
+ We distinguish calls from pseudo-calls with the later having a 1
+ stored in the SRC field of the instruction. */
+
+ if (src == 1)
+ {
+ /* This is a pseudo-call. */
+
+ /* XXX allocate a new stack frame and transfer control. For
+ that we need to analyze the target function, like the kernel
+ verifier does. We better populate a cache
+ (function_start_address -> frame_size) so we avoid
+ calculating this more than once. */
+ /* XXX note that disp32 is PC-relative in number of 64-bit
+ words, _minus one_. */
+ }
+ else
+ {
+ /* This is a call to a helper.
+
+ DISP32 contains the helper number. Dispatch to the
+ corresponding helper emulator in bpf-helpers.c. */
+
+ switch (disp32) {
+ /* case TRACE_PRINTK: */
+ case 7:
+ bpf_trace_printk (current_cpu);
+ break;
+ default:;
+ }
+ }
+}
+
+VOID
+bpfbf_exit (SIM_CPU *current_cpu)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ /* r0 holds "return code" */
+ DI r0 = GET_H_GPR (0);
+
+ printf ("exit %ld (0x%lx)\n", r0, r0);
+
+ sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
+ sim_exited, 0 /* sigrc */);
+}
+
+VOID
+bpfbf_breakpoint (SIM_CPU *current_cpu)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+
+ sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu),
+ sim_stopped, SIM_SIGTRAP);
+}
+
+/* We use the definitions below instead of the cgen-generated model.c,
+ because the later is not really able to work with cpus featuring
+ several ISAs. This should be fixed in CGEN. */
+
+static void
+bpf_def_model_init ()
+{
+ /* Do nothing. */
+}
+
+static void
+bpfbf_prepare_run (SIM_CPU *cpu)
+{
+ /* Nothing. */
+}
+
+void
+bpf_engine_run_full (SIM_CPU *cpu)
+{
+ if (current_target_byte_order == BFD_ENDIAN_LITTLE)
+ {
+ if (!bpf_idesc_le)
+ {
+ bpfbf_ebpfle_init_idesc_table (cpu);
+ bpf_idesc_le = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = bpf_idesc_le;
+
+ bpfbf_ebpfle_engine_run_full (cpu);
+ }
+ else
+ {
+ if (!bpf_idesc_be)
+ {
+ bpfbf_ebpfbe_init_idesc_table (cpu);
+ bpf_idesc_be = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = bpf_idesc_be;
+
+ bpfbf_ebpfbe_engine_run_full (cpu);
+ }
+}
+
+#if WITH_FAST
+
+void
+bpf_engine_run_fast (SIM_CPU *cpu)
+{
+ if (current_target_byte_order == BFD_ENDIAN_LITTLE)
+ {
+ if (!bpf_idesc_le)
+ {
+ bpfbf_ebpfle_init_idesc_table (cpu);
+ bpf_idesc_le = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = bpf_idesc_le;
+
+ bpfbf_ebpfle_engine_run_fast (cpu);
+ }
+ else
+ {
+ if (!bpf_idesc_be)
+ {
+ bpfbf_ebpfbe_init_idesc_table (cpu);
+ bpf_idesc_be = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = bpf_idesc_be;
+
+ bpfbf_ebpfbe_engine_run_fast (cpu);
+ }
+}
+
+#endif /* WITH_FAST */
+
+static const CGEN_INSN *
+bpfbf_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+bpf_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = bpfbf_fetch_register;
+ CPU_REG_STORE (cpu) = bpfbf_store_register;
+ CPU_PC_FETCH (cpu) = bpfbf_h_pc_get;
+ CPU_PC_STORE (cpu) = bpfbf_h_pc_set;
+ CPU_GET_IDATA (cpu) = bpfbf_get_idata;
+ /* Only used by profiling. 0 disables it. */
+ CPU_MAX_INSNS (cpu) = 0;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = bpf_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = bpf_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = bpf_engine_run_full;
+#endif
+}
+
+static const SIM_MODEL bpf_models[] =
+{
+ { "bpf-def", & bpf_mach, MODEL_BPF_DEF, NULL, bpf_def_model_init },
+ { 0 }
+};
+
+static const SIM_MACH_IMP_PROPERTIES bpfbf_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+const SIM_MACH bpf_mach =
+{
+ "bpf", "bpf", MACH_BPF,
+ 32, 32, & bpf_models[0], & bpfbf_imp_properties,
+ bpf_init_cpu,
+ bpfbf_prepare_run
+};
diff --git a/sim/bpf/config.in b/sim/bpf/config.in
new file mode 100644
index 0000000000..7c667a1c0d
--- /dev/null
+++ b/sim/bpf/config.in
@@ -0,0 +1,248 @@
+/* config.in. Generated from configure.ac by autoheader. */
+
+/* Define if building universal (internal helper macro) */
+#undef AC_APPLE_UNIVERSAL_BUILD
+
+/* Sim debug setting */
+#undef DEBUG
+
+/* Define to 1 if translation of program messages to the user's native
+ language is requested. */
+#undef ENABLE_NLS
+
+/* Define to 1 if you have the <dlfcn.h> header file. */
+#undef HAVE_DLFCN_H
+
+/* Define to 1 if you have the <errno.h> header file. */
+#undef HAVE_ERRNO_H
+
+/* Define to 1 if you have the <fcntl.h> header file. */
+#undef HAVE_FCNTL_H
+
+/* Define to 1 if you have the <fpu_control.h> header file. */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define to 1 if you have the `ftruncate' function. */
+#undef HAVE_FTRUNCATE
+
+/* Define to 1 if you have the `getrusage' function. */
+#undef HAVE_GETRUSAGE
+
+/* Define to 1 if you have the <inttypes.h> header file. */
+#undef HAVE_INTTYPES_H
+
+/* Define to 1 if you have the `nsl' library (-lnsl). */
+#undef HAVE_LIBNSL
+
+/* Define to 1 if you have the `socket' library (-lsocket). */
+#undef HAVE_LIBSOCKET
+
+/* Define to 1 if you have the `lstat' function. */
+#undef HAVE_LSTAT
+
+/* Define to 1 if you have the <memory.h> header file. */
+#undef HAVE_MEMORY_H
+
+/* Define to 1 if you have the `mmap' function. */
+#undef HAVE_MMAP
+
+/* Define to 1 if you have the `munmap' function. */
+#undef HAVE_MUNMAP
+
+/* Define to 1 if you have the `posix_fallocate' function. */
+#undef HAVE_POSIX_FALLOCATE
+
+/* Define to 1 if you have the `sigaction' function. */
+#undef HAVE_SIGACTION
+
+/* Define to 1 if the system has the type `socklen_t'. */
+#undef HAVE_SOCKLEN_T
+
+/* Define to 1 if you have the <stdint.h> header file. */
+#undef HAVE_STDINT_H
+
+/* Define to 1 if you have the <stdlib.h> header file. */
+#undef HAVE_STDLIB_H
+
+/* Define to 1 if you have the <strings.h> header file. */
+#undef HAVE_STRINGS_H
+
+/* Define to 1 if you have the <string.h> header file. */
+#undef HAVE_STRING_H
+
+/* Define to 1 if `st_atime' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_ATIME
+
+/* Define to 1 if `st_blksize' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_BLKSIZE
+
+/* Define to 1 if `st_blocks' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_BLOCKS
+
+/* Define to 1 if `st_ctime' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_CTIME
+
+/* Define to 1 if `st_dev' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_DEV
+
+/* Define to 1 if `st_gid' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_GID
+
+/* Define to 1 if `st_ino' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_INO
+
+/* Define to 1 if `st_mode' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_MODE
+
+/* Define to 1 if `st_mtime' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_MTIME
+
+/* Define to 1 if `st_nlink' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_NLINK
+
+/* Define to 1 if `st_rdev' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_RDEV
+
+/* Define to 1 if `st_size' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_SIZE
+
+/* Define to 1 if `st_uid' is a member of `struct stat'. */
+#undef HAVE_STRUCT_STAT_ST_UID
+
+/* Define to 1 if you have the <sys/mman.h> header file. */
+#undef HAVE_SYS_MMAN_H
+
+/* Define to 1 if you have the <sys/resource.h> header file. */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define to 1 if you have the <sys/times.h> header file. */
+#undef HAVE_SYS_TIMES_H
+
+/* Define to 1 if you have the <sys/time.h> header file. */
+#undef HAVE_SYS_TIME_H
+
+/* Define to 1 if you have the <sys/types.h> header file. */
+#undef HAVE_SYS_TYPES_H
+
+/* Define to 1 if you have the `time' function. */
+#undef HAVE_TIME
+
+/* Define to 1 if you have the <time.h> header file. */
+#undef HAVE_TIME_H
+
+/* Define to 1 if you have the `truncate' function. */
+#undef HAVE_TRUNCATE
+
+/* Define to 1 if you have the <unistd.h> header file. */
+#undef HAVE_UNISTD_H
+
+/* Define to 1 if you have the <windows.h> header file. */
+#undef HAVE_WINDOWS_H
+
+/* Define to 1 if you have the `__setfpucw' function. */
+#undef HAVE___SETFPUCW
+
+/* Define to the sub-directory in which libtool stores uninstalled libraries.
+ */
+#undef LT_OBJDIR
+
+/* Name of this package. */
+#undef PACKAGE
+
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
+
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
+
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the home page for this package. */
+#undef PACKAGE_URL
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* Additional package description */
+#undef PKGVERSION
+
+/* Sim profile settings */
+#undef PROFILE
+
+/* Bug reporting address */
+#undef REPORT_BUGS_TO
+
+/* Define as the return type of signal handlers (`int' or `void'). */
+#undef RETSIGTYPE
+
+/* Define to 1 if you have the ANSI C header files. */
+#undef STDC_HEADERS
+
+/* Enable extensions on AIX 3, Interix. */
+#ifndef _ALL_SOURCE
+# undef _ALL_SOURCE
+#endif
+/* Enable GNU extensions on systems that have them. */
+#ifndef _GNU_SOURCE
+# undef _GNU_SOURCE
+#endif
+/* Enable threading extensions on Solaris. */
+#ifndef _POSIX_PTHREAD_SEMANTICS
+# undef _POSIX_PTHREAD_SEMANTICS
+#endif
+/* Enable extensions on HP NonStop. */
+#ifndef _TANDEM_SOURCE
+# undef _TANDEM_SOURCE
+#endif
+/* Enable general extensions on Solaris. */
+#ifndef __EXTENSIONS__
+# undef __EXTENSIONS__
+#endif
+
+
+/* Sim assert settings */
+#undef WITH_ASSERT
+
+/* Sim debug setting */
+#undef WITH_DEBUG
+
+/* Sim default environment */
+#undef WITH_ENVIRONMENT
+
+/* Sim profile settings */
+#undef WITH_PROFILE
+
+/* How to route I/O */
+#undef WITH_STDIO
+
+/* Sim trace settings */
+#undef WITH_TRACE
+
+/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
+ significant byte first (like Motorola and SPARC, unlike Intel). */
+#if defined AC_APPLE_UNIVERSAL_BUILD
+# if defined __BIG_ENDIAN__
+# define WORDS_BIGENDIAN 1
+# endif
+#else
+# ifndef WORDS_BIGENDIAN
+# undef WORDS_BIGENDIAN
+# endif
+#endif
+
+/* Define to 1 if on MINIX. */
+#undef _MINIX
+
+/* Define to 2 if the system does not provide POSIX.1 features except with
+ this defined. */
+#undef _POSIX_1_SOURCE
+
+/* Define to 1 if you need to in order for `stat' and other things to work. */
+#undef _POSIX_SOURCE
diff --git a/sim/bpf/configure.ac b/sim/bpf/configure.ac
new file mode 100644
index 0000000000..16ca54e86c
--- /dev/null
+++ b/sim/bpf/configure.ac
@@ -0,0 +1,13 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_INIT(Makefile.in)
+sinclude(../common/acinclude.m4)
+
+SIM_AC_COMMON
+
+SIM_AC_OPTION_ENDIAN([], [LITTLE])
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL([bpf-def])
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT
diff --git a/sim/bpf/decode.h b/sim/bpf/decode.h
new file mode 100644
index 0000000000..74d31cbdfe
--- /dev/null
+++ b/sim/bpf/decode.h
@@ -0,0 +1,37 @@
+/* Decode declarations.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+ Contributed by Oracle, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Include declarations for eBPF LE and eBPF BE ISAs. */
+
+#ifndef DECODE_H
+#define DECODE_H
+
+#undef WITH_PROFILE_MODEL_P
+
+#ifdef WANT_ISA_EBPFLE
+#include "decode-le.h"
+#include "defs-le.h"
+#endif /* WANT_ISA_EBPFLE */
+
+#ifdef WANT_ISA_EBPFBE
+#include "decode-be.h"
+#include "defs-be.h"
+#endif /* WANT_ISA_EBPFBE */
+
+#endif /* DECODE_H */
diff --git a/sim/bpf/eng.h b/sim/bpf/eng.h
new file mode 100644
index 0000000000..08e29f99a8
--- /dev/null
+++ b/sim/bpf/eng.h
@@ -0,0 +1,24 @@
+/* Engine declarations.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+ Contributed by Oracle, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+/* Include declarations for eBPF LE and eBPF BE ISAs. */
+
+#include "eng-le.h"
+#include "eng-be.h"
+
diff --git a/sim/bpf/mloop.in b/sim/bpf/mloop.in
new file mode 100644
index 0000000000..2661eed8a8
--- /dev/null
+++ b/sim/bpf/mloop.in
@@ -0,0 +1,165 @@
+# Simulator main loop for eBPF. -*- C -*-
+#
+# Copyright (C) 2020 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+# Syntax:
+# /bin/sh mloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same, or if
+# the slow (full featured) version is `simple', then the fast version can be
+# one of scache/pbb.
+# A target can't provide more than this.
+# However for illustration's sake this file provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_WORD insn,
+ ARGBUF *abuf, int fast_p)
+{
+ const IDESC *id = @prefix@_decode (current_cpu, pc, insn, abuf);
+ @prefix@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (!fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ @prefix@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+ else
+ {
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+ const CGEN_INSN *idata = idesc->idata;
+ int virtual_p = 0;
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+ CGEN_TRACE_INSN_INIT (current_cpu, abuf, 1);
+ CGEN_TRACE_INSN (current_cpu, idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ CGEN_TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+ }
+
+ return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+# Nothing needed.
+
+;;
+
+xextract-scache)
+
+cat <<EOF
+{
+
+ UDI insn = GETIMEMUDI (current_cpu, vpc);
+
+ if (current_target_byte_order == BFD_ENDIAN_BIG)
+ {
+ /* eBPF instructions are little-endian, but GETIMEMUDI reads according
+ to target byte order. Swap to little-endian. */
+ insn = SWAP_8 (insn);
+
+ /* But, the imm32 and offset16 fields within instructions follow target
+ byte order. Swap those fields back. */
+ UHI off16 = (UHI) ((insn & 0x00000000ffff0000) >> 16);
+ USI imm32 = (USI) ((insn & 0xffffffff00000000) >> 32);
+ off16 = SWAP_2 (off16);
+ imm32 = SWAP_4 (imm32);
+
+ insn = (((UDI) imm32) << 32) | (((UDI) off16) << 16) | (insn & 0xffff);
+ }
+
+ extract (current_cpu, vpc, insn, sc, FAST_P);
+
+ //XXX SEM_SKIP_COMPILE (current_cpu, sc, 1);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, vpc, sc, FAST_P
+# Outputs: vpc
+# vpc is the virtual program counter.
+
+cat <<EOF
+ vpc = execute (current_cpu, sc, FAST_P);
+EOF
+
+;;
+
+*)
+ echo "Invalid argument to mainloop.in: $1" >&2
+ exit 1
+ ;;
+
+esac
diff --git a/sim/bpf/sim-if.c b/sim/bpf/sim-if.c
new file mode 100644
index 0000000000..964cc705eb
--- /dev/null
+++ b/sim/bpf/sim-if.c
@@ -0,0 +1,216 @@
+/* Main simulator entry points specific to the eBPF.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#include "sim-main.h"
+#include "sim-options.h"
+#include "libiberty.h"
+#include "bfd.h"
+
+/* Globals. */
+
+/* String with the name of the section containing the BPF program to
+ run. */
+static char *bpf_program_section = NULL;
+
+extern uint64_t skb_data_offset;
+
+\f
+/* Handle BPF-specific options. */
+
+static SIM_RC bpf_option_handler (SIM_DESC, sim_cpu *, int, char *, int);
+
+typedef enum
+{
+ OPTION_BPF_SET_PROGRAM = OPTION_START,
+ OPTION_BPF_LIST_PROGRAMS,
+ OPTION_BPF_VERIFY_PROGRAM,
+ OPTION_BPF_SKB_DATA_OFFSET,
+} BPF_OPTION;
+
+static const OPTION bpf_options[] =
+{
+ { {"bpf-set-program", required_argument, NULL, OPTION_BPF_SET_PROGRAM},
+ '\0', "SECTION_NAME", "Set the entry point",
+ bpf_option_handler },
+ { {"bpf-list-programs", no_argument, NULL, OPTION_BPF_LIST_PROGRAMS},
+ '\0', "", "List loaded bpf programs",
+ bpf_option_handler },
+ { {"bpf-verify-program", required_argument, NULL, OPTION_BPF_VERIFY_PROGRAM},
+ '\0', "PROGRAM", "Run the verifier on the given BPF program",
+ bpf_option_handler },
+ { {"skb-data-offset", required_argument, NULL, OPTION_BPF_SKB_DATA_OFFSET},
+ '\0', "OFFSET", "Configure offsetof(struct sk_buff, data)",
+ bpf_option_handler },
+
+ { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL, NULL }
+};
+
+static SIM_RC
+bpf_option_handler (SIM_DESC sd, sim_cpu *cpu ATTRIBUTE_UNUSED, int opt,
+ char *arg, int is_command ATTRIBUTE_UNUSED)
+{
+ switch ((BPF_OPTION) opt)
+ {
+ case OPTION_BPF_VERIFY_PROGRAM:
+ /* XXX call the verifier. */
+ sim_io_printf (sd, "Verifying BPF program %s...\n", arg);
+ break;
+
+ case OPTION_BPF_LIST_PROGRAMS:
+ /* XXX list programs. */
+ sim_io_printf (sd, "BPF programs available:\n");
+ break;
+
+ case OPTION_BPF_SET_PROGRAM:
+ /* XXX: check that the section exists and tell the user about a
+ new start_address. */
+ bpf_program_section = xstrdup (arg);
+ break;
+
+ case OPTION_BPF_SKB_DATA_OFFSET:
+ skb_data_offset = strtoul (arg, NULL, 0);
+ break;
+
+ default:
+ sim_io_eprintf (sd, "Unknown option `%s'\n", arg);
+ return SIM_RC_FAIL;
+ }
+
+ return SIM_RC_OK;
+}
+
+/* Like sim_state_free, but free the cpu buffers as well. */
+
+static void
+bpf_free_state (SIM_DESC sd)
+{
+ if (STATE_MODULES (sd) != NULL)
+ sim_module_uninstall (sd);
+
+ sim_cpu_free_all (sd);
+ sim_state_free (sd);
+}
+
+/* Create an instance of the simulator. */
+
+SIM_DESC
+sim_open (SIM_OPEN_KIND kind,
+ host_callback *callback,
+ struct bfd *abfd,
+ char * const *argv)
+{
+ /* XXX Analyze the program, and collect per-function information
+ like the kernel verifier does. The implementation of the CALL
+ instruction will need that information, to update %fp. */
+
+ SIM_DESC sd = sim_state_alloc (kind, callback);
+
+ /* ... */
+
+ if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ())
+ != SIM_RC_OK)
+ goto error;
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ goto error;
+
+ /* Add the BPF-specific option list to the simulator. */
+ if (sim_add_option_table (sd, NULL, bpf_options) != SIM_RC_OK)
+ {
+ bpf_free_state (sd);
+ return 0;
+ }
+
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ goto error;
+
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL), abfd) != SIM_RC_OK)
+ goto error;
+
+ if (sim_config (sd) != SIM_RC_OK)
+ goto error;
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ goto error;
+
+ /* ... */
+
+ /* Initialize the CPU descriptors and the disassemble in the cpu
+ descriptor table entries. */
+ {
+ int i;
+ CGEN_CPU_DESC cd = bpf_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+ CGEN_ENDIAN_LITTLE);
+
+ /* We have one cpu per installed program! MAX_NR_PROCESSORS is an
+ arbitrary upper limit. XXX where is it defined? */
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+
+ CPU_CPU_DESC (cpu) = cd;
+ CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
+ }
+
+ bpf_cgen_init_dis (cd);
+ }
+
+ /* Initialize various cgen things not done by common framework.
+ Must be done after bpf_cgen_cpu_open. */
+ cgen_init (sd);
+
+ /* XXX do eBPF sim specific initializations. */
+
+ return sd;
+
+ error:
+ bpf_free_state (sd);
+ return NULL;
+}
+\f
+
+SIM_RC
+sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
+ char *const *argv, char *const *envp)
+{
+ SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+ SIM_ADDR addr;
+
+ /* Determine the start address.
+
+ XXX acknowledge bpf_program_section. If it is NULL, emit a
+ warning explaining that we are using the ELF file start address,
+ which often is not what is actually wanted. */
+ if (abfd != NULL)
+ addr = bfd_get_start_address (abfd);
+ else
+ addr = 0;
+
+ sim_pc_set (current_cpu, addr);
+
+ if (STATE_PROG_ARGV (sd) != argv)
+ {
+ freeargv (STATE_PROG_ARGV (sd));
+ STATE_PROG_ARGV (sd) = dupargv (argv);
+ }
+
+ return SIM_RC_OK;
+}
diff --git a/sim/bpf/sim-main.h b/sim/bpf/sim-main.h
new file mode 100644
index 0000000000..fc1e69f6f3
--- /dev/null
+++ b/sim/bpf/sim-main.h
@@ -0,0 +1,51 @@
+/* eBPF simulator main header
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#ifndef SIM_MAIN_H
+#define SIM_MAIN_H
+
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "bpf-desc.h"
+#include "bpf-opc.h"
+#include "arch.h"
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "bpf-sim.h"
+
+
+struct _sim_cpu
+{
+ sim_cpu_base base;
+ CGEN_CPU cgen_cpu;
+
+#if defined (WANT_CPU_BPFBF)
+ BPFBF_CPU_DATA cpu_data;
+#endif
+};
+
+\f
+
+struct sim_state
+{
+ sim_cpu *cpu[MAX_NR_PROCESSORS];
+ CGEN_STATE cgen_state;
+ sim_state_base base;
+};
+
+#endif /* ! SIM_MAIN_H */
diff --git a/sim/bpf/traps.c b/sim/bpf/traps.c
new file mode 100644
index 0000000000..e7ac0c2838
--- /dev/null
+++ b/sim/bpf/traps.c
@@ -0,0 +1,33 @@
+/* Trap handlers for eBPF.
+ Copyright (C) 2020 Free Software Foundation, Inc.
+
+ This file is part of GDB, the GNU debugger.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+#define WANT_CPU bpfbf
+#define WANT_CPU_BPFBF
+
+#include "sim-main.h"
+
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu ATTRIBUTE_UNUSED,
+ IADDR cia ATTRIBUTE_UNUSED,
+ SEM_PC pc ATTRIBUTE_UNUSED)
+{
+ /* Can't just return 0 here: the return value is used to set vpc
+ (see decdde-{le,be}.c)
+ Returning 0 will cause an infinite loop! */
+ abort();
+}
diff --git a/sim/configure b/sim/configure
index 72f95cd5c7..37a86f435c 100755
--- a/sim/configure
+++ b/sim/configure
@@ -669,6 +669,7 @@ ac_subdirs_all='aarch64
arm
avr
bfin
+bpf
cr16
cris
d10v
@@ -3717,6 +3718,13 @@ subdirs="$subdirs aarch64"
subdirs="$subdirs bfin"
+ ;;
+ bpf-*-*)
+
+ sim_arch=bpf
+ subdirs="$subdirs bpf"
+
+
;;
cr16*-*-*)
diff --git a/sim/configure.tgt b/sim/configure.tgt
index 8a8e03d96f..c115c3c8dd 100644
--- a/sim/configure.tgt
+++ b/sim/configure.tgt
@@ -26,6 +26,9 @@ case "${target}" in
bfin-*-*)
SIM_ARCH(bfin)
;;
+ bpf-*-*)
+ SIM_ARCH(bpf)
+ ;;
cr16*-*-*)
SIM_ARCH(cr16)
;;
diff --git a/sim/testsuite/configure b/sim/testsuite/configure
index a3e7fa7131..c3674c2fa0 100755
--- a/sim/testsuite/configure
+++ b/sim/testsuite/configure
@@ -1875,6 +1875,9 @@ case "${target}" in
bfin-*-*)
sim_arch=bfin
;;
+ bpf-*-*)
+ sim_arch=bpf
+ ;;
cr16*-*-*)
sim_arch=cr16
;;
@@ -1928,6 +1931,9 @@ case "${target}" in
or1k-*-* | or1knd-*-*)
sim_arch=or1k
;;
+ pru*-*-*)
+ sim_arch=pru
+ ;;
rl78-*-*)
sim_arch=rl78
;;
@@ -1946,9 +1952,6 @@ case "${target}" in
powerpc*-*-*)
sim_arch=ppc
;;
- pru*-*-*)
- sim_arch=pru
- ;;
ft32-*-*)
sim_arch=ft32
;;
diff --git a/sim/testsuite/sim/bpf/allinsn.exp b/sim/testsuite/sim/bpf/allinsn.exp
new file mode 100644
index 0000000000..2cca77021a
--- /dev/null
+++ b/sim/testsuite/sim/bpf/allinsn.exp
@@ -0,0 +1,26 @@
+# eBPF simulator testsuite
+
+if [istarget bpf-unknown-none] {
+ # all machines
+ set all_machs "bpf"
+
+ global global_sim_options
+ if ![info exists global_sim_options] {
+ set global_sim_options "--memory-size=4Mb"
+ }
+
+ global global_ld_options
+ if ![info exists global_ld_options] {
+ set global_ld_options "-Ttext=0x0"
+ }
+
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+
+ run_sim_test $src $all_machs
+ }
+}
diff --git a/sim/testsuite/sim/bpf/alu.s b/sim/testsuite/sim/bpf/alu.s
new file mode 100644
index 0000000000..6013ac7eb9
--- /dev/null
+++ b/sim/testsuite/sim/bpf/alu.s
@@ -0,0 +1,109 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;;; alu.s
+;;; Tests for ALU64 BPF instructions in simulator
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ mov %r1, 0
+ mov %r2, -1
+
+ ;; add
+ add %r1, 1
+ add %r2, -1
+ add %r1, %r2
+ fail_ne %r1, -1
+
+ ;; sub
+ sub %r1, %r1
+ fail_ne %r1, 0
+ sub %r1, 10
+ sub %r2, %r1
+ fail_ne %r2, 8
+
+ ;; mul
+ mul %r2, %r2 ; r2 = 64
+ mul %r2, 3 ; r2 = 192
+ mov %r1, -3
+ mul %r1, %r2 ; r1 = -576
+ mul %r2, 0
+ fail_ne %r1, -576
+ fail_ne %r2, 0
+ mul %r1, %r1
+ mul %r1, %r1
+ fail_ne %r1, 110075314176
+
+ ;; div
+ div %r2, %r1
+ fail_ne %r2, 0
+ div %r1, -10000
+ fail_ne %r1, -11007531
+ div %r1, %r1
+ fail_ne %r1, 1
+
+ ;; and
+ lddw %r1, 0xaaaaaaaa55555555
+ and %r1, 0x55aaaaaa ; we still only have 32-bit imm.
+ fail_ne %r1, 0x0000000055000000
+ lddw %r2, 0x5555555a5aaaaaaa
+ and %r2, %r1
+ fail_ne %r2, 0x0000000050000000
+
+ ;; or
+ or %r2, 0xdeadbeef
+ fail_ne %r2, 0xffffffffdeadbeef ; 0xdeadbeef gets sign extended
+ lddw %r1, 0xdead00000000beef
+ lddw %r2, 0x0000123456780000
+ or %r1, %r2
+ fail_ne %r1, 0xdead12345678beef
+
+ ;; lsh
+ mov %r1, 0xdeadbeef
+ lsh %r1, 11
+ fail_ne %r1, 0xfffffef56df77800 ; because deadbeef gets sign ext.
+ mov %r2, 21
+ lsh %r1, %r2
+ fail_ne %r1, 0xdeadbeef00000000
+
+ ;; rsh
+ rsh %r1, 11
+ fail_ne %r1, 0x001bd5b7dde00000 ; 0xdeadbeef 00000000 >> 0xb
+ rsh %r1, %r2
+ fail_ne %r1, 0x00000000deadbeef
+
+ ;; arsh
+ arsh %r1, 8
+ fail_ne %r1, 0x0000000000deadbe
+ lsh %r1, 40 ; r1 = 0xdead be00 0000 0000
+ arsh %r1, %r2 ; r1 arsh (r2 == 21)
+ fail_ne %r1, 0xfffffef56df00000
+
+ ;; mod
+ mov %r1, 1025
+ mod %r1, -16
+ fail_ne %r1, 1
+ mov %r1, -25
+ mov %r2, 5
+ mod %r1, %r2
+ fail_ne %r1, 0
+
+ ;; xor
+ xor %r1, %r2
+ fail_ne %r1, 5
+ xor %r1, 0x7eadbeef
+ fail_ne %r1, 0x7eadbeea
+ xor %r1, %r1
+ fail_ne %r1, 0
+
+ ;; neg
+ neg %r2
+ fail_ne %r2, -5
+ mov %r1, -1025
+ neg %r1
+ fail_ne %r1, 1025
+
+ pass
diff --git a/sim/testsuite/sim/bpf/alu32.s b/sim/testsuite/sim/bpf/alu32.s
new file mode 100644
index 0000000000..a611abd6f6
--- /dev/null
+++ b/sim/testsuite/sim/bpf/alu32.s
@@ -0,0 +1,99 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;; alu32.s
+;; Tests for ALU(32) BPF instructions in simulator
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ mov32 %r1, 10 ; r1 = 10
+ mov32 %r2, -5 ; r2 = -5
+
+ ;; add
+ add32 %r1, 1 ; r1 += 1 (r1 = 11)
+ add32 %r2, -1 ; r2 += -1 (r2 = -6)
+ add32 %r1, %r2 ; r1 += r2 (r1 = 11 + -6 = 5)
+ fail_ne32 %r1, 5
+
+ ;; sub
+ sub32 %r1, 5 ; r1 -= 5 (r1 = 0)
+ sub32 %r1, -5 ; r1 -= -5 (r1 = 5)
+ sub32 %r1, %r2 ; r1 -= r2 (r1 = 5 - -6 = 11)
+ fail_ne32 %r1, 11
+
+ ;; mul
+ mul32 %r1, 2 ; r1 *= 2 (r1 = 22)
+ mul32 %r1, -2 ; r1 *= -2 (r1 = -44)
+ mul32 %r1, %r2 ; r1 *= r2 (r1 = -44 * -6 = 264)
+ fail_ne32 %r1, 264
+
+ ;; div
+ div32 %r1, %r2 ; r1 /= r2 (r1 = 264 / -6 = -44)
+ div32 %r1, -2 ; r1 /= -2 (r1 = 22)
+ div32 %r1, 2 ; r1 /= 2 (r1 = 11)
+ fail_ne32 %r1, 11
+
+ ;; and (bitwise)
+ mov32 %r1, 0xb ; r1 = (0xb = 0b1011)
+ mov32 %r2, 0x5 ; r2 = (0x5 = 0b0101)
+ and32 %r1, 0xa ; r1 &= (0xa = 0b1010) = (0b1010 = 0xa)
+ fail_ne32 %r1, 0xa
+ and32 %r1, %r2 ; r1 &= r2 = 0x0
+ fail_ne32 %r1, 0x0
+
+ ;; or (bitwise)
+ or32 %r1, 0xb
+ or32 %r1, %r2
+ fail_ne32 %r1, 0xf
+
+ ;; lsh (left shift)
+ lsh32 %r1, 4 ; r1 <<= 4 (r1 = 0xf0)
+ mov32 %r2, 24 ; r2 = 24
+ lsh32 %r1, %r2
+ fail_ne32 %r1, 0xf0000000
+
+ ;; rsh (right logical shift)
+ rsh32 %r1, 2
+ rsh32 %r1, %r2
+ fail_ne32 %r1, 0x3c ; (0xf000 0000 >> 26)
+
+ ;; arsh (right arithmetic shift)
+ arsh32 %r1, 1
+ or32 %r1, 0x80000000
+ mov32 %r2, 3
+ arsh32 %r1, %r2
+ fail_ne %r1, 0x00000000F0000003
+ ; Note: make sure r1 is NOT sign-extended
+ ; i.e. upper-32 bits should be untouched
+
+ ;; mod
+ mov32 %r1, -25
+ mov32 %r2, 4
+ mod32 %r1, %r2
+ fail_ne32 %r1, -1
+ mov32 %r1, 25
+ mod32 %r1, 5
+ fail_ne32 %r1, 0
+
+ ;; xor
+ xor32 %r1, %r2
+ fail_ne32 %r1, 4
+ xor32 %r1, 0xF000000F
+ fail_ne %r1, 0xF000000B ; Note: check for (bad) sign-extend
+ xor32 %r1, %r1
+ fail_ne %r1, 0
+
+ ;; neg
+ mov32 %r1, -1
+ mov32 %r2, 0x7fffffff
+ neg32 %r1
+ neg32 %r2
+ fail_ne32 %r1, 1
+ fail_ne %r2, 0x80000001 ; Note: check for (bad) sign-extend
+ neg32 %r2
+ fail_ne32 %r2, 0x7fffffff
+
+ pass
diff --git a/sim/testsuite/sim/bpf/endbe.s b/sim/testsuite/sim/bpf/endbe.s
new file mode 100644
index 0000000000..2f662aec02
--- /dev/null
+++ b/sim/testsuite/sim/bpf/endbe.s
@@ -0,0 +1,46 @@
+# mach: bpf
+# as: --EB
+# ld: --EB
+# sim: -E big
+# output: pass\nexit 0 (0x0)\n
+;;; endbe.s
+;;; Tests for BPF endianness-conversion instructions in simulator
+;;; running in BIG ENDIAN
+;;;
+;;; Both 'be' and 'le' ISAs have both endbe and endle instructions.
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ lddw %r1, 0x12345678deadbeef
+ endle %r1, 64
+ fail_ne %r1, 0xefbeadde78563412
+ endle %r1, 64
+ fail_ne %r1, 0x12345678deadbeef
+
+ ;; `bitsize` < 64 will truncate
+ endle %r1, 32
+ fail_ne %r1, 0xefbeadde
+ endle %r1, 32
+ fail_ne %r1, 0xdeadbeef
+
+ endle %r1, 16
+ fail_ne %r1, 0xefbe
+ endle %r1, 16
+ fail_ne %r1, 0xbeef
+
+ ;; endbe on be should be noop (except truncate)
+ lddw %r1, 0x12345678deadbeef
+ endbe %r1, 64
+ fail_ne %r1, 0x12345678deadbeef
+
+ endbe %r1, 32
+ fail_ne %r1, 0xdeadbeef
+
+ endbe %r1, 16
+ fail_ne %r1, 0xbeef
+
+ pass
diff --git a/sim/testsuite/sim/bpf/endle.s b/sim/testsuite/sim/bpf/endle.s
new file mode 100644
index 0000000000..d8f5ceb977
--- /dev/null
+++ b/sim/testsuite/sim/bpf/endle.s
@@ -0,0 +1,43 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;;; endle.s
+;;; Tests for BPF endianness-conversion instructions in simulator
+;;; running in LITTLE ENDIAN
+;;;
+;;; Both 'be' and 'le' ISAs have both endbe and endle instructions.
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ lddw %r1, 0x12345678deadbeef
+ endbe %r1, 64
+ fail_ne %r1, 0xefbeadde78563412
+ endbe %r1, 64
+ fail_ne %r1, 0x12345678deadbeef
+
+ ;; `bitsize` < 64 will truncate
+ endbe %r1, 32
+ fail_ne %r1, 0xefbeadde
+ endbe %r1, 32
+ fail_ne %r1, 0xdeadbeef
+
+ endbe %r1, 16
+ fail_ne %r1, 0xefbe
+ endbe %r1, 16
+ fail_ne %r1, 0xbeef
+
+ ;; endle on le should be noop (except truncate)
+ lddw %r1, 0x12345678deadbeef
+ endle %r1, 64
+ fail_ne %r1, 0x12345678deadbeef
+
+ endle %r1, 32
+ fail_ne %r1, 0xdeadbeef
+
+ endle %r1, 16
+ fail_ne %r1, 0xbeef
+
+ pass
diff --git a/sim/testsuite/sim/bpf/jmp.s b/sim/testsuite/sim/bpf/jmp.s
new file mode 100644
index 0000000000..a9fe88be4a
--- /dev/null
+++ b/sim/testsuite/sim/bpf/jmp.s
@@ -0,0 +1,120 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;;; jmp.s
+;;; Tests for eBPF JMP instructions in simulator
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ mov %r1, 5
+ mov %r2, 2
+ mov %r3, 7
+ mov %r4, -1
+
+ ;; ja - jump absolute (unconditional)
+ ja 2f
+1: fail
+
+2: ;; jeq - jump eq
+ jeq %r1, 4, 1b ; no
+ jeq %r1, %r2, 1b ; no
+ jeq %r1, 5, 2f ; yes
+ fail
+2: jeq %r1, %r1, 2f ; yes
+ fail
+
+2: ;; jgt - jump (unsigned) greater-than
+ jgt %r1, 6, 1b ; no
+ jgt %r1, -5, 1b ; no - unsigned
+ jgt %r1, %r4, 1b ; no - unsigned
+ jgt %r1, 4, 2f ; yes
+ fail
+2: jgt %r1, %r2, 2f ; yes
+ fail
+
+2: ;; jge - jump (unsigned) greater-than-or-equal-to
+ jge %r1, 6, 1b ; no
+ jge %r1, 5, 2f ; yes
+ fail
+2: jge %r1, %r3, 1b ; no
+ jge %r1, -5, 1b ; no - unsigned
+ jge %r1, %r2, 2f ; yes
+ fail
+
+2: ;; jlt - jump (unsigned) less-than
+ jlt %r1, 5, 1b ; no
+ jlt %r1, %r2, 1b ; no
+ jlt %r4, %r1, 1b ; no - unsigned
+ jlt %r1, 6, 2f ; yes
+ fail
+2:
+ jlt %r1, %r3, 2f ; yes
+ fail
+
+2: ;; jle - jump (unsigned) less-than-or-equal-to
+ jle %r1, 4, 1b ; no
+ jle %r1, %r2, 1b ; no
+ jle %r4, %r1, 1b ; no
+ jle %r1, 5, 2f ; yes
+ fail
+2: jle %r1, %r1, 2f ; yes
+ fail
+
+2: ;; jset - jump "test" (AND)
+ jset %r1, 2, 1b ; no (5 & 2 = 0)
+ jset %r1, %r2, 1b ; no (same)
+ jset %r1, 4, 2f ; yes (5 & 4 != 0)
+ fail
+
+2: ;; jne - jump not-equal-to
+ jne %r1, 5, 1b ; no
+ jne %r1, %r1, 1b ; no
+ jne %r1, 6, 2f ; yes
+ fail
+2: jne %r1, %r4, 2f ; yes
+ fail
+
+2: ;; jsgt - jump (signed) greater-than
+ jsgt %r1, %r3, 1b ; no
+ jsgt %r1, %r1, 1b ; no
+ jsgt %r1, 5, 1b ; no
+ jsgt %r1, -4, 2f ; yes
+ fail
+2: jsgt %r1, %r4, 2f ; yes
+ fail
+
+2: ;; jsge - jump (signed) greater-than-or-equal-to
+ jsge %r1, %r3, 1b ; no
+ jsge %r1, %r1, 2f ; yes
+ fail
+2: jsge %r1, 7, 1b ; no
+ jsge %r1, -4, 2f ; yes
+ fail
+2: jsge %r1, %r4, 2f ; yes
+ fail
+
+2: ;; jslt - jump (signed) less-than
+ jslt %r1, 5, 1b ; no
+ jslt %r1, %r2, 1b ; no
+ jslt %r4, %r1, 2f ; yes
+ fail
+2: jslt %r1, 6, 2f ; yes
+ fail
+2: jslt %r1, %r3, 2f ; yes
+ fail
+
+2: ;; jsle - jump (signed) less-than-or-equal-to
+ jsle %r1, 4, 1b ; no
+ jsle %r1, %r2, 1b ; no
+ jsle %r4, %r1, 2f ; yes
+ fail
+2: jsle %r1, 5, 2f ; yes
+ fail
+2: jsle %r1, %r3, 2f ; yes
+ fail
+
+2:
+ pass
diff --git a/sim/testsuite/sim/bpf/jmp32.s b/sim/testsuite/sim/bpf/jmp32.s
new file mode 100644
index 0000000000..3621295129
--- /dev/null
+++ b/sim/testsuite/sim/bpf/jmp32.s
@@ -0,0 +1,120 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;;; jmp32.s
+;;; Tests for eBPF JMP32 instructions in simulator
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ mov32 %r1, 5
+ mov32 %r2, 2
+ mov32 %r3, 7
+ mov32 %r4, -1
+
+ ;; ja - jump absolute (unconditional)
+ ja 2f
+1: fail
+
+2: ;; jeq - jump eq
+ jeq32 %r1, 4, 1b ; no
+ jeq32 %r1, %r2, 1b ; no
+ jeq32 %r1, 5, 2f ; yes
+ fail
+2: jeq32 %r1, %r1, 2f ; yes
+ fail
+
+2: ;; jgt - jump (unsigned) greater-than
+ jgt32 %r1, 6, 1b ; no
+ jgt32 %r1, -5, 1b ; no - unsigned
+ jgt32 %r1, %r4, 1b ; no - unsigned
+ jgt32 %r1, 4, 2f ; yes
+ fail
+2: jgt32 %r1, %r2, 2f ; yes
+ fail
+
+2: ;; jge - jump (unsigned) greater-than-or-equal-to
+ jge32 %r1, 6, 1b ; no
+ jge32 %r1, 5, 2f ; yes
+ fail
+2: jge32 %r1, %r3, 1b ; no
+ jge32 %r1, -5, 1b ; no - unsigned
+ jge32 %r1, %r2, 2f ; yes
+ fail
+
+2: ;; jlt - jump (unsigned) less-than
+ jlt32 %r1, 5, 1b ; no
+ jlt32 %r1, %r2, 1b ; no
+ jlt32 %r4, %r1, 1b ; no - unsigned
+ jlt32 %r1, 6, 2f ; yes
+ fail
+2:
+ jlt32 %r1, %r3, 2f ; yes
+ fail
+
+2: ;; jle - jump (unsigned) less-than-or-equal-to
+ jle32 %r1, 4, 1b ; no
+ jle32 %r1, %r2, 1b ; no
+ jle32 %r4, %r1, 1b ; no
+ jle32 %r1, 5, 2f ; yes
+ fail
+2: jle32 %r1, %r1, 2f ; yes
+ fail
+
+2: ;; jset - jump "test" (AND)
+ jset32 %r1, 2, 1b ; no (5 & 2 = 0)
+ jset32 %r1, %r2, 1b ; no (same)
+ jset32 %r1, 4, 2f ; yes (5 & 4 != 0)
+ fail
+
+2: ;; jne - jump not-equal-to
+ jne32 %r1, 5, 1b ; no
+ jne32 %r1, %r1, 1b ; no
+ jne32 %r1, 6, 2f ; yes
+ fail
+2: jne32 %r1, %r4, 2f ; yes
+ fail
+
+2: ;; jsgt - jump (signed) greater-than
+ jsgt32 %r1, %r3, 1b ; no
+ jsgt32 %r1, %r1, 1b ; no
+ jsgt32 %r1, 5, 1b ; no
+ jsgt32 %r1, -4, 2f ; yes
+ fail
+2: jsgt32 %r1, %r4, 2f ; yes
+ fail
+
+2: ;; jsge - jump (signed) greater-than-or-equal-to
+ jsge32 %r1, %r3, 1b ; no
+ jsge32 %r1, %r1, 2f ; yes
+ fail
+2: jsge32 %r1, 7, 1b ; no
+ jsge32 %r1, -4, 2f ; yes
+ fail
+2: jsge32 %r1, %r4, 2f ; yes
+ fail
+
+2: ;; jslt - jump (signed) less-than
+ jslt32 %r1, 5, 1b ; no
+ jslt32 %r1, %r2, 1b ; no
+ jslt32 %r4, %r1, 2f ; yes
+ fail
+2: jslt32 %r1, 6, 2f ; yes
+ fail
+2: jslt32 %r1, %r3, 2f ; yes
+ fail
+
+2: ;; jsle - jump (signed) less-than-or-equal-to
+ jsle32 %r1, 4, 1b ; no
+ jsle32 %r1, %r2, 1b ; no
+ jsle32 %r4, %r1, 2f ; yes
+ fail
+2: jsle32 %r1, 5, 2f ; yes
+ fail
+2: jsle32 %r1, %r3, 2f ; yes
+ fail
+
+2:
+ pass
diff --git a/sim/testsuite/sim/bpf/ldabs.s b/sim/testsuite/sim/bpf/ldabs.s
new file mode 100644
index 0000000000..ae777f1cf5
--- /dev/null
+++ b/sim/testsuite/sim/bpf/ldabs.s
@@ -0,0 +1,87 @@
+# mach: bpf
+# sim: --skb-data-offset=0x20
+# output: pass\nexit 0 (0x0)\n
+;;; ldabs.s
+;;; Tests for non-generic BPF load instructions in simulator.
+;;; These instructions (ld{abs,ind}{b,h,w,dw}) are used to access
+;;; kernel socket data from BPF programs for high performance filters.
+;;;
+;;; Register r6 is an implicit input holding a pointer to a struct sk_buff.
+;;; Register r0 is an implicit output, holding the fetched data.
+;;;
+;;; e.g.
+;;; ldabsw means:
+;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + imm32))
+;;;
+;;; ldindw means
+;;; r0 = ntohl (*(u32 *) (((struct sk_buff *)r6)->data + src_reg + imm32))
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ ;; R6 holds a pointer to a struct sk_buff, which we pretend
+ ;; exists at 0x1000
+ mov %r6, 0x1000
+
+ ;; We configure skb-data-offset=0x20
+ ;; This specifies offsetof(struct sk_buff, data), where the field 'data'
+ ;; is a pointer a data buffer, in this case at 0x2000
+ stw [%r6+0x20], 0x2000
+
+ ;; Write the value 0x7eadbeef into memory at 0x2004
+ ;; i.e. offset 4 within the data buffer pointed to by
+ ;; ((struct sk_buff *)r6)->data
+ stw [%r6+0x1004], 0xdeadbeef
+
+ ;; Now load data[4] into r0 using the ldabsw instruction
+ ldabsw 0x4
+
+ ;; ...and compare to what we expect
+ fail_ne32 %r0, 0xdeadbeef
+
+ ;; Repeat for a half-word (2-bytes)
+ sth [%r6+0x1008], 0x1234
+ ldabsh 0x8
+ fail_ne32 %r0, 0x1234
+
+ ;; Repeat for a single byte
+ stb [%r6+0x1010], 0x5a
+ ldabsb 0x10
+ fail_ne32 %r0, 0x5a
+
+ ;; Repeat for a double-word (8-byte)
+ ;; (note: fail_ne macro uses r0, so copy to another r1 to compare)
+ lddw %r2, 0x1234deadbeef5678
+ stxdw [%r6+0x1018], %r2
+ ldabsdw 0x18
+ mov %r1, %r0
+ fail_ne %r1, 0x1234deadbeef5678
+
+ ;; Now, we do the same for the indirect loads
+ mov %r7, 0x100
+ stw [%r6+0x1100], 0xfeedbeef
+
+ ldindw %r7, 0x0
+ fail_ne32 %r0, 0xfeedbeef
+
+ ;; half-word
+ sth [%r6+0x1104], 0x6789
+ ldindh %r7, 0x4
+ fail_ne32 %r0, 0x6789
+
+ ;; byte
+ stb [%r6+0x1108], 0x5f
+ ldindb %r7, 0x8
+ fail_ne32 %r0, 0x5f
+
+ ;; double-word
+ lddw %r2, 0xcafe12345678d00d
+ stxdw [%r6+0x1110], %r2
+ ldinddw %r7, 0x10
+ mov %r1, %r0
+ fail_ne %r1, 0xcafe12345678d00d
+
+ pass
diff --git a/sim/testsuite/sim/bpf/mem.s b/sim/testsuite/sim/bpf/mem.s
new file mode 100644
index 0000000000..2dea57d227
--- /dev/null
+++ b/sim/testsuite/sim/bpf/mem.s
@@ -0,0 +1,56 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;;; mem.s
+;;; Tests for BPF memory (ldx, stx, ..) instructions in simulator
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ lddw %r1, 0x1234deadbeef5678
+ mov %r2, 0x1000
+
+ ;; basic store/load check
+ stxb [%r2+0], %r1
+ stxh [%r2+2], %r1
+ stxw [%r2+4], %r1
+ stxdw [%r2+8], %r1
+
+ stb [%r2+16], 0x5a
+ sth [%r2+18], 0xcafe
+ stw [%r2+20], 0xbeefface
+ stdw [%r2+24], 0x7eadbeef
+
+ ldxb %r1, [%r2+16]
+ fail_ne %r1, 0x5a
+ ldxh %r1, [%r2+18]
+ fail_ne %r1, 0xffffffffffffcafe
+ ldxw %r1, [%r2+20]
+ fail_ne %r1, 0xffffffffbeefface
+ ldxdw %r1, [%r2+24]
+ fail_ne %r1, 0x7eadbeef
+
+ ldxb %r3, [%r2+0]
+ fail_ne %r3, 0x78
+ ldxh %r3, [%r2+2]
+ fail_ne %r3, 0x5678
+ ldxw %r3, [%r2+4]
+ fail_ne %r3, 0xffffffffbeef5678
+ ldxdw %r3, [%r2+8]
+ fail_ne %r3, 0x1234deadbeef5678
+
+ ldxw %r4, [%r2+10]
+ fail_ne %r4, 0xffffffffdeadbeef
+
+ ;; negative offsets
+ add %r2, 16
+ ldxh %r5, [%r2+-14]
+ fail_ne %r5, 0x5678
+ ldxw %r5, [%r2+-12]
+ fail_ne %r5, 0xffffffffbeef5678
+ ldxdw %r5, [%r2+-8]
+ fail_ne %r5, 0x1234deadbeef5678
+
+ pass
diff --git a/sim/testsuite/sim/bpf/mov.s b/sim/testsuite/sim/bpf/mov.s
new file mode 100644
index 0000000000..6665450468
--- /dev/null
+++ b/sim/testsuite/sim/bpf/mov.s
@@ -0,0 +1,54 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;; mov.s
+;; Tests for mov and mov32 instructions
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ ;; some basic sanity checks
+ mov32 %r1, 5
+ fail_ne %r1, 5
+
+ mov32 %r2, %r1
+ fail_ne %r2, 5
+
+ mov %r2, %r1
+ fail_ne %r2, 5
+
+ mov %r1, -666
+ fail_ne %r1, -666
+
+ ;; should NOT sign extend
+ mov32 %r1, -1
+ fail_ne %r1, 0x00000000ffffffff
+
+ ;; should sign extend
+ mov %r2, -1
+ fail_ne %r2, 0xffffffffffffffff
+
+ mov %r3, 0x80000000
+
+ ;; should NOT sign extend
+ mov32 %r4, %r3
+ fail_ne %r4, 0x0000000080000000
+
+ ;; should sign extend
+ mov %r5, %r3
+ fail_ne %r5, 0xffffffff80000000
+
+ mov32 %r1, -2147483648
+ mov32 %r1, %r1
+ fail_ne32 %r1, -2147483648
+
+ ;; casting shenanigans
+ mov %r1, %r1
+ fail_ne %r1, +2147483648
+ mov32 %r2, -1
+ mov %r2, %r2
+ fail_ne %r2, +4294967295
+
+ pass
diff --git a/sim/testsuite/sim/bpf/testutils.inc b/sim/testsuite/sim/bpf/testutils.inc
new file mode 100644
index 0000000000..d3d6b17b5b
--- /dev/null
+++ b/sim/testsuite/sim/bpf/testutils.inc
@@ -0,0 +1,38 @@
+
+ ;; Print "pass\n" and 'exit 0'
+ .macro pass
+ .data
+mpass:
+ .string "pass\n"
+ .text
+_pass:
+ mov %r1, mpass ; point to "pass\n" string
+ mov %r2, 5 ; strlen mpass
+ call 7 ; printk
+ mov %r0, 0 ;
+ exit ; exit 0
+ .endm
+
+;;; MACRO fail
+;;; Exit with status 1
+ .macro fail
+ mov %r0, 1
+ exit
+ .endm
+
+;;; MACRO fail_ne32
+;;; Exit with status 1 if \reg32 != \val
+ .macro fail_ne32 reg val
+ jeq32 \reg, \val, 2
+ mov %r0, 1
+ exit
+ .endm
+
+;;; MACRO fail_ne
+;;; Exit with status1 if \reg ne \val
+ .macro fail_ne reg val
+ lddw %r0, \val
+ jeq \reg, %r0, 2
+ mov %r0, 1
+ exit
+ .endm
diff --git a/sim/testsuite/sim/bpf/xadd.s b/sim/testsuite/sim/bpf/xadd.s
new file mode 100644
index 0000000000..1ca7577145
--- /dev/null
+++ b/sim/testsuite/sim/bpf/xadd.s
@@ -0,0 +1,44 @@
+# mach: bpf
+# output: pass\nexit 0 (0x0)\n
+;;; xadd.s
+;;; Tests for BPF atomic exchange-and-add instructions in simulator
+;;;
+;;; The xadd instructions (XADDW, XADDDW) operate on a memory location
+;;; specified in $dst + offset16, atomically adding the value in $src.
+;;;
+;;; In the simulator, there isn't anything else happening. The atomic
+;;; instructions are identical to a non-atomic load/add/store.
+
+ .include "testutils.inc"
+
+ .text
+ .global main
+ .type main, @function
+main:
+ mov %r1, 0x1000
+ mov %r2, 5
+
+ ;; basic xadd w
+ stw [%r1+0], 10
+ xaddw [%r1+0], %r2
+ ldxw %r3, [%r1+0]
+ fail_ne %r3, 15
+
+ ;; basic xadd dw
+ stdw [%r1+8], 42
+ xadddw [%r1+8], %r2
+ ldxdw %r3, [%r1+8]
+ fail_ne %r3, 47
+
+ ;; xadd w negative value
+ mov %r4, -1
+ xaddw [%r1+0], %r4
+ ldxw %r3, [%r1+0]
+ fail_ne %r3, 14
+
+ ;; xadd dw negative val
+ xadddw [%r1+8], %r4
+ ldxdw %r3, [%r1+8]
+ fail_ne %r3, 46
+
+ pass
--
2.25.0.2.g232378479e
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH V4 3/3] sim: generated files for the eBPF simulator
2020-07-10 12:25 [PATCH V4 0/3] eBPF support Jose E. Marchesi
2020-07-10 12:25 ` [PATCH V4 1/3] gdb: support for eBPF Jose E. Marchesi
2020-07-10 12:25 ` [PATCH V4 2/3] sim: eBPF simulator Jose E. Marchesi
@ 2020-07-10 12:25 ` Jose E. Marchesi
2 siblings, 0 replies; 10+ messages in thread
From: Jose E. Marchesi @ 2020-07-10 12:25 UTC (permalink / raw)
To: gdb-patches
This patch adds the autootools and CGEN generated files for the eBPF
simulator.
sim/ChangeLog:
2020-07-10 Jose E. Marchesi <jose.marchesi@oracle.com>
David Faust <david.faust@oracle.com>
* configure: Generate.
* bpf/arch.c: Likewise.
* bpf/arch.h: Likewise.
* bpf/cpu.c: Likewise.
* bpf/cpu.h: Likewise.
* bpf/cpuall.h: Likewise.
* bpf/decode-be.c: Likewise.
* bpf/decode-be.h: Likewise.
* bpf/decode-le.c: Likewise.
* bpf/decode-le.h: Likewise.
* bpf/decode.h: Likewise.
* bpf/defs-be.h: Likewise.
* bpf/defs-le.h: Likewise.
* bpf/sem-be.c: Likewise.
* bpf/sem-le.c: Likewise.
---
sim/ChangeLog | 19 +
sim/bpf/arch.c | 35 +
sim/bpf/arch.h | 50 +
sim/bpf/cpu.c | 69 +
sim/bpf/cpu.h | 81 ++
sim/bpf/cpuall.h | 65 +
sim/bpf/decode-be.c | 1129 +++++++++++++++
sim/bpf/decode-be.h | 94 ++
sim/bpf/decode-le.c | 1129 +++++++++++++++
sim/bpf/decode-le.h | 94 ++
sim/bpf/defs-be.h | 383 ++++++
sim/bpf/defs-le.h | 383 ++++++
sim/bpf/sem-be.c | 3207 +++++++++++++++++++++++++++++++++++++++++++
sim/bpf/sem-le.c | 3207 +++++++++++++++++++++++++++++++++++++++++++
14 files changed, 9945 insertions(+)
create mode 100644 sim/bpf/arch.c
create mode 100644 sim/bpf/arch.h
create mode 100644 sim/bpf/cpu.c
create mode 100644 sim/bpf/cpu.h
create mode 100644 sim/bpf/cpuall.h
create mode 100644 sim/bpf/decode-be.c
create mode 100644 sim/bpf/decode-be.h
create mode 100644 sim/bpf/decode-le.c
create mode 100644 sim/bpf/decode-le.h
create mode 100644 sim/bpf/defs-be.h
create mode 100644 sim/bpf/defs-le.h
create mode 100644 sim/bpf/sem-be.c
create mode 100644 sim/bpf/sem-le.c
diff --git a/sim/bpf/arch.c b/sim/bpf/arch.c
new file mode 100644
index 0000000000..d4b6d139c5
--- /dev/null
+++ b/sim/bpf/arch.c
@@ -0,0 +1,35 @@
+/* Simulator support for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const SIM_MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_BPFBF
+ & bpf_mach,
+#endif
+ 0
+};
+
diff --git a/sim/bpf/arch.h b/sim/bpf/arch.h
new file mode 100644
index 0000000000..734d65398f
--- /dev/null
+++ b/sim/bpf/arch.h
@@ -0,0 +1,50 @@
+/* Simulator header for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPF_ARCH_H
+#define BPF_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+#define WI DI
+#define UWI UDI
+#define AI UDI
+
+#define IAI UDI
+
+/* Enum declaration for model types. */
+typedef enum model_type {
+ MODEL_BPF_DEF, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types. */
+typedef enum unit_type {
+ UNIT_NONE, UNIT_BPF_DEF_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* BPF_ARCH_H */
diff --git a/sim/bpf/cpu.c b/sim/bpf/cpu.c
new file mode 100644
index 0000000000..c19de5d8e1
--- /dev/null
+++ b/sim/bpf/cpu.c
@@ -0,0 +1,69 @@
+/* Misc. support for CPU family bpfbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU bpfbf
+#define WANT_CPU_BPFBF
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-gpr. */
+
+DI
+bpfbf_h_gpr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_gpr[regno]);
+}
+
+/* Set a value for h-gpr. */
+
+void
+bpfbf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ CPU (h_gpr[regno]) = newval;
+}
+
+/* Get the value of h-pc. */
+
+UDI
+bpfbf_h_pc_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PC ();
+}
+
+/* Set a value for h-pc. */
+
+void
+bpfbf_h_pc_set (SIM_CPU *current_cpu, UDI newval)
+{
+ SET_H_PC (newval);
+}
+
+/* Record trace results for INSN. */
+
+void
+bpfbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
diff --git a/sim/bpf/cpu.h b/sim/bpf/cpu.h
new file mode 100644
index 0000000000..1e23fbeabf
--- /dev/null
+++ b/sim/bpf/cpu.h
@@ -0,0 +1,81 @@
+/* CPU family header for bpfbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef CPU_BPFBF_H
+#define CPU_BPFBF_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* The size of an "int" needed to hold an instruction word.
+ This is usually 32 bits, but some architectures needs 64 bits. */
+typedef CGEN_INSN_LGUINT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* General Purpose Registers */
+ DI h_gpr[16];
+#define GET_H_GPR(a1) CPU (h_gpr)[a1]
+#define SET_H_GPR(a1, x) (CPU (h_gpr)[a1] = (x))
+ /* program counter */
+ UDI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) \
+do { \
+CPU (h_pc) = (x);\
+;} while (0)
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} BPFBF_CPU_DATA;
+
+/* Cover fns for register access. */
+DI bpfbf_h_gpr_get (SIM_CPU *, UINT);
+void bpfbf_h_gpr_set (SIM_CPU *, UINT, DI);
+UDI bpfbf_h_pc_get (SIM_CPU *);
+void bpfbf_h_pc_set (SIM_CPU *, UDI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN bpfbf_fetch_register;
+extern CPUREG_STORE_FN bpfbf_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_BPF_DEF_DATA;
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_BPFBF_H */
diff --git a/sim/bpf/cpuall.h b/sim/bpf/cpuall.h
new file mode 100644
index 0000000000..3933dea353
--- /dev/null
+++ b/sim/bpf/cpuall.h
@@ -0,0 +1,65 @@
+/* Simulator CPU header for bpf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPF_CPUALL_H
+#define BPF_CPUALL_H
+
+/* Include files for each cpu family. */
+
+#ifdef WANT_CPU_BPFBF
+#include "eng.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const SIM_MACH bpf_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+#endif
+
+#endif /* BPF_CPUALL_H */
diff --git a/sim/bpf/decode-be.c b/sim/bpf/decode-be.c
new file mode 100644
index 0000000000..22d95ddec1
--- /dev/null
+++ b/sim/bpf/decode-be.c
@@ -0,0 +1,1129 @@
+/* Simulator instruction decoder for bpfbf_ebpfbe.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU bpfbf
+#define WANT_CPU_BPFBF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC bpfbf_ebpfbe_insn_data[BPFBF_EBPFBE_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem bpfbf_ebpfbe_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, BPFBF_EBPFBE_INSN_X_AFTER, BPFBF_EBPFBE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, BPFBF_EBPFBE_INSN_X_BEFORE, BPFBF_EBPFBE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, BPFBF_EBPFBE_INSN_X_CTI_CHAIN, BPFBF_EBPFBE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, BPFBF_EBPFBE_INSN_X_CHAIN, BPFBF_EBPFBE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, BPFBF_EBPFBE_INSN_X_BEGIN, BPFBF_EBPFBE_SFMT_EMPTY },
+ { BPF_INSN_ADDIBE, BPFBF_EBPFBE_INSN_ADDIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_ADDRBE, BPFBF_EBPFBE_INSN_ADDRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_ADD32IBE, BPFBF_EBPFBE_INSN_ADD32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_ADD32RBE, BPFBF_EBPFBE_INSN_ADD32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_SUBIBE, BPFBF_EBPFBE_INSN_SUBIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_SUBRBE, BPFBF_EBPFBE_INSN_SUBRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_SUB32IBE, BPFBF_EBPFBE_INSN_SUB32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_SUB32RBE, BPFBF_EBPFBE_INSN_SUB32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_MULIBE, BPFBF_EBPFBE_INSN_MULIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_MULRBE, BPFBF_EBPFBE_INSN_MULRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_MUL32IBE, BPFBF_EBPFBE_INSN_MUL32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_MUL32RBE, BPFBF_EBPFBE_INSN_MUL32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_DIVIBE, BPFBF_EBPFBE_INSN_DIVIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_DIVRBE, BPFBF_EBPFBE_INSN_DIVRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_DIV32IBE, BPFBF_EBPFBE_INSN_DIV32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_DIV32RBE, BPFBF_EBPFBE_INSN_DIV32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_ORIBE, BPFBF_EBPFBE_INSN_ORIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_ORRBE, BPFBF_EBPFBE_INSN_ORRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_OR32IBE, BPFBF_EBPFBE_INSN_OR32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_OR32RBE, BPFBF_EBPFBE_INSN_OR32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_ANDIBE, BPFBF_EBPFBE_INSN_ANDIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_ANDRBE, BPFBF_EBPFBE_INSN_ANDRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_AND32IBE, BPFBF_EBPFBE_INSN_AND32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_AND32RBE, BPFBF_EBPFBE_INSN_AND32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_LSHIBE, BPFBF_EBPFBE_INSN_LSHIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_LSHRBE, BPFBF_EBPFBE_INSN_LSHRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_LSH32IBE, BPFBF_EBPFBE_INSN_LSH32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_LSH32RBE, BPFBF_EBPFBE_INSN_LSH32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_RSHIBE, BPFBF_EBPFBE_INSN_RSHIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_RSHRBE, BPFBF_EBPFBE_INSN_RSHRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_RSH32IBE, BPFBF_EBPFBE_INSN_RSH32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_RSH32RBE, BPFBF_EBPFBE_INSN_RSH32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_MODIBE, BPFBF_EBPFBE_INSN_MODIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_MODRBE, BPFBF_EBPFBE_INSN_MODRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_MOD32IBE, BPFBF_EBPFBE_INSN_MOD32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_MOD32RBE, BPFBF_EBPFBE_INSN_MOD32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_XORIBE, BPFBF_EBPFBE_INSN_XORIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_XORRBE, BPFBF_EBPFBE_INSN_XORRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_XOR32IBE, BPFBF_EBPFBE_INSN_XOR32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_XOR32RBE, BPFBF_EBPFBE_INSN_XOR32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_ARSHIBE, BPFBF_EBPFBE_INSN_ARSHIBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_ARSHRBE, BPFBF_EBPFBE_INSN_ARSHRBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_ARSH32IBE, BPFBF_EBPFBE_INSN_ARSH32IBE, BPFBF_EBPFBE_SFMT_ADDIBE },
+ { BPF_INSN_ARSH32RBE, BPFBF_EBPFBE_INSN_ARSH32RBE, BPFBF_EBPFBE_SFMT_ADDRBE },
+ { BPF_INSN_NEGBE, BPFBF_EBPFBE_INSN_NEGBE, BPFBF_EBPFBE_SFMT_NEGBE },
+ { BPF_INSN_NEG32BE, BPFBF_EBPFBE_INSN_NEG32BE, BPFBF_EBPFBE_SFMT_NEGBE },
+ { BPF_INSN_MOVIBE, BPFBF_EBPFBE_INSN_MOVIBE, BPFBF_EBPFBE_SFMT_MOVIBE },
+ { BPF_INSN_MOVRBE, BPFBF_EBPFBE_INSN_MOVRBE, BPFBF_EBPFBE_SFMT_MOVRBE },
+ { BPF_INSN_MOV32IBE, BPFBF_EBPFBE_INSN_MOV32IBE, BPFBF_EBPFBE_SFMT_MOVIBE },
+ { BPF_INSN_MOV32RBE, BPFBF_EBPFBE_INSN_MOV32RBE, BPFBF_EBPFBE_SFMT_MOVRBE },
+ { BPF_INSN_ENDLEBE, BPFBF_EBPFBE_INSN_ENDLEBE, BPFBF_EBPFBE_SFMT_ENDLEBE },
+ { BPF_INSN_ENDBEBE, BPFBF_EBPFBE_INSN_ENDBEBE, BPFBF_EBPFBE_SFMT_ENDLEBE },
+ { BPF_INSN_LDDWBE, BPFBF_EBPFBE_INSN_LDDWBE, BPFBF_EBPFBE_SFMT_LDDWBE },
+ { BPF_INSN_LDABSW, BPFBF_EBPFBE_INSN_LDABSW, BPFBF_EBPFBE_SFMT_LDABSW },
+ { BPF_INSN_LDABSH, BPFBF_EBPFBE_INSN_LDABSH, BPFBF_EBPFBE_SFMT_LDABSH },
+ { BPF_INSN_LDABSB, BPFBF_EBPFBE_INSN_LDABSB, BPFBF_EBPFBE_SFMT_LDABSB },
+ { BPF_INSN_LDABSDW, BPFBF_EBPFBE_INSN_LDABSDW, BPFBF_EBPFBE_SFMT_LDABSDW },
+ { BPF_INSN_LDINDWBE, BPFBF_EBPFBE_INSN_LDINDWBE, BPFBF_EBPFBE_SFMT_LDINDWBE },
+ { BPF_INSN_LDINDHBE, BPFBF_EBPFBE_INSN_LDINDHBE, BPFBF_EBPFBE_SFMT_LDINDHBE },
+ { BPF_INSN_LDINDBBE, BPFBF_EBPFBE_INSN_LDINDBBE, BPFBF_EBPFBE_SFMT_LDINDBBE },
+ { BPF_INSN_LDINDDWBE, BPFBF_EBPFBE_INSN_LDINDDWBE, BPFBF_EBPFBE_SFMT_LDINDDWBE },
+ { BPF_INSN_LDXWBE, BPFBF_EBPFBE_INSN_LDXWBE, BPFBF_EBPFBE_SFMT_LDXWBE },
+ { BPF_INSN_LDXHBE, BPFBF_EBPFBE_INSN_LDXHBE, BPFBF_EBPFBE_SFMT_LDXHBE },
+ { BPF_INSN_LDXBBE, BPFBF_EBPFBE_INSN_LDXBBE, BPFBF_EBPFBE_SFMT_LDXBBE },
+ { BPF_INSN_LDXDWBE, BPFBF_EBPFBE_INSN_LDXDWBE, BPFBF_EBPFBE_SFMT_LDXDWBE },
+ { BPF_INSN_STXWBE, BPFBF_EBPFBE_INSN_STXWBE, BPFBF_EBPFBE_SFMT_STXWBE },
+ { BPF_INSN_STXHBE, BPFBF_EBPFBE_INSN_STXHBE, BPFBF_EBPFBE_SFMT_STXHBE },
+ { BPF_INSN_STXBBE, BPFBF_EBPFBE_INSN_STXBBE, BPFBF_EBPFBE_SFMT_STXBBE },
+ { BPF_INSN_STXDWBE, BPFBF_EBPFBE_INSN_STXDWBE, BPFBF_EBPFBE_SFMT_STXDWBE },
+ { BPF_INSN_STBBE, BPFBF_EBPFBE_INSN_STBBE, BPFBF_EBPFBE_SFMT_STBBE },
+ { BPF_INSN_STHBE, BPFBF_EBPFBE_INSN_STHBE, BPFBF_EBPFBE_SFMT_STHBE },
+ { BPF_INSN_STWBE, BPFBF_EBPFBE_INSN_STWBE, BPFBF_EBPFBE_SFMT_STWBE },
+ { BPF_INSN_STDWBE, BPFBF_EBPFBE_INSN_STDWBE, BPFBF_EBPFBE_SFMT_STDWBE },
+ { BPF_INSN_JEQIBE, BPFBF_EBPFBE_INSN_JEQIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JEQRBE, BPFBF_EBPFBE_INSN_JEQRBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JEQ32IBE, BPFBF_EBPFBE_INSN_JEQ32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JEQ32RBE, BPFBF_EBPFBE_INSN_JEQ32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JGTIBE, BPFBF_EBPFBE_INSN_JGTIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JGTRBE, BPFBF_EBPFBE_INSN_JGTRBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JGT32IBE, BPFBF_EBPFBE_INSN_JGT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JGT32RBE, BPFBF_EBPFBE_INSN_JGT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JGEIBE, BPFBF_EBPFBE_INSN_JGEIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JGERBE, BPFBF_EBPFBE_INSN_JGERBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JGE32IBE, BPFBF_EBPFBE_INSN_JGE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JGE32RBE, BPFBF_EBPFBE_INSN_JGE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JLTIBE, BPFBF_EBPFBE_INSN_JLTIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JLTRBE, BPFBF_EBPFBE_INSN_JLTRBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JLT32IBE, BPFBF_EBPFBE_INSN_JLT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JLT32RBE, BPFBF_EBPFBE_INSN_JLT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JLEIBE, BPFBF_EBPFBE_INSN_JLEIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JLERBE, BPFBF_EBPFBE_INSN_JLERBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JLE32IBE, BPFBF_EBPFBE_INSN_JLE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JLE32RBE, BPFBF_EBPFBE_INSN_JLE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSETIBE, BPFBF_EBPFBE_INSN_JSETIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSETRBE, BPFBF_EBPFBE_INSN_JSETRBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSET32IBE, BPFBF_EBPFBE_INSN_JSET32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSET32RBE, BPFBF_EBPFBE_INSN_JSET32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JNEIBE, BPFBF_EBPFBE_INSN_JNEIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JNERBE, BPFBF_EBPFBE_INSN_JNERBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JNE32IBE, BPFBF_EBPFBE_INSN_JNE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JNE32RBE, BPFBF_EBPFBE_INSN_JNE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSGTIBE, BPFBF_EBPFBE_INSN_JSGTIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSGTRBE, BPFBF_EBPFBE_INSN_JSGTRBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSGT32IBE, BPFBF_EBPFBE_INSN_JSGT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSGT32RBE, BPFBF_EBPFBE_INSN_JSGT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSGEIBE, BPFBF_EBPFBE_INSN_JSGEIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSGERBE, BPFBF_EBPFBE_INSN_JSGERBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSGE32IBE, BPFBF_EBPFBE_INSN_JSGE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSGE32RBE, BPFBF_EBPFBE_INSN_JSGE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSLTIBE, BPFBF_EBPFBE_INSN_JSLTIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSLTRBE, BPFBF_EBPFBE_INSN_JSLTRBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSLT32IBE, BPFBF_EBPFBE_INSN_JSLT32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSLT32RBE, BPFBF_EBPFBE_INSN_JSLT32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSLEIBE, BPFBF_EBPFBE_INSN_JSLEIBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSLERBE, BPFBF_EBPFBE_INSN_JSLERBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_JSLE32IBE, BPFBF_EBPFBE_INSN_JSLE32IBE, BPFBF_EBPFBE_SFMT_JEQIBE },
+ { BPF_INSN_JSLE32RBE, BPFBF_EBPFBE_INSN_JSLE32RBE, BPFBF_EBPFBE_SFMT_JEQRBE },
+ { BPF_INSN_CALLBE, BPFBF_EBPFBE_INSN_CALLBE, BPFBF_EBPFBE_SFMT_CALLBE },
+ { BPF_INSN_JA, BPFBF_EBPFBE_INSN_JA, BPFBF_EBPFBE_SFMT_JA },
+ { BPF_INSN_EXIT, BPFBF_EBPFBE_INSN_EXIT, BPFBF_EBPFBE_SFMT_EXIT },
+ { BPF_INSN_XADDDWBE, BPFBF_EBPFBE_INSN_XADDDWBE, BPFBF_EBPFBE_SFMT_XADDDWBE },
+ { BPF_INSN_XADDWBE, BPFBF_EBPFBE_INSN_XADDWBE, BPFBF_EBPFBE_SFMT_XADDWBE },
+ { BPF_INSN_BRKPT, BPFBF_EBPFBE_INSN_BRKPT, BPFBF_EBPFBE_SFMT_EXIT },
+};
+
+static const struct insn_sem bpfbf_ebpfbe_insn_sem_invalid =
+{
+ VIRTUAL_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+bpfbf_ebpfbe_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = BPFBF_EBPFBE_INSN__MAX;
+ IDESC *table = bpfbf_ebpfbe_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & bpfbf_ebpfbe_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = bpfbf_ebpfbe_insn_sem, tend = t + sizeof (bpfbf_ebpfbe_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+bpfbf_ebpfbe_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_WORD base_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ BPFBF_EBPFBE_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_WORD insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 0) & (255 << 0)));
+ switch (val)
+ {
+ case 4 : itype = BPFBF_EBPFBE_INSN_ADD32IBE; goto extract_sfmt_addibe;
+ case 5 : itype = BPFBF_EBPFBE_INSN_JA; goto extract_sfmt_ja;
+ case 7 : itype = BPFBF_EBPFBE_INSN_ADDIBE; goto extract_sfmt_addibe;
+ case 12 : itype = BPFBF_EBPFBE_INSN_ADD32RBE; goto extract_sfmt_addrbe;
+ case 15 : itype = BPFBF_EBPFBE_INSN_ADDRBE; goto extract_sfmt_addrbe;
+ case 20 : itype = BPFBF_EBPFBE_INSN_SUB32IBE; goto extract_sfmt_addibe;
+ case 21 : itype = BPFBF_EBPFBE_INSN_JEQIBE; goto extract_sfmt_jeqibe;
+ case 22 : itype = BPFBF_EBPFBE_INSN_JEQ32IBE; goto extract_sfmt_jeqibe;
+ case 23 : itype = BPFBF_EBPFBE_INSN_SUBIBE; goto extract_sfmt_addibe;
+ case 24 : itype = BPFBF_EBPFBE_INSN_LDDWBE; goto extract_sfmt_lddwbe;
+ case 28 : itype = BPFBF_EBPFBE_INSN_SUB32RBE; goto extract_sfmt_addrbe;
+ case 29 : itype = BPFBF_EBPFBE_INSN_JEQRBE; goto extract_sfmt_jeqrbe;
+ case 30 : itype = BPFBF_EBPFBE_INSN_JEQ32RBE; goto extract_sfmt_jeqrbe;
+ case 31 : itype = BPFBF_EBPFBE_INSN_SUBRBE; goto extract_sfmt_addrbe;
+ case 32 : itype = BPFBF_EBPFBE_INSN_LDABSW; goto extract_sfmt_ldabsw;
+ case 36 : itype = BPFBF_EBPFBE_INSN_MUL32IBE; goto extract_sfmt_addibe;
+ case 37 : itype = BPFBF_EBPFBE_INSN_JGTIBE; goto extract_sfmt_jeqibe;
+ case 38 : itype = BPFBF_EBPFBE_INSN_JGT32IBE; goto extract_sfmt_jeqibe;
+ case 39 : itype = BPFBF_EBPFBE_INSN_MULIBE; goto extract_sfmt_addibe;
+ case 40 : itype = BPFBF_EBPFBE_INSN_LDABSH; goto extract_sfmt_ldabsh;
+ case 44 : itype = BPFBF_EBPFBE_INSN_MUL32RBE; goto extract_sfmt_addrbe;
+ case 45 : itype = BPFBF_EBPFBE_INSN_JGTRBE; goto extract_sfmt_jeqrbe;
+ case 46 : itype = BPFBF_EBPFBE_INSN_JGT32RBE; goto extract_sfmt_jeqrbe;
+ case 47 : itype = BPFBF_EBPFBE_INSN_MULRBE; goto extract_sfmt_addrbe;
+ case 48 : itype = BPFBF_EBPFBE_INSN_LDABSB; goto extract_sfmt_ldabsb;
+ case 52 : itype = BPFBF_EBPFBE_INSN_DIV32IBE; goto extract_sfmt_addibe;
+ case 53 : itype = BPFBF_EBPFBE_INSN_JGEIBE; goto extract_sfmt_jeqibe;
+ case 54 : itype = BPFBF_EBPFBE_INSN_JGE32IBE; goto extract_sfmt_jeqibe;
+ case 55 : itype = BPFBF_EBPFBE_INSN_DIVIBE; goto extract_sfmt_addibe;
+ case 56 : itype = BPFBF_EBPFBE_INSN_LDABSDW; goto extract_sfmt_ldabsdw;
+ case 60 : itype = BPFBF_EBPFBE_INSN_DIV32RBE; goto extract_sfmt_addrbe;
+ case 61 : itype = BPFBF_EBPFBE_INSN_JGERBE; goto extract_sfmt_jeqrbe;
+ case 62 : itype = BPFBF_EBPFBE_INSN_JGE32RBE; goto extract_sfmt_jeqrbe;
+ case 63 : itype = BPFBF_EBPFBE_INSN_DIVRBE; goto extract_sfmt_addrbe;
+ case 64 : itype = BPFBF_EBPFBE_INSN_LDINDWBE; goto extract_sfmt_ldindwbe;
+ case 68 : itype = BPFBF_EBPFBE_INSN_OR32IBE; goto extract_sfmt_addibe;
+ case 69 : itype = BPFBF_EBPFBE_INSN_JSETIBE; goto extract_sfmt_jeqibe;
+ case 70 : itype = BPFBF_EBPFBE_INSN_JSET32IBE; goto extract_sfmt_jeqibe;
+ case 71 : itype = BPFBF_EBPFBE_INSN_ORIBE; goto extract_sfmt_addibe;
+ case 72 : itype = BPFBF_EBPFBE_INSN_LDINDHBE; goto extract_sfmt_ldindhbe;
+ case 76 : itype = BPFBF_EBPFBE_INSN_OR32RBE; goto extract_sfmt_addrbe;
+ case 77 : itype = BPFBF_EBPFBE_INSN_JSETRBE; goto extract_sfmt_jeqrbe;
+ case 78 : itype = BPFBF_EBPFBE_INSN_JSET32RBE; goto extract_sfmt_jeqrbe;
+ case 79 : itype = BPFBF_EBPFBE_INSN_ORRBE; goto extract_sfmt_addrbe;
+ case 80 : itype = BPFBF_EBPFBE_INSN_LDINDBBE; goto extract_sfmt_ldindbbe;
+ case 84 : itype = BPFBF_EBPFBE_INSN_AND32IBE; goto extract_sfmt_addibe;
+ case 85 : itype = BPFBF_EBPFBE_INSN_JNEIBE; goto extract_sfmt_jeqibe;
+ case 86 : itype = BPFBF_EBPFBE_INSN_JNE32IBE; goto extract_sfmt_jeqibe;
+ case 87 : itype = BPFBF_EBPFBE_INSN_ANDIBE; goto extract_sfmt_addibe;
+ case 88 : itype = BPFBF_EBPFBE_INSN_LDINDDWBE; goto extract_sfmt_ldinddwbe;
+ case 92 : itype = BPFBF_EBPFBE_INSN_AND32RBE; goto extract_sfmt_addrbe;
+ case 93 : itype = BPFBF_EBPFBE_INSN_JNERBE; goto extract_sfmt_jeqrbe;
+ case 94 : itype = BPFBF_EBPFBE_INSN_JNE32RBE; goto extract_sfmt_jeqrbe;
+ case 95 : itype = BPFBF_EBPFBE_INSN_ANDRBE; goto extract_sfmt_addrbe;
+ case 97 : itype = BPFBF_EBPFBE_INSN_LDXWBE; goto extract_sfmt_ldxwbe;
+ case 98 : itype = BPFBF_EBPFBE_INSN_STWBE; goto extract_sfmt_stwbe;
+ case 99 : itype = BPFBF_EBPFBE_INSN_STXWBE; goto extract_sfmt_stxwbe;
+ case 100 : itype = BPFBF_EBPFBE_INSN_LSH32IBE; goto extract_sfmt_addibe;
+ case 101 : itype = BPFBF_EBPFBE_INSN_JSGTIBE; goto extract_sfmt_jeqibe;
+ case 102 : itype = BPFBF_EBPFBE_INSN_JSGT32IBE; goto extract_sfmt_jeqibe;
+ case 103 : itype = BPFBF_EBPFBE_INSN_LSHIBE; goto extract_sfmt_addibe;
+ case 105 : itype = BPFBF_EBPFBE_INSN_LDXHBE; goto extract_sfmt_ldxhbe;
+ case 106 : itype = BPFBF_EBPFBE_INSN_STHBE; goto extract_sfmt_sthbe;
+ case 107 : itype = BPFBF_EBPFBE_INSN_STXHBE; goto extract_sfmt_stxhbe;
+ case 108 : itype = BPFBF_EBPFBE_INSN_LSH32RBE; goto extract_sfmt_addrbe;
+ case 109 : itype = BPFBF_EBPFBE_INSN_JSGTRBE; goto extract_sfmt_jeqrbe;
+ case 110 : itype = BPFBF_EBPFBE_INSN_JSGT32RBE; goto extract_sfmt_jeqrbe;
+ case 111 : itype = BPFBF_EBPFBE_INSN_LSHRBE; goto extract_sfmt_addrbe;
+ case 113 : itype = BPFBF_EBPFBE_INSN_LDXBBE; goto extract_sfmt_ldxbbe;
+ case 114 : itype = BPFBF_EBPFBE_INSN_STBBE; goto extract_sfmt_stbbe;
+ case 115 : itype = BPFBF_EBPFBE_INSN_STXBBE; goto extract_sfmt_stxbbe;
+ case 116 : itype = BPFBF_EBPFBE_INSN_RSH32IBE; goto extract_sfmt_addibe;
+ case 117 : itype = BPFBF_EBPFBE_INSN_JSGEIBE; goto extract_sfmt_jeqibe;
+ case 118 : itype = BPFBF_EBPFBE_INSN_JSGE32IBE; goto extract_sfmt_jeqibe;
+ case 119 : itype = BPFBF_EBPFBE_INSN_RSHIBE; goto extract_sfmt_addibe;
+ case 121 : itype = BPFBF_EBPFBE_INSN_LDXDWBE; goto extract_sfmt_ldxdwbe;
+ case 122 : itype = BPFBF_EBPFBE_INSN_STDWBE; goto extract_sfmt_stdwbe;
+ case 123 : itype = BPFBF_EBPFBE_INSN_STXDWBE; goto extract_sfmt_stxdwbe;
+ case 124 : itype = BPFBF_EBPFBE_INSN_RSH32RBE; goto extract_sfmt_addrbe;
+ case 125 : itype = BPFBF_EBPFBE_INSN_JSGERBE; goto extract_sfmt_jeqrbe;
+ case 126 : itype = BPFBF_EBPFBE_INSN_JSGE32RBE; goto extract_sfmt_jeqrbe;
+ case 127 : itype = BPFBF_EBPFBE_INSN_RSHRBE; goto extract_sfmt_addrbe;
+ case 132 : itype = BPFBF_EBPFBE_INSN_NEG32BE; goto extract_sfmt_negbe;
+ case 133 : itype = BPFBF_EBPFBE_INSN_CALLBE; goto extract_sfmt_callbe;
+ case 135 : itype = BPFBF_EBPFBE_INSN_NEGBE; goto extract_sfmt_negbe;
+ case 140 : itype = BPFBF_EBPFBE_INSN_BRKPT; goto extract_sfmt_exit;
+ case 148 : itype = BPFBF_EBPFBE_INSN_MOD32IBE; goto extract_sfmt_addibe;
+ case 149 : itype = BPFBF_EBPFBE_INSN_EXIT; goto extract_sfmt_exit;
+ case 151 : itype = BPFBF_EBPFBE_INSN_MODIBE; goto extract_sfmt_addibe;
+ case 156 : itype = BPFBF_EBPFBE_INSN_MOD32RBE; goto extract_sfmt_addrbe;
+ case 159 : itype = BPFBF_EBPFBE_INSN_MODRBE; goto extract_sfmt_addrbe;
+ case 164 : itype = BPFBF_EBPFBE_INSN_XOR32IBE; goto extract_sfmt_addibe;
+ case 165 : itype = BPFBF_EBPFBE_INSN_JLTIBE; goto extract_sfmt_jeqibe;
+ case 166 : itype = BPFBF_EBPFBE_INSN_JLT32IBE; goto extract_sfmt_jeqibe;
+ case 167 : itype = BPFBF_EBPFBE_INSN_XORIBE; goto extract_sfmt_addibe;
+ case 172 : itype = BPFBF_EBPFBE_INSN_XOR32RBE; goto extract_sfmt_addrbe;
+ case 173 : itype = BPFBF_EBPFBE_INSN_JLTRBE; goto extract_sfmt_jeqrbe;
+ case 174 : itype = BPFBF_EBPFBE_INSN_JLT32RBE; goto extract_sfmt_jeqrbe;
+ case 175 : itype = BPFBF_EBPFBE_INSN_XORRBE; goto extract_sfmt_addrbe;
+ case 180 : itype = BPFBF_EBPFBE_INSN_MOV32IBE; goto extract_sfmt_movibe;
+ case 181 : itype = BPFBF_EBPFBE_INSN_JLEIBE; goto extract_sfmt_jeqibe;
+ case 182 : itype = BPFBF_EBPFBE_INSN_JLE32IBE; goto extract_sfmt_jeqibe;
+ case 183 : itype = BPFBF_EBPFBE_INSN_MOVIBE; goto extract_sfmt_movibe;
+ case 188 : itype = BPFBF_EBPFBE_INSN_MOV32RBE; goto extract_sfmt_movrbe;
+ case 189 : itype = BPFBF_EBPFBE_INSN_JLERBE; goto extract_sfmt_jeqrbe;
+ case 190 : itype = BPFBF_EBPFBE_INSN_JLE32RBE; goto extract_sfmt_jeqrbe;
+ case 191 : itype = BPFBF_EBPFBE_INSN_MOVRBE; goto extract_sfmt_movrbe;
+ case 195 : itype = BPFBF_EBPFBE_INSN_XADDWBE; goto extract_sfmt_xaddwbe;
+ case 196 : itype = BPFBF_EBPFBE_INSN_ARSH32IBE; goto extract_sfmt_addibe;
+ case 197 : itype = BPFBF_EBPFBE_INSN_JSLTIBE; goto extract_sfmt_jeqibe;
+ case 198 : itype = BPFBF_EBPFBE_INSN_JSLT32IBE; goto extract_sfmt_jeqibe;
+ case 199 : itype = BPFBF_EBPFBE_INSN_ARSHIBE; goto extract_sfmt_addibe;
+ case 204 : itype = BPFBF_EBPFBE_INSN_ARSH32RBE; goto extract_sfmt_addrbe;
+ case 205 : itype = BPFBF_EBPFBE_INSN_JSLTRBE; goto extract_sfmt_jeqrbe;
+ case 206 : itype = BPFBF_EBPFBE_INSN_JSLT32RBE; goto extract_sfmt_jeqrbe;
+ case 207 : itype = BPFBF_EBPFBE_INSN_ARSHRBE; goto extract_sfmt_addrbe;
+ case 212 : itype = BPFBF_EBPFBE_INSN_ENDLEBE; goto extract_sfmt_endlebe;
+ case 213 : itype = BPFBF_EBPFBE_INSN_JSLEIBE; goto extract_sfmt_jeqibe;
+ case 214 : itype = BPFBF_EBPFBE_INSN_JSLE32IBE; goto extract_sfmt_jeqibe;
+ case 219 : itype = BPFBF_EBPFBE_INSN_XADDDWBE; goto extract_sfmt_xadddwbe;
+ case 220 : itype = BPFBF_EBPFBE_INSN_ENDBEBE; goto extract_sfmt_endlebe;
+ case 221 : itype = BPFBF_EBPFBE_INSN_JSLERBE; goto extract_sfmt_jeqrbe;
+ case 222 : itype = BPFBF_EBPFBE_INSN_JSLE32RBE; goto extract_sfmt_jeqrbe;
+ default : itype = BPFBF_EBPFBE_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addibe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addibe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addrbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addrbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_negbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_lddwbe.f
+ UINT f_dstbe;
+
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negbe", "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movibe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movibe", "f_imm32 0x%x", 'x', f_imm32, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movrbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_srcbe) = f_srcbe;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movrbe", "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_endlebe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_endlebe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lddwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_lddwbe.f
+ UINT f_imm64_c;
+ UINT f_imm64_b;
+ UINT f_imm64_a;
+ UINT f_dstbe;
+ DI f_imm64;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+ UINT word_2;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 8);
+ word_2 = GETIMEMUSI (current_cpu, pc + 12);
+ f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0));
+ f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+{
+ f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm64) = f_imm64;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddwbe", "f_imm64 0x%x", 'x', f_imm64, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsw:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsh:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsh", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsb:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsb", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsdw:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsdw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldindwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+ UINT f_srcbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindwbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldindhbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+ UINT f_srcbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindhbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldindbbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+ UINT f_srcbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindbbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldinddwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+ UINT f_srcbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldinddwbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxwbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxhbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxhbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxbbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxbbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxdwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ FLD (f_dstbe) = f_dstbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxdwbe", "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, "f_dstbe 0x%x", 'x', f_dstbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxhbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxhbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxbbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxbbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxdwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxdwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stbbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stbbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sthbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stdwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jeqibe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqibe", "f_offset16 0x%x", 'x', f_offset16, "f_dstbe 0x%x", 'x', f_dstbe, "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jeqrbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqrbe", "f_offset16 0x%x", 'x', f_offset16, "f_dstbe 0x%x", 'x', f_dstbe, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_callbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ INT f_imm32;
+ UINT f_srcbe;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callbe", "f_imm32 0x%x", 'x', f_imm32, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ja:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ HI f_offset16;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ja", "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_exit:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_exit", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_xadddwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xadddwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_xaddwbe:
+ {
+ const IDESC *idesc = &bpfbf_ebpfbe_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ HI f_offset16;
+ UINT f_dstbe;
+ UINT f_srcbe;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstbe) = f_dstbe;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcbe) = f_srcbe;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xaddwbe", "f_dstbe 0x%x", 'x', f_dstbe, "f_offset16 0x%x", 'x', f_offset16, "f_srcbe 0x%x", 'x', f_srcbe, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+}
diff --git a/sim/bpf/decode-be.h b/sim/bpf/decode-be.h
new file mode 100644
index 0000000000..431d7c605c
--- /dev/null
+++ b/sim/bpf/decode-be.h
@@ -0,0 +1,94 @@
+/* Decode header for bpfbf_ebpfbe.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPFBF_EBPFBE_DECODE_H
+#define BPFBF_EBPFBE_DECODE_H
+
+extern const IDESC *bpfbf_ebpfbe_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_WORD,
+ ARGBUF *);
+extern void bpfbf_ebpfbe_init_idesc_table (SIM_CPU *);
+extern void bpfbf_ebpfbe_sem_init_idesc_table (SIM_CPU *);
+extern void bpfbf_ebpfbe_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family bpfbf. */
+typedef enum bpfbf_ebpfbe_insn_type {
+ BPFBF_EBPFBE_INSN_X_INVALID, BPFBF_EBPFBE_INSN_X_AFTER, BPFBF_EBPFBE_INSN_X_BEFORE, BPFBF_EBPFBE_INSN_X_CTI_CHAIN
+ , BPFBF_EBPFBE_INSN_X_CHAIN, BPFBF_EBPFBE_INSN_X_BEGIN, BPFBF_EBPFBE_INSN_ADDIBE, BPFBF_EBPFBE_INSN_ADDRBE
+ , BPFBF_EBPFBE_INSN_ADD32IBE, BPFBF_EBPFBE_INSN_ADD32RBE, BPFBF_EBPFBE_INSN_SUBIBE, BPFBF_EBPFBE_INSN_SUBRBE
+ , BPFBF_EBPFBE_INSN_SUB32IBE, BPFBF_EBPFBE_INSN_SUB32RBE, BPFBF_EBPFBE_INSN_MULIBE, BPFBF_EBPFBE_INSN_MULRBE
+ , BPFBF_EBPFBE_INSN_MUL32IBE, BPFBF_EBPFBE_INSN_MUL32RBE, BPFBF_EBPFBE_INSN_DIVIBE, BPFBF_EBPFBE_INSN_DIVRBE
+ , BPFBF_EBPFBE_INSN_DIV32IBE, BPFBF_EBPFBE_INSN_DIV32RBE, BPFBF_EBPFBE_INSN_ORIBE, BPFBF_EBPFBE_INSN_ORRBE
+ , BPFBF_EBPFBE_INSN_OR32IBE, BPFBF_EBPFBE_INSN_OR32RBE, BPFBF_EBPFBE_INSN_ANDIBE, BPFBF_EBPFBE_INSN_ANDRBE
+ , BPFBF_EBPFBE_INSN_AND32IBE, BPFBF_EBPFBE_INSN_AND32RBE, BPFBF_EBPFBE_INSN_LSHIBE, BPFBF_EBPFBE_INSN_LSHRBE
+ , BPFBF_EBPFBE_INSN_LSH32IBE, BPFBF_EBPFBE_INSN_LSH32RBE, BPFBF_EBPFBE_INSN_RSHIBE, BPFBF_EBPFBE_INSN_RSHRBE
+ , BPFBF_EBPFBE_INSN_RSH32IBE, BPFBF_EBPFBE_INSN_RSH32RBE, BPFBF_EBPFBE_INSN_MODIBE, BPFBF_EBPFBE_INSN_MODRBE
+ , BPFBF_EBPFBE_INSN_MOD32IBE, BPFBF_EBPFBE_INSN_MOD32RBE, BPFBF_EBPFBE_INSN_XORIBE, BPFBF_EBPFBE_INSN_XORRBE
+ , BPFBF_EBPFBE_INSN_XOR32IBE, BPFBF_EBPFBE_INSN_XOR32RBE, BPFBF_EBPFBE_INSN_ARSHIBE, BPFBF_EBPFBE_INSN_ARSHRBE
+ , BPFBF_EBPFBE_INSN_ARSH32IBE, BPFBF_EBPFBE_INSN_ARSH32RBE, BPFBF_EBPFBE_INSN_NEGBE, BPFBF_EBPFBE_INSN_NEG32BE
+ , BPFBF_EBPFBE_INSN_MOVIBE, BPFBF_EBPFBE_INSN_MOVRBE, BPFBF_EBPFBE_INSN_MOV32IBE, BPFBF_EBPFBE_INSN_MOV32RBE
+ , BPFBF_EBPFBE_INSN_ENDLEBE, BPFBF_EBPFBE_INSN_ENDBEBE, BPFBF_EBPFBE_INSN_LDDWBE, BPFBF_EBPFBE_INSN_LDABSW
+ , BPFBF_EBPFBE_INSN_LDABSH, BPFBF_EBPFBE_INSN_LDABSB, BPFBF_EBPFBE_INSN_LDABSDW, BPFBF_EBPFBE_INSN_LDINDWBE
+ , BPFBF_EBPFBE_INSN_LDINDHBE, BPFBF_EBPFBE_INSN_LDINDBBE, BPFBF_EBPFBE_INSN_LDINDDWBE, BPFBF_EBPFBE_INSN_LDXWBE
+ , BPFBF_EBPFBE_INSN_LDXHBE, BPFBF_EBPFBE_INSN_LDXBBE, BPFBF_EBPFBE_INSN_LDXDWBE, BPFBF_EBPFBE_INSN_STXWBE
+ , BPFBF_EBPFBE_INSN_STXHBE, BPFBF_EBPFBE_INSN_STXBBE, BPFBF_EBPFBE_INSN_STXDWBE, BPFBF_EBPFBE_INSN_STBBE
+ , BPFBF_EBPFBE_INSN_STHBE, BPFBF_EBPFBE_INSN_STWBE, BPFBF_EBPFBE_INSN_STDWBE, BPFBF_EBPFBE_INSN_JEQIBE
+ , BPFBF_EBPFBE_INSN_JEQRBE, BPFBF_EBPFBE_INSN_JEQ32IBE, BPFBF_EBPFBE_INSN_JEQ32RBE, BPFBF_EBPFBE_INSN_JGTIBE
+ , BPFBF_EBPFBE_INSN_JGTRBE, BPFBF_EBPFBE_INSN_JGT32IBE, BPFBF_EBPFBE_INSN_JGT32RBE, BPFBF_EBPFBE_INSN_JGEIBE
+ , BPFBF_EBPFBE_INSN_JGERBE, BPFBF_EBPFBE_INSN_JGE32IBE, BPFBF_EBPFBE_INSN_JGE32RBE, BPFBF_EBPFBE_INSN_JLTIBE
+ , BPFBF_EBPFBE_INSN_JLTRBE, BPFBF_EBPFBE_INSN_JLT32IBE, BPFBF_EBPFBE_INSN_JLT32RBE, BPFBF_EBPFBE_INSN_JLEIBE
+ , BPFBF_EBPFBE_INSN_JLERBE, BPFBF_EBPFBE_INSN_JLE32IBE, BPFBF_EBPFBE_INSN_JLE32RBE, BPFBF_EBPFBE_INSN_JSETIBE
+ , BPFBF_EBPFBE_INSN_JSETRBE, BPFBF_EBPFBE_INSN_JSET32IBE, BPFBF_EBPFBE_INSN_JSET32RBE, BPFBF_EBPFBE_INSN_JNEIBE
+ , BPFBF_EBPFBE_INSN_JNERBE, BPFBF_EBPFBE_INSN_JNE32IBE, BPFBF_EBPFBE_INSN_JNE32RBE, BPFBF_EBPFBE_INSN_JSGTIBE
+ , BPFBF_EBPFBE_INSN_JSGTRBE, BPFBF_EBPFBE_INSN_JSGT32IBE, BPFBF_EBPFBE_INSN_JSGT32RBE, BPFBF_EBPFBE_INSN_JSGEIBE
+ , BPFBF_EBPFBE_INSN_JSGERBE, BPFBF_EBPFBE_INSN_JSGE32IBE, BPFBF_EBPFBE_INSN_JSGE32RBE, BPFBF_EBPFBE_INSN_JSLTIBE
+ , BPFBF_EBPFBE_INSN_JSLTRBE, BPFBF_EBPFBE_INSN_JSLT32IBE, BPFBF_EBPFBE_INSN_JSLT32RBE, BPFBF_EBPFBE_INSN_JSLEIBE
+ , BPFBF_EBPFBE_INSN_JSLERBE, BPFBF_EBPFBE_INSN_JSLE32IBE, BPFBF_EBPFBE_INSN_JSLE32RBE, BPFBF_EBPFBE_INSN_CALLBE
+ , BPFBF_EBPFBE_INSN_JA, BPFBF_EBPFBE_INSN_EXIT, BPFBF_EBPFBE_INSN_XADDDWBE, BPFBF_EBPFBE_INSN_XADDWBE
+ , BPFBF_EBPFBE_INSN_BRKPT, BPFBF_EBPFBE_INSN__MAX
+} BPFBF_EBPFBE_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family bpfbf. */
+typedef enum bpfbf_ebpfbe_sfmt_type {
+ BPFBF_EBPFBE_SFMT_EMPTY, BPFBF_EBPFBE_SFMT_ADDIBE, BPFBF_EBPFBE_SFMT_ADDRBE, BPFBF_EBPFBE_SFMT_NEGBE
+ , BPFBF_EBPFBE_SFMT_MOVIBE, BPFBF_EBPFBE_SFMT_MOVRBE, BPFBF_EBPFBE_SFMT_ENDLEBE, BPFBF_EBPFBE_SFMT_LDDWBE
+ , BPFBF_EBPFBE_SFMT_LDABSW, BPFBF_EBPFBE_SFMT_LDABSH, BPFBF_EBPFBE_SFMT_LDABSB, BPFBF_EBPFBE_SFMT_LDABSDW
+ , BPFBF_EBPFBE_SFMT_LDINDWBE, BPFBF_EBPFBE_SFMT_LDINDHBE, BPFBF_EBPFBE_SFMT_LDINDBBE, BPFBF_EBPFBE_SFMT_LDINDDWBE
+ , BPFBF_EBPFBE_SFMT_LDXWBE, BPFBF_EBPFBE_SFMT_LDXHBE, BPFBF_EBPFBE_SFMT_LDXBBE, BPFBF_EBPFBE_SFMT_LDXDWBE
+ , BPFBF_EBPFBE_SFMT_STXWBE, BPFBF_EBPFBE_SFMT_STXHBE, BPFBF_EBPFBE_SFMT_STXBBE, BPFBF_EBPFBE_SFMT_STXDWBE
+ , BPFBF_EBPFBE_SFMT_STBBE, BPFBF_EBPFBE_SFMT_STHBE, BPFBF_EBPFBE_SFMT_STWBE, BPFBF_EBPFBE_SFMT_STDWBE
+ , BPFBF_EBPFBE_SFMT_JEQIBE, BPFBF_EBPFBE_SFMT_JEQRBE, BPFBF_EBPFBE_SFMT_CALLBE, BPFBF_EBPFBE_SFMT_JA
+ , BPFBF_EBPFBE_SFMT_EXIT, BPFBF_EBPFBE_SFMT_XADDDWBE, BPFBF_EBPFBE_SFMT_XADDWBE
+} BPFBF_EBPFBE_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* BPFBF_EBPFBE_DECODE_H */
diff --git a/sim/bpf/decode-le.c b/sim/bpf/decode-le.c
new file mode 100644
index 0000000000..8181485e4c
--- /dev/null
+++ b/sim/bpf/decode-le.c
@@ -0,0 +1,1129 @@
+/* Simulator instruction decoder for bpfbf_ebpfle.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU bpfbf
+#define WANT_CPU_BPFBF
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC bpfbf_ebpfle_insn_data[BPFBF_EBPFLE_INSN__MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem bpfbf_ebpfle_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, BPFBF_EBPFLE_INSN_X_AFTER, BPFBF_EBPFLE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, BPFBF_EBPFLE_INSN_X_BEFORE, BPFBF_EBPFLE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, BPFBF_EBPFLE_INSN_X_CTI_CHAIN, BPFBF_EBPFLE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, BPFBF_EBPFLE_INSN_X_CHAIN, BPFBF_EBPFLE_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, BPFBF_EBPFLE_INSN_X_BEGIN, BPFBF_EBPFLE_SFMT_EMPTY },
+ { BPF_INSN_ADDILE, BPFBF_EBPFLE_INSN_ADDILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_ADDRLE, BPFBF_EBPFLE_INSN_ADDRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_ADD32ILE, BPFBF_EBPFLE_INSN_ADD32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_ADD32RLE, BPFBF_EBPFLE_INSN_ADD32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_SUBILE, BPFBF_EBPFLE_INSN_SUBILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_SUBRLE, BPFBF_EBPFLE_INSN_SUBRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_SUB32ILE, BPFBF_EBPFLE_INSN_SUB32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_SUB32RLE, BPFBF_EBPFLE_INSN_SUB32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_MULILE, BPFBF_EBPFLE_INSN_MULILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_MULRLE, BPFBF_EBPFLE_INSN_MULRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_MUL32ILE, BPFBF_EBPFLE_INSN_MUL32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_MUL32RLE, BPFBF_EBPFLE_INSN_MUL32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_DIVILE, BPFBF_EBPFLE_INSN_DIVILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_DIVRLE, BPFBF_EBPFLE_INSN_DIVRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_DIV32ILE, BPFBF_EBPFLE_INSN_DIV32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_DIV32RLE, BPFBF_EBPFLE_INSN_DIV32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_ORILE, BPFBF_EBPFLE_INSN_ORILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_ORRLE, BPFBF_EBPFLE_INSN_ORRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_OR32ILE, BPFBF_EBPFLE_INSN_OR32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_OR32RLE, BPFBF_EBPFLE_INSN_OR32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_ANDILE, BPFBF_EBPFLE_INSN_ANDILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_ANDRLE, BPFBF_EBPFLE_INSN_ANDRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_AND32ILE, BPFBF_EBPFLE_INSN_AND32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_AND32RLE, BPFBF_EBPFLE_INSN_AND32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_LSHILE, BPFBF_EBPFLE_INSN_LSHILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_LSHRLE, BPFBF_EBPFLE_INSN_LSHRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_LSH32ILE, BPFBF_EBPFLE_INSN_LSH32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_LSH32RLE, BPFBF_EBPFLE_INSN_LSH32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_RSHILE, BPFBF_EBPFLE_INSN_RSHILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_RSHRLE, BPFBF_EBPFLE_INSN_RSHRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_RSH32ILE, BPFBF_EBPFLE_INSN_RSH32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_RSH32RLE, BPFBF_EBPFLE_INSN_RSH32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_MODILE, BPFBF_EBPFLE_INSN_MODILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_MODRLE, BPFBF_EBPFLE_INSN_MODRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_MOD32ILE, BPFBF_EBPFLE_INSN_MOD32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_MOD32RLE, BPFBF_EBPFLE_INSN_MOD32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_XORILE, BPFBF_EBPFLE_INSN_XORILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_XORRLE, BPFBF_EBPFLE_INSN_XORRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_XOR32ILE, BPFBF_EBPFLE_INSN_XOR32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_XOR32RLE, BPFBF_EBPFLE_INSN_XOR32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_ARSHILE, BPFBF_EBPFLE_INSN_ARSHILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_ARSHRLE, BPFBF_EBPFLE_INSN_ARSHRLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_ARSH32ILE, BPFBF_EBPFLE_INSN_ARSH32ILE, BPFBF_EBPFLE_SFMT_ADDILE },
+ { BPF_INSN_ARSH32RLE, BPFBF_EBPFLE_INSN_ARSH32RLE, BPFBF_EBPFLE_SFMT_ADDRLE },
+ { BPF_INSN_NEGLE, BPFBF_EBPFLE_INSN_NEGLE, BPFBF_EBPFLE_SFMT_NEGLE },
+ { BPF_INSN_NEG32LE, BPFBF_EBPFLE_INSN_NEG32LE, BPFBF_EBPFLE_SFMT_NEGLE },
+ { BPF_INSN_MOVILE, BPFBF_EBPFLE_INSN_MOVILE, BPFBF_EBPFLE_SFMT_MOVILE },
+ { BPF_INSN_MOVRLE, BPFBF_EBPFLE_INSN_MOVRLE, BPFBF_EBPFLE_SFMT_MOVRLE },
+ { BPF_INSN_MOV32ILE, BPFBF_EBPFLE_INSN_MOV32ILE, BPFBF_EBPFLE_SFMT_MOVILE },
+ { BPF_INSN_MOV32RLE, BPFBF_EBPFLE_INSN_MOV32RLE, BPFBF_EBPFLE_SFMT_MOVRLE },
+ { BPF_INSN_ENDLELE, BPFBF_EBPFLE_INSN_ENDLELE, BPFBF_EBPFLE_SFMT_ENDLELE },
+ { BPF_INSN_ENDBELE, BPFBF_EBPFLE_INSN_ENDBELE, BPFBF_EBPFLE_SFMT_ENDLELE },
+ { BPF_INSN_LDDWLE, BPFBF_EBPFLE_INSN_LDDWLE, BPFBF_EBPFLE_SFMT_LDDWLE },
+ { BPF_INSN_LDABSW, BPFBF_EBPFLE_INSN_LDABSW, BPFBF_EBPFLE_SFMT_LDABSW },
+ { BPF_INSN_LDABSH, BPFBF_EBPFLE_INSN_LDABSH, BPFBF_EBPFLE_SFMT_LDABSH },
+ { BPF_INSN_LDABSB, BPFBF_EBPFLE_INSN_LDABSB, BPFBF_EBPFLE_SFMT_LDABSB },
+ { BPF_INSN_LDABSDW, BPFBF_EBPFLE_INSN_LDABSDW, BPFBF_EBPFLE_SFMT_LDABSDW },
+ { BPF_INSN_LDINDWLE, BPFBF_EBPFLE_INSN_LDINDWLE, BPFBF_EBPFLE_SFMT_LDINDWLE },
+ { BPF_INSN_LDINDHLE, BPFBF_EBPFLE_INSN_LDINDHLE, BPFBF_EBPFLE_SFMT_LDINDHLE },
+ { BPF_INSN_LDINDBLE, BPFBF_EBPFLE_INSN_LDINDBLE, BPFBF_EBPFLE_SFMT_LDINDBLE },
+ { BPF_INSN_LDINDDWLE, BPFBF_EBPFLE_INSN_LDINDDWLE, BPFBF_EBPFLE_SFMT_LDINDDWLE },
+ { BPF_INSN_LDXWLE, BPFBF_EBPFLE_INSN_LDXWLE, BPFBF_EBPFLE_SFMT_LDXWLE },
+ { BPF_INSN_LDXHLE, BPFBF_EBPFLE_INSN_LDXHLE, BPFBF_EBPFLE_SFMT_LDXHLE },
+ { BPF_INSN_LDXBLE, BPFBF_EBPFLE_INSN_LDXBLE, BPFBF_EBPFLE_SFMT_LDXBLE },
+ { BPF_INSN_LDXDWLE, BPFBF_EBPFLE_INSN_LDXDWLE, BPFBF_EBPFLE_SFMT_LDXDWLE },
+ { BPF_INSN_STXWLE, BPFBF_EBPFLE_INSN_STXWLE, BPFBF_EBPFLE_SFMT_STXWLE },
+ { BPF_INSN_STXHLE, BPFBF_EBPFLE_INSN_STXHLE, BPFBF_EBPFLE_SFMT_STXHLE },
+ { BPF_INSN_STXBLE, BPFBF_EBPFLE_INSN_STXBLE, BPFBF_EBPFLE_SFMT_STXBLE },
+ { BPF_INSN_STXDWLE, BPFBF_EBPFLE_INSN_STXDWLE, BPFBF_EBPFLE_SFMT_STXDWLE },
+ { BPF_INSN_STBLE, BPFBF_EBPFLE_INSN_STBLE, BPFBF_EBPFLE_SFMT_STBLE },
+ { BPF_INSN_STHLE, BPFBF_EBPFLE_INSN_STHLE, BPFBF_EBPFLE_SFMT_STHLE },
+ { BPF_INSN_STWLE, BPFBF_EBPFLE_INSN_STWLE, BPFBF_EBPFLE_SFMT_STWLE },
+ { BPF_INSN_STDWLE, BPFBF_EBPFLE_INSN_STDWLE, BPFBF_EBPFLE_SFMT_STDWLE },
+ { BPF_INSN_JEQILE, BPFBF_EBPFLE_INSN_JEQILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JEQRLE, BPFBF_EBPFLE_INSN_JEQRLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JEQ32ILE, BPFBF_EBPFLE_INSN_JEQ32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JEQ32RLE, BPFBF_EBPFLE_INSN_JEQ32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JGTILE, BPFBF_EBPFLE_INSN_JGTILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JGTRLE, BPFBF_EBPFLE_INSN_JGTRLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JGT32ILE, BPFBF_EBPFLE_INSN_JGT32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JGT32RLE, BPFBF_EBPFLE_INSN_JGT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JGEILE, BPFBF_EBPFLE_INSN_JGEILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JGERLE, BPFBF_EBPFLE_INSN_JGERLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JGE32ILE, BPFBF_EBPFLE_INSN_JGE32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JGE32RLE, BPFBF_EBPFLE_INSN_JGE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JLTILE, BPFBF_EBPFLE_INSN_JLTILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JLTRLE, BPFBF_EBPFLE_INSN_JLTRLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JLT32ILE, BPFBF_EBPFLE_INSN_JLT32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JLT32RLE, BPFBF_EBPFLE_INSN_JLT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JLEILE, BPFBF_EBPFLE_INSN_JLEILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JLERLE, BPFBF_EBPFLE_INSN_JLERLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JLE32ILE, BPFBF_EBPFLE_INSN_JLE32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JLE32RLE, BPFBF_EBPFLE_INSN_JLE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSETILE, BPFBF_EBPFLE_INSN_JSETILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSETRLE, BPFBF_EBPFLE_INSN_JSETRLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSET32ILE, BPFBF_EBPFLE_INSN_JSET32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSET32RLE, BPFBF_EBPFLE_INSN_JSET32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JNEILE, BPFBF_EBPFLE_INSN_JNEILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JNERLE, BPFBF_EBPFLE_INSN_JNERLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JNE32ILE, BPFBF_EBPFLE_INSN_JNE32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JNE32RLE, BPFBF_EBPFLE_INSN_JNE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSGTILE, BPFBF_EBPFLE_INSN_JSGTILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSGTRLE, BPFBF_EBPFLE_INSN_JSGTRLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSGT32ILE, BPFBF_EBPFLE_INSN_JSGT32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSGT32RLE, BPFBF_EBPFLE_INSN_JSGT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSGEILE, BPFBF_EBPFLE_INSN_JSGEILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSGERLE, BPFBF_EBPFLE_INSN_JSGERLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSGE32ILE, BPFBF_EBPFLE_INSN_JSGE32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSGE32RLE, BPFBF_EBPFLE_INSN_JSGE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSLTILE, BPFBF_EBPFLE_INSN_JSLTILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSLTRLE, BPFBF_EBPFLE_INSN_JSLTRLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSLT32ILE, BPFBF_EBPFLE_INSN_JSLT32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSLT32RLE, BPFBF_EBPFLE_INSN_JSLT32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSLEILE, BPFBF_EBPFLE_INSN_JSLEILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSLERLE, BPFBF_EBPFLE_INSN_JSLERLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_JSLE32ILE, BPFBF_EBPFLE_INSN_JSLE32ILE, BPFBF_EBPFLE_SFMT_JEQILE },
+ { BPF_INSN_JSLE32RLE, BPFBF_EBPFLE_INSN_JSLE32RLE, BPFBF_EBPFLE_SFMT_JEQRLE },
+ { BPF_INSN_CALLLE, BPFBF_EBPFLE_INSN_CALLLE, BPFBF_EBPFLE_SFMT_CALLLE },
+ { BPF_INSN_JA, BPFBF_EBPFLE_INSN_JA, BPFBF_EBPFLE_SFMT_JA },
+ { BPF_INSN_EXIT, BPFBF_EBPFLE_INSN_EXIT, BPFBF_EBPFLE_SFMT_EXIT },
+ { BPF_INSN_XADDDWLE, BPFBF_EBPFLE_INSN_XADDDWLE, BPFBF_EBPFLE_SFMT_XADDDWLE },
+ { BPF_INSN_XADDWLE, BPFBF_EBPFLE_INSN_XADDWLE, BPFBF_EBPFLE_SFMT_XADDWLE },
+ { BPF_INSN_BRKPT, BPFBF_EBPFLE_INSN_BRKPT, BPFBF_EBPFLE_SFMT_EXIT },
+};
+
+static const struct insn_sem bpfbf_ebpfle_insn_sem_invalid =
+{
+ VIRTUAL_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+bpfbf_ebpfle_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = BPFBF_EBPFLE_INSN__MAX;
+ IDESC *table = bpfbf_ebpfle_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & bpfbf_ebpfle_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = bpfbf_ebpfle_insn_sem, tend = t + sizeof (bpfbf_ebpfle_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+bpfbf_ebpfle_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_WORD base_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ BPFBF_EBPFLE_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_WORD insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 0) & (255 << 0)));
+ switch (val)
+ {
+ case 4 : itype = BPFBF_EBPFLE_INSN_ADD32ILE; goto extract_sfmt_addile;
+ case 5 : itype = BPFBF_EBPFLE_INSN_JA; goto extract_sfmt_ja;
+ case 7 : itype = BPFBF_EBPFLE_INSN_ADDILE; goto extract_sfmt_addile;
+ case 12 : itype = BPFBF_EBPFLE_INSN_ADD32RLE; goto extract_sfmt_addrle;
+ case 15 : itype = BPFBF_EBPFLE_INSN_ADDRLE; goto extract_sfmt_addrle;
+ case 20 : itype = BPFBF_EBPFLE_INSN_SUB32ILE; goto extract_sfmt_addile;
+ case 21 : itype = BPFBF_EBPFLE_INSN_JEQILE; goto extract_sfmt_jeqile;
+ case 22 : itype = BPFBF_EBPFLE_INSN_JEQ32ILE; goto extract_sfmt_jeqile;
+ case 23 : itype = BPFBF_EBPFLE_INSN_SUBILE; goto extract_sfmt_addile;
+ case 24 : itype = BPFBF_EBPFLE_INSN_LDDWLE; goto extract_sfmt_lddwle;
+ case 28 : itype = BPFBF_EBPFLE_INSN_SUB32RLE; goto extract_sfmt_addrle;
+ case 29 : itype = BPFBF_EBPFLE_INSN_JEQRLE; goto extract_sfmt_jeqrle;
+ case 30 : itype = BPFBF_EBPFLE_INSN_JEQ32RLE; goto extract_sfmt_jeqrle;
+ case 31 : itype = BPFBF_EBPFLE_INSN_SUBRLE; goto extract_sfmt_addrle;
+ case 32 : itype = BPFBF_EBPFLE_INSN_LDABSW; goto extract_sfmt_ldabsw;
+ case 36 : itype = BPFBF_EBPFLE_INSN_MUL32ILE; goto extract_sfmt_addile;
+ case 37 : itype = BPFBF_EBPFLE_INSN_JGTILE; goto extract_sfmt_jeqile;
+ case 38 : itype = BPFBF_EBPFLE_INSN_JGT32ILE; goto extract_sfmt_jeqile;
+ case 39 : itype = BPFBF_EBPFLE_INSN_MULILE; goto extract_sfmt_addile;
+ case 40 : itype = BPFBF_EBPFLE_INSN_LDABSH; goto extract_sfmt_ldabsh;
+ case 44 : itype = BPFBF_EBPFLE_INSN_MUL32RLE; goto extract_sfmt_addrle;
+ case 45 : itype = BPFBF_EBPFLE_INSN_JGTRLE; goto extract_sfmt_jeqrle;
+ case 46 : itype = BPFBF_EBPFLE_INSN_JGT32RLE; goto extract_sfmt_jeqrle;
+ case 47 : itype = BPFBF_EBPFLE_INSN_MULRLE; goto extract_sfmt_addrle;
+ case 48 : itype = BPFBF_EBPFLE_INSN_LDABSB; goto extract_sfmt_ldabsb;
+ case 52 : itype = BPFBF_EBPFLE_INSN_DIV32ILE; goto extract_sfmt_addile;
+ case 53 : itype = BPFBF_EBPFLE_INSN_JGEILE; goto extract_sfmt_jeqile;
+ case 54 : itype = BPFBF_EBPFLE_INSN_JGE32ILE; goto extract_sfmt_jeqile;
+ case 55 : itype = BPFBF_EBPFLE_INSN_DIVILE; goto extract_sfmt_addile;
+ case 56 : itype = BPFBF_EBPFLE_INSN_LDABSDW; goto extract_sfmt_ldabsdw;
+ case 60 : itype = BPFBF_EBPFLE_INSN_DIV32RLE; goto extract_sfmt_addrle;
+ case 61 : itype = BPFBF_EBPFLE_INSN_JGERLE; goto extract_sfmt_jeqrle;
+ case 62 : itype = BPFBF_EBPFLE_INSN_JGE32RLE; goto extract_sfmt_jeqrle;
+ case 63 : itype = BPFBF_EBPFLE_INSN_DIVRLE; goto extract_sfmt_addrle;
+ case 64 : itype = BPFBF_EBPFLE_INSN_LDINDWLE; goto extract_sfmt_ldindwle;
+ case 68 : itype = BPFBF_EBPFLE_INSN_OR32ILE; goto extract_sfmt_addile;
+ case 69 : itype = BPFBF_EBPFLE_INSN_JSETILE; goto extract_sfmt_jeqile;
+ case 70 : itype = BPFBF_EBPFLE_INSN_JSET32ILE; goto extract_sfmt_jeqile;
+ case 71 : itype = BPFBF_EBPFLE_INSN_ORILE; goto extract_sfmt_addile;
+ case 72 : itype = BPFBF_EBPFLE_INSN_LDINDHLE; goto extract_sfmt_ldindhle;
+ case 76 : itype = BPFBF_EBPFLE_INSN_OR32RLE; goto extract_sfmt_addrle;
+ case 77 : itype = BPFBF_EBPFLE_INSN_JSETRLE; goto extract_sfmt_jeqrle;
+ case 78 : itype = BPFBF_EBPFLE_INSN_JSET32RLE; goto extract_sfmt_jeqrle;
+ case 79 : itype = BPFBF_EBPFLE_INSN_ORRLE; goto extract_sfmt_addrle;
+ case 80 : itype = BPFBF_EBPFLE_INSN_LDINDBLE; goto extract_sfmt_ldindble;
+ case 84 : itype = BPFBF_EBPFLE_INSN_AND32ILE; goto extract_sfmt_addile;
+ case 85 : itype = BPFBF_EBPFLE_INSN_JNEILE; goto extract_sfmt_jeqile;
+ case 86 : itype = BPFBF_EBPFLE_INSN_JNE32ILE; goto extract_sfmt_jeqile;
+ case 87 : itype = BPFBF_EBPFLE_INSN_ANDILE; goto extract_sfmt_addile;
+ case 88 : itype = BPFBF_EBPFLE_INSN_LDINDDWLE; goto extract_sfmt_ldinddwle;
+ case 92 : itype = BPFBF_EBPFLE_INSN_AND32RLE; goto extract_sfmt_addrle;
+ case 93 : itype = BPFBF_EBPFLE_INSN_JNERLE; goto extract_sfmt_jeqrle;
+ case 94 : itype = BPFBF_EBPFLE_INSN_JNE32RLE; goto extract_sfmt_jeqrle;
+ case 95 : itype = BPFBF_EBPFLE_INSN_ANDRLE; goto extract_sfmt_addrle;
+ case 97 : itype = BPFBF_EBPFLE_INSN_LDXWLE; goto extract_sfmt_ldxwle;
+ case 98 : itype = BPFBF_EBPFLE_INSN_STWLE; goto extract_sfmt_stwle;
+ case 99 : itype = BPFBF_EBPFLE_INSN_STXWLE; goto extract_sfmt_stxwle;
+ case 100 : itype = BPFBF_EBPFLE_INSN_LSH32ILE; goto extract_sfmt_addile;
+ case 101 : itype = BPFBF_EBPFLE_INSN_JSGTILE; goto extract_sfmt_jeqile;
+ case 102 : itype = BPFBF_EBPFLE_INSN_JSGT32ILE; goto extract_sfmt_jeqile;
+ case 103 : itype = BPFBF_EBPFLE_INSN_LSHILE; goto extract_sfmt_addile;
+ case 105 : itype = BPFBF_EBPFLE_INSN_LDXHLE; goto extract_sfmt_ldxhle;
+ case 106 : itype = BPFBF_EBPFLE_INSN_STHLE; goto extract_sfmt_sthle;
+ case 107 : itype = BPFBF_EBPFLE_INSN_STXHLE; goto extract_sfmt_stxhle;
+ case 108 : itype = BPFBF_EBPFLE_INSN_LSH32RLE; goto extract_sfmt_addrle;
+ case 109 : itype = BPFBF_EBPFLE_INSN_JSGTRLE; goto extract_sfmt_jeqrle;
+ case 110 : itype = BPFBF_EBPFLE_INSN_JSGT32RLE; goto extract_sfmt_jeqrle;
+ case 111 : itype = BPFBF_EBPFLE_INSN_LSHRLE; goto extract_sfmt_addrle;
+ case 113 : itype = BPFBF_EBPFLE_INSN_LDXBLE; goto extract_sfmt_ldxble;
+ case 114 : itype = BPFBF_EBPFLE_INSN_STBLE; goto extract_sfmt_stble;
+ case 115 : itype = BPFBF_EBPFLE_INSN_STXBLE; goto extract_sfmt_stxble;
+ case 116 : itype = BPFBF_EBPFLE_INSN_RSH32ILE; goto extract_sfmt_addile;
+ case 117 : itype = BPFBF_EBPFLE_INSN_JSGEILE; goto extract_sfmt_jeqile;
+ case 118 : itype = BPFBF_EBPFLE_INSN_JSGE32ILE; goto extract_sfmt_jeqile;
+ case 119 : itype = BPFBF_EBPFLE_INSN_RSHILE; goto extract_sfmt_addile;
+ case 121 : itype = BPFBF_EBPFLE_INSN_LDXDWLE; goto extract_sfmt_ldxdwle;
+ case 122 : itype = BPFBF_EBPFLE_INSN_STDWLE; goto extract_sfmt_stdwle;
+ case 123 : itype = BPFBF_EBPFLE_INSN_STXDWLE; goto extract_sfmt_stxdwle;
+ case 124 : itype = BPFBF_EBPFLE_INSN_RSH32RLE; goto extract_sfmt_addrle;
+ case 125 : itype = BPFBF_EBPFLE_INSN_JSGERLE; goto extract_sfmt_jeqrle;
+ case 126 : itype = BPFBF_EBPFLE_INSN_JSGE32RLE; goto extract_sfmt_jeqrle;
+ case 127 : itype = BPFBF_EBPFLE_INSN_RSHRLE; goto extract_sfmt_addrle;
+ case 132 : itype = BPFBF_EBPFLE_INSN_NEG32LE; goto extract_sfmt_negle;
+ case 133 : itype = BPFBF_EBPFLE_INSN_CALLLE; goto extract_sfmt_callle;
+ case 135 : itype = BPFBF_EBPFLE_INSN_NEGLE; goto extract_sfmt_negle;
+ case 140 : itype = BPFBF_EBPFLE_INSN_BRKPT; goto extract_sfmt_exit;
+ case 148 : itype = BPFBF_EBPFLE_INSN_MOD32ILE; goto extract_sfmt_addile;
+ case 149 : itype = BPFBF_EBPFLE_INSN_EXIT; goto extract_sfmt_exit;
+ case 151 : itype = BPFBF_EBPFLE_INSN_MODILE; goto extract_sfmt_addile;
+ case 156 : itype = BPFBF_EBPFLE_INSN_MOD32RLE; goto extract_sfmt_addrle;
+ case 159 : itype = BPFBF_EBPFLE_INSN_MODRLE; goto extract_sfmt_addrle;
+ case 164 : itype = BPFBF_EBPFLE_INSN_XOR32ILE; goto extract_sfmt_addile;
+ case 165 : itype = BPFBF_EBPFLE_INSN_JLTILE; goto extract_sfmt_jeqile;
+ case 166 : itype = BPFBF_EBPFLE_INSN_JLT32ILE; goto extract_sfmt_jeqile;
+ case 167 : itype = BPFBF_EBPFLE_INSN_XORILE; goto extract_sfmt_addile;
+ case 172 : itype = BPFBF_EBPFLE_INSN_XOR32RLE; goto extract_sfmt_addrle;
+ case 173 : itype = BPFBF_EBPFLE_INSN_JLTRLE; goto extract_sfmt_jeqrle;
+ case 174 : itype = BPFBF_EBPFLE_INSN_JLT32RLE; goto extract_sfmt_jeqrle;
+ case 175 : itype = BPFBF_EBPFLE_INSN_XORRLE; goto extract_sfmt_addrle;
+ case 180 : itype = BPFBF_EBPFLE_INSN_MOV32ILE; goto extract_sfmt_movile;
+ case 181 : itype = BPFBF_EBPFLE_INSN_JLEILE; goto extract_sfmt_jeqile;
+ case 182 : itype = BPFBF_EBPFLE_INSN_JLE32ILE; goto extract_sfmt_jeqile;
+ case 183 : itype = BPFBF_EBPFLE_INSN_MOVILE; goto extract_sfmt_movile;
+ case 188 : itype = BPFBF_EBPFLE_INSN_MOV32RLE; goto extract_sfmt_movrle;
+ case 189 : itype = BPFBF_EBPFLE_INSN_JLERLE; goto extract_sfmt_jeqrle;
+ case 190 : itype = BPFBF_EBPFLE_INSN_JLE32RLE; goto extract_sfmt_jeqrle;
+ case 191 : itype = BPFBF_EBPFLE_INSN_MOVRLE; goto extract_sfmt_movrle;
+ case 195 : itype = BPFBF_EBPFLE_INSN_XADDWLE; goto extract_sfmt_xaddwle;
+ case 196 : itype = BPFBF_EBPFLE_INSN_ARSH32ILE; goto extract_sfmt_addile;
+ case 197 : itype = BPFBF_EBPFLE_INSN_JSLTILE; goto extract_sfmt_jeqile;
+ case 198 : itype = BPFBF_EBPFLE_INSN_JSLT32ILE; goto extract_sfmt_jeqile;
+ case 199 : itype = BPFBF_EBPFLE_INSN_ARSHILE; goto extract_sfmt_addile;
+ case 204 : itype = BPFBF_EBPFLE_INSN_ARSH32RLE; goto extract_sfmt_addrle;
+ case 205 : itype = BPFBF_EBPFLE_INSN_JSLTRLE; goto extract_sfmt_jeqrle;
+ case 206 : itype = BPFBF_EBPFLE_INSN_JSLT32RLE; goto extract_sfmt_jeqrle;
+ case 207 : itype = BPFBF_EBPFLE_INSN_ARSHRLE; goto extract_sfmt_addrle;
+ case 212 : itype = BPFBF_EBPFLE_INSN_ENDLELE; goto extract_sfmt_endlele;
+ case 213 : itype = BPFBF_EBPFLE_INSN_JSLEILE; goto extract_sfmt_jeqile;
+ case 214 : itype = BPFBF_EBPFLE_INSN_JSLE32ILE; goto extract_sfmt_jeqile;
+ case 219 : itype = BPFBF_EBPFLE_INSN_XADDDWLE; goto extract_sfmt_xadddwle;
+ case 220 : itype = BPFBF_EBPFLE_INSN_ENDBELE; goto extract_sfmt_endlele;
+ case 221 : itype = BPFBF_EBPFLE_INSN_JSLERLE; goto extract_sfmt_jeqrle;
+ case 222 : itype = BPFBF_EBPFLE_INSN_JSLE32RLE; goto extract_sfmt_jeqrle;
+ default : itype = BPFBF_EBPFLE_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addile:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addile", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addrle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addrle", "f_dstle 0x%x", 'x', f_dstle, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_negle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_lddwle.f
+ UINT f_dstle;
+
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negle", "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movile:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movile", "f_imm32 0x%x", 'x', f_imm32, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movrle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_srcle) = f_srcle;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movrle", "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_endlele:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_endlele", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lddwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_lddwle.f
+ UINT f_imm64_c;
+ UINT f_imm64_b;
+ UINT f_imm64_a;
+ UINT f_dstle;
+ DI f_imm64;
+ /* Contents of trailing part of insn. */
+ UINT word_1;
+ UINT word_2;
+
+ word_1 = GETIMEMUSI (current_cpu, pc + 8);
+ word_2 = GETIMEMUSI (current_cpu, pc + 12);
+ f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0));
+ f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0));
+ f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+{
+ f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));
+}
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm64) = f_imm64;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lddwle", "f_imm64 0x%x", 'x', f_imm64, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsw:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsh:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsh", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsb:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsb", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldabsdw:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldabsdw", "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldindwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+ UINT f_srcle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindwle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldindhle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+ UINT f_srcle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindhle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldindble:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+ UINT f_srcle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldindble", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldinddwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+ UINT f_srcle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldinddwle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxwle", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxhle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxhle", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxble:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxble", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxdwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ FLD (f_dstle) = f_dstle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxdwle", "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, "f_dstle 0x%x", 'x', f_dstle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxhle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxhle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxble:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxble", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxdwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxdwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stble:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stble", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sthle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthle", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stwle", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stdwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stdwle", "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jeqile:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ INT f_imm32;
+ HI f_offset16;
+ UINT f_dstle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_dstle) = f_dstle;
+ FLD (f_imm32) = f_imm32;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqile", "f_offset16 0x%x", 'x', f_offset16, "f_dstle 0x%x", 'x', f_dstle, "f_imm32 0x%x", 'x', f_imm32, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jeqrle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ FLD (f_dstle) = f_dstle;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jeqrle", "f_offset16 0x%x", 'x', f_offset16, "f_dstle 0x%x", 'x', f_dstle, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_callle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ INT f_imm32;
+ UINT f_srcle;
+
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm32) = f_imm32;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_callle", "f_imm32 0x%x", 'x', f_imm32, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ja:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_stble.f
+ HI f_offset16;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_offset16) = f_offset16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ja", "f_offset16 0x%x", 'x', f_offset16, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_exit:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_exit", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_xadddwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xadddwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_xaddwle:
+ {
+ const IDESC *idesc = &bpfbf_ebpfle_insn_data[itype];
+ CGEN_INSN_WORD insn = base_insn;
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ HI f_offset16;
+ UINT f_srcle;
+ UINT f_dstle;
+
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0));
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0));
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dstle) = f_dstle;
+ FLD (f_offset16) = f_offset16;
+ FLD (f_srcle) = f_srcle;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xaddwle", "f_dstle 0x%x", 'x', f_dstle, "f_offset16 0x%x", 'x', f_offset16, "f_srcle 0x%x", 'x', f_srcle, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+}
diff --git a/sim/bpf/decode-le.h b/sim/bpf/decode-le.h
new file mode 100644
index 0000000000..d854f1d4ed
--- /dev/null
+++ b/sim/bpf/decode-le.h
@@ -0,0 +1,94 @@
+/* Decode header for bpfbf_ebpfle.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef BPFBF_EBPFLE_DECODE_H
+#define BPFBF_EBPFLE_DECODE_H
+
+extern const IDESC *bpfbf_ebpfle_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_WORD,
+ ARGBUF *);
+extern void bpfbf_ebpfle_init_idesc_table (SIM_CPU *);
+extern void bpfbf_ebpfle_sem_init_idesc_table (SIM_CPU *);
+extern void bpfbf_ebpfle_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family bpfbf. */
+typedef enum bpfbf_ebpfle_insn_type {
+ BPFBF_EBPFLE_INSN_X_INVALID, BPFBF_EBPFLE_INSN_X_AFTER, BPFBF_EBPFLE_INSN_X_BEFORE, BPFBF_EBPFLE_INSN_X_CTI_CHAIN
+ , BPFBF_EBPFLE_INSN_X_CHAIN, BPFBF_EBPFLE_INSN_X_BEGIN, BPFBF_EBPFLE_INSN_ADDILE, BPFBF_EBPFLE_INSN_ADDRLE
+ , BPFBF_EBPFLE_INSN_ADD32ILE, BPFBF_EBPFLE_INSN_ADD32RLE, BPFBF_EBPFLE_INSN_SUBILE, BPFBF_EBPFLE_INSN_SUBRLE
+ , BPFBF_EBPFLE_INSN_SUB32ILE, BPFBF_EBPFLE_INSN_SUB32RLE, BPFBF_EBPFLE_INSN_MULILE, BPFBF_EBPFLE_INSN_MULRLE
+ , BPFBF_EBPFLE_INSN_MUL32ILE, BPFBF_EBPFLE_INSN_MUL32RLE, BPFBF_EBPFLE_INSN_DIVILE, BPFBF_EBPFLE_INSN_DIVRLE
+ , BPFBF_EBPFLE_INSN_DIV32ILE, BPFBF_EBPFLE_INSN_DIV32RLE, BPFBF_EBPFLE_INSN_ORILE, BPFBF_EBPFLE_INSN_ORRLE
+ , BPFBF_EBPFLE_INSN_OR32ILE, BPFBF_EBPFLE_INSN_OR32RLE, BPFBF_EBPFLE_INSN_ANDILE, BPFBF_EBPFLE_INSN_ANDRLE
+ , BPFBF_EBPFLE_INSN_AND32ILE, BPFBF_EBPFLE_INSN_AND32RLE, BPFBF_EBPFLE_INSN_LSHILE, BPFBF_EBPFLE_INSN_LSHRLE
+ , BPFBF_EBPFLE_INSN_LSH32ILE, BPFBF_EBPFLE_INSN_LSH32RLE, BPFBF_EBPFLE_INSN_RSHILE, BPFBF_EBPFLE_INSN_RSHRLE
+ , BPFBF_EBPFLE_INSN_RSH32ILE, BPFBF_EBPFLE_INSN_RSH32RLE, BPFBF_EBPFLE_INSN_MODILE, BPFBF_EBPFLE_INSN_MODRLE
+ , BPFBF_EBPFLE_INSN_MOD32ILE, BPFBF_EBPFLE_INSN_MOD32RLE, BPFBF_EBPFLE_INSN_XORILE, BPFBF_EBPFLE_INSN_XORRLE
+ , BPFBF_EBPFLE_INSN_XOR32ILE, BPFBF_EBPFLE_INSN_XOR32RLE, BPFBF_EBPFLE_INSN_ARSHILE, BPFBF_EBPFLE_INSN_ARSHRLE
+ , BPFBF_EBPFLE_INSN_ARSH32ILE, BPFBF_EBPFLE_INSN_ARSH32RLE, BPFBF_EBPFLE_INSN_NEGLE, BPFBF_EBPFLE_INSN_NEG32LE
+ , BPFBF_EBPFLE_INSN_MOVILE, BPFBF_EBPFLE_INSN_MOVRLE, BPFBF_EBPFLE_INSN_MOV32ILE, BPFBF_EBPFLE_INSN_MOV32RLE
+ , BPFBF_EBPFLE_INSN_ENDLELE, BPFBF_EBPFLE_INSN_ENDBELE, BPFBF_EBPFLE_INSN_LDDWLE, BPFBF_EBPFLE_INSN_LDABSW
+ , BPFBF_EBPFLE_INSN_LDABSH, BPFBF_EBPFLE_INSN_LDABSB, BPFBF_EBPFLE_INSN_LDABSDW, BPFBF_EBPFLE_INSN_LDINDWLE
+ , BPFBF_EBPFLE_INSN_LDINDHLE, BPFBF_EBPFLE_INSN_LDINDBLE, BPFBF_EBPFLE_INSN_LDINDDWLE, BPFBF_EBPFLE_INSN_LDXWLE
+ , BPFBF_EBPFLE_INSN_LDXHLE, BPFBF_EBPFLE_INSN_LDXBLE, BPFBF_EBPFLE_INSN_LDXDWLE, BPFBF_EBPFLE_INSN_STXWLE
+ , BPFBF_EBPFLE_INSN_STXHLE, BPFBF_EBPFLE_INSN_STXBLE, BPFBF_EBPFLE_INSN_STXDWLE, BPFBF_EBPFLE_INSN_STBLE
+ , BPFBF_EBPFLE_INSN_STHLE, BPFBF_EBPFLE_INSN_STWLE, BPFBF_EBPFLE_INSN_STDWLE, BPFBF_EBPFLE_INSN_JEQILE
+ , BPFBF_EBPFLE_INSN_JEQRLE, BPFBF_EBPFLE_INSN_JEQ32ILE, BPFBF_EBPFLE_INSN_JEQ32RLE, BPFBF_EBPFLE_INSN_JGTILE
+ , BPFBF_EBPFLE_INSN_JGTRLE, BPFBF_EBPFLE_INSN_JGT32ILE, BPFBF_EBPFLE_INSN_JGT32RLE, BPFBF_EBPFLE_INSN_JGEILE
+ , BPFBF_EBPFLE_INSN_JGERLE, BPFBF_EBPFLE_INSN_JGE32ILE, BPFBF_EBPFLE_INSN_JGE32RLE, BPFBF_EBPFLE_INSN_JLTILE
+ , BPFBF_EBPFLE_INSN_JLTRLE, BPFBF_EBPFLE_INSN_JLT32ILE, BPFBF_EBPFLE_INSN_JLT32RLE, BPFBF_EBPFLE_INSN_JLEILE
+ , BPFBF_EBPFLE_INSN_JLERLE, BPFBF_EBPFLE_INSN_JLE32ILE, BPFBF_EBPFLE_INSN_JLE32RLE, BPFBF_EBPFLE_INSN_JSETILE
+ , BPFBF_EBPFLE_INSN_JSETRLE, BPFBF_EBPFLE_INSN_JSET32ILE, BPFBF_EBPFLE_INSN_JSET32RLE, BPFBF_EBPFLE_INSN_JNEILE
+ , BPFBF_EBPFLE_INSN_JNERLE, BPFBF_EBPFLE_INSN_JNE32ILE, BPFBF_EBPFLE_INSN_JNE32RLE, BPFBF_EBPFLE_INSN_JSGTILE
+ , BPFBF_EBPFLE_INSN_JSGTRLE, BPFBF_EBPFLE_INSN_JSGT32ILE, BPFBF_EBPFLE_INSN_JSGT32RLE, BPFBF_EBPFLE_INSN_JSGEILE
+ , BPFBF_EBPFLE_INSN_JSGERLE, BPFBF_EBPFLE_INSN_JSGE32ILE, BPFBF_EBPFLE_INSN_JSGE32RLE, BPFBF_EBPFLE_INSN_JSLTILE
+ , BPFBF_EBPFLE_INSN_JSLTRLE, BPFBF_EBPFLE_INSN_JSLT32ILE, BPFBF_EBPFLE_INSN_JSLT32RLE, BPFBF_EBPFLE_INSN_JSLEILE
+ , BPFBF_EBPFLE_INSN_JSLERLE, BPFBF_EBPFLE_INSN_JSLE32ILE, BPFBF_EBPFLE_INSN_JSLE32RLE, BPFBF_EBPFLE_INSN_CALLLE
+ , BPFBF_EBPFLE_INSN_JA, BPFBF_EBPFLE_INSN_EXIT, BPFBF_EBPFLE_INSN_XADDDWLE, BPFBF_EBPFLE_INSN_XADDWLE
+ , BPFBF_EBPFLE_INSN_BRKPT, BPFBF_EBPFLE_INSN__MAX
+} BPFBF_EBPFLE_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family bpfbf. */
+typedef enum bpfbf_ebpfle_sfmt_type {
+ BPFBF_EBPFLE_SFMT_EMPTY, BPFBF_EBPFLE_SFMT_ADDILE, BPFBF_EBPFLE_SFMT_ADDRLE, BPFBF_EBPFLE_SFMT_NEGLE
+ , BPFBF_EBPFLE_SFMT_MOVILE, BPFBF_EBPFLE_SFMT_MOVRLE, BPFBF_EBPFLE_SFMT_ENDLELE, BPFBF_EBPFLE_SFMT_LDDWLE
+ , BPFBF_EBPFLE_SFMT_LDABSW, BPFBF_EBPFLE_SFMT_LDABSH, BPFBF_EBPFLE_SFMT_LDABSB, BPFBF_EBPFLE_SFMT_LDABSDW
+ , BPFBF_EBPFLE_SFMT_LDINDWLE, BPFBF_EBPFLE_SFMT_LDINDHLE, BPFBF_EBPFLE_SFMT_LDINDBLE, BPFBF_EBPFLE_SFMT_LDINDDWLE
+ , BPFBF_EBPFLE_SFMT_LDXWLE, BPFBF_EBPFLE_SFMT_LDXHLE, BPFBF_EBPFLE_SFMT_LDXBLE, BPFBF_EBPFLE_SFMT_LDXDWLE
+ , BPFBF_EBPFLE_SFMT_STXWLE, BPFBF_EBPFLE_SFMT_STXHLE, BPFBF_EBPFLE_SFMT_STXBLE, BPFBF_EBPFLE_SFMT_STXDWLE
+ , BPFBF_EBPFLE_SFMT_STBLE, BPFBF_EBPFLE_SFMT_STHLE, BPFBF_EBPFLE_SFMT_STWLE, BPFBF_EBPFLE_SFMT_STDWLE
+ , BPFBF_EBPFLE_SFMT_JEQILE, BPFBF_EBPFLE_SFMT_JEQRLE, BPFBF_EBPFLE_SFMT_CALLLE, BPFBF_EBPFLE_SFMT_JA
+ , BPFBF_EBPFLE_SFMT_EXIT, BPFBF_EBPFLE_SFMT_XADDDWLE, BPFBF_EBPFLE_SFMT_XADDWLE
+} BPFBF_EBPFLE_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int bpfbf_model_bpf_def_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void bpfbf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void bpfbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* BPFBF_EBPFLE_DECODE_H */
diff --git a/sim/bpf/defs-be.h b/sim/bpf/defs-be.h
new file mode 100644
index 0000000000..fc6dbb4d7a
--- /dev/null
+++ b/sim/bpf/defs-be.h
@@ -0,0 +1,383 @@
+/* ISA definitions header for ebpfbe.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef DEFS_BPFBF_EBPFBE_H
+#define DEFS_BPFBF_EBPFBE_H
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } sfmt_empty;
+ struct { /* */
+ INT f_imm32;
+ UINT f_srcbe;
+ } sfmt_ldindwbe;
+ struct { /* */
+ DI f_imm64;
+ UINT f_dstbe;
+ } sfmt_lddwbe;
+ struct { /* */
+ INT f_imm32;
+ UINT f_dstbe;
+ HI f_offset16;
+ } sfmt_stbbe;
+ struct { /* */
+ UINT f_dstbe;
+ UINT f_srcbe;
+ HI f_offset16;
+ } sfmt_ldxwbe;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_ADDIBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_code; \
+ UINT f_srcbe; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDIBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_ADDRBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_code; \
+ UINT f_srcbe; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDRBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_NEGBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_code; \
+ UINT f_srcbe; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_NEGBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_ENDLEBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_code; \
+ UINT f_srcbe; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_ENDLEBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDDWBE_VARS \
+ UINT f_imm64_a; \
+ UINT f_imm64_b; \
+ UINT f_imm64_c; \
+ DI f_imm64; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_srcbe; \
+ UINT f_op_class; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ UINT word_2; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDDWBE_CODE \
+ length = 16; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 8); \
+ word_2 = GETIMEMUSI (current_cpu, pc + 12); \
+ f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \
+{\
+ f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\
+}\
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDABSW_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDABSW_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDINDWBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_srcbe; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDINDWBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDXWBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_srcbe; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDXWBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_STBBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_srcbe; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_STBBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_JEQIBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_code; \
+ UINT f_srcbe; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_JEQIBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_JEQRBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_dstbe; \
+ UINT f_op_code; \
+ UINT f_srcbe; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_JEQRBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_dstbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_srcbe = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_CALLBE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_code; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_CALLBE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_JA_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_code; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_JA_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_EXIT_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_code; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_EXIT_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#endif /* DEFS_BPFBF_EBPFBE_H */
diff --git a/sim/bpf/defs-le.h b/sim/bpf/defs-le.h
new file mode 100644
index 0000000000..aeb8a44e88
--- /dev/null
+++ b/sim/bpf/defs-le.h
@@ -0,0 +1,383 @@
+/* ISA definitions header for ebpfle.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef DEFS_BPFBF_EBPFLE_H
+#define DEFS_BPFBF_EBPFLE_H
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } sfmt_empty;
+ struct { /* */
+ INT f_imm32;
+ UINT f_srcle;
+ } sfmt_ldindwle;
+ struct { /* */
+ DI f_imm64;
+ UINT f_dstle;
+ } sfmt_lddwle;
+ struct { /* */
+ INT f_imm32;
+ UINT f_dstle;
+ HI f_offset16;
+ } sfmt_stble;
+ struct { /* */
+ UINT f_dstle;
+ UINT f_srcle;
+ HI f_offset16;
+ } sfmt_ldxwle;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_ADDILE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_code; \
+ UINT f_dstle; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDILE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_ADDRLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_code; \
+ UINT f_dstle; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDRLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_NEGLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_code; \
+ UINT f_dstle; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_NEGLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_ENDLELE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_code; \
+ UINT f_dstle; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_ENDLELE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDDWLE_VARS \
+ UINT f_imm64_a; \
+ UINT f_imm64_b; \
+ UINT f_imm64_c; \
+ DI f_imm64; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_dstle; \
+ UINT f_op_class; \
+ /* Contents of trailing part of insn. */ \
+ UINT word_1; \
+ UINT word_2; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDDWLE_CODE \
+ length = 16; \
+ word_1 = GETIMEMUSI (current_cpu, pc + 8); \
+ word_2 = GETIMEMUSI (current_cpu, pc + 12); \
+ f_imm64_a = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_imm64_b = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
+ f_imm64_c = (0|(EXTRACT_LSB0_UINT (word_2, 32, 31, 32) << 0)); \
+{\
+ f_imm64 = ((((((UDI) (UINT) (f_imm64_c))) << (32))) | (((UDI) (UINT) (f_imm64_a))));\
+}\
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDABSW_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDABSW_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDINDWLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_dstle; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDINDWLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_LDXWLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_dstle; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDXWLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_STBLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_mode; \
+ UINT f_op_size; \
+ UINT f_dstle; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_STBLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_mode = EXTRACT_LSB0_LGUINT (insn, 64, 7, 3); \
+ f_op_size = EXTRACT_LSB0_LGUINT (insn, 64, 4, 2); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_JEQILE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_code; \
+ UINT f_dstle; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_JEQILE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_JEQRLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_srcle; \
+ UINT f_op_code; \
+ UINT f_dstle; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_JEQRLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_srcle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 4) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_dstle = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 11, 4) << 0)); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_CALLLE_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_code; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_CALLLE_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_JA_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_code; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_JA_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#define EXTRACT_IFMT_EXIT_VARS \
+ INT f_imm32; \
+ HI f_offset16; \
+ UINT f_regs; \
+ UINT f_op_code; \
+ UINT f_op_src; \
+ UINT f_op_class; \
+ unsigned int length;
+#define EXTRACT_IFMT_EXIT_CODE \
+ length = 8; \
+ f_imm32 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 63, 32) << 0)); \
+ f_offset16 = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 31, 16) << 0)); \
+ f_regs = (0|(EXTRACT_LSB0_LGUINT (insn, 64, 15, 8) << 0)); \
+ f_op_code = EXTRACT_LSB0_LGUINT (insn, 64, 7, 4); \
+ f_op_src = EXTRACT_LSB0_LGUINT (insn, 64, 3, 1); \
+ f_op_class = EXTRACT_LSB0_LGUINT (insn, 64, 2, 3); \
+
+#endif /* DEFS_BPFBF_EBPFLE_H */
diff --git a/sim/bpf/sem-be.c b/sim/bpf/sem-be.c
new file mode 100644
index 0000000000..12b65c77a1
--- /dev/null
+++ b/sim/bpf/sem-be.c
@@ -0,0 +1,3207 @@
+/* Simulator instruction semantics for bpfbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU bpfbf
+#define WANT_CPU_BPFBF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFBE
+ bpfbf_ebpfbe_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFBE
+ bpfbf_ebpfbe_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFBE
+#ifdef DEFINE_SWITCH
+ vpc = bpfbf_ebpfbe_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = bpfbf_ebpfbe_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFBE
+ vpc = bpfbf_ebpfbe_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFBE
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = bpfbf_ebpfbe_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = bpfbf_ebpfbe_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = bpfbf_ebpfbe_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addibe: add $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,addibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addrbe: add $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,addrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ADDDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* add32ibe: add32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,add32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ADDSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* add32rbe: add32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,add32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ADDSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* subibe: sub $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,subibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SUBDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* subrbe: sub $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,subrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SUBDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sub32ibe: sub32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,sub32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SUBSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sub32rbe: sub32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,sub32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SUBSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mulibe: mul $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mulibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MULDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mulrbe: mul $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mulrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MULDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mul32ibe: mul32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mul32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MULSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mul32rbe: mul32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mul32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MULSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* divibe: div $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,divibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = DIVDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* divrbe: div $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,divrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = DIVDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* div32ibe: div32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,div32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = DIVSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* div32rbe: div32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,div32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = DIVSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* oribe: or $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,oribe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ORDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* orrbe: or $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,orrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ORDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* or32ibe: or32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,or32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ORSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* or32rbe: or32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,or32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ORSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andibe: and $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,andibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ANDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andrbe: and $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,andrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ANDDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* and32ibe: and32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,and32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ANDSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* and32rbe: and32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,and32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ANDSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lshibe: lsh $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,lshibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SLLDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lshrbe: lsh $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,lshrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SLLDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lsh32ibe: lsh32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,lsh32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SLLSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lsh32rbe: lsh32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,lsh32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SLLSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rshibe: rsh $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,rshibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRLDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rshrbe: rsh $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,rshrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRLDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rsh32ibe: rsh32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,rsh32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRLSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rsh32rbe: rsh32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,rsh32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRLSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* modibe: mod $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,modibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MODDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* modrbe: mod $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,modrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MODDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mod32ibe: mod32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mod32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MODSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mod32rbe: mod32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mod32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MODSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xoribe: xor $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,xoribe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = XORDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xorrbe: xor $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,xorrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = XORDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xor32ibe: xor32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,xor32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = XORSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xor32rbe: xor32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,xor32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = XORSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arshibe: arsh $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,arshibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRADI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arshrbe: arsh $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,arshrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRADI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arsh32ibe: arsh32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,arsh32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRASI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arsh32rbe: arsh32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,arsh32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRASI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* negbe: neg $dstbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,negbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = NEGDI (CPU (h_gpr[FLD (f_dstbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* neg32be: neg32 $dstbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,neg32be) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = NEGSI (CPU (h_gpr[FLD (f_dstbe)]));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movibe: mov $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,movibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = FLD (f_imm32);
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movrbe: mov $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,movrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = CPU (h_gpr[FLD (f_srcbe)]);
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mov32ibe: mov32 $dstbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mov32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = FLD (f_imm32);
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mov32rbe: mov32 $dstbe,$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,mov32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = CPU (h_gpr[FLD (f_srcbe)]);
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* endlebe: endle $dstbe,$endsize */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,endlebe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = bpfbf_endle (current_cpu, CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* endbebe: endbe $dstbe,$endsize */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,endbebe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = bpfbf_endbe (current_cpu, CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lddwbe: lddw $dstbe,$imm64 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,lddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 16);
+
+ {
+ DI opval = FLD (f_imm64);
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsw: ldabsw $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldabsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsh: ldabsh $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldabsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsb: ldabsb $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldabsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsdw: ldabsdw $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldabsdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldindwbe: ldindw $srcbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldindwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldindhbe: ldindh $srcbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldindhbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldindbbe: ldindb $srcbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldindbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldinddwbe: ldinddw $srcbe,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldinddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxwbe: ldxw $dstbe,[$srcbe+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldxwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxhbe: ldxh $dstbe,[$srcbe+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldxhbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = GETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxbbe: ldxb $dstbe,[$srcbe+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldxbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = GETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxdwbe: ldxdw $dstbe,[$srcbe+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ldxdwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcbe)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstbe)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxwbe: stxw [$dstbe+$offset16],$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stxwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = CPU (h_gpr[FLD (f_srcbe)]);
+ SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxhbe: stxh [$dstbe+$offset16],$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stxhbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = CPU (h_gpr[FLD (f_srcbe)]);
+ SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxbbe: stxb [$dstbe+$offset16],$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stxbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = CPU (h_gpr[FLD (f_srcbe)]);
+ SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxdwbe: stxdw [$dstbe+$offset16],$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stxdwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = CPU (h_gpr[FLD (f_srcbe)]);
+ SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stbbe: stb [$dstbe+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stbbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = FLD (f_imm32);
+ SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sthbe: sth [$dstbe+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,sthbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = FLD (f_imm32);
+ SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stwbe: stw [$dstbe+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = FLD (f_imm32);
+ SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stdwbe: stdw [$dstbe+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,stdwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = FLD (f_imm32);
+ SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* jeqibe: jeq $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jeqibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jeqrbe: jeq $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jeqrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jeq32ibe: jeq32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jeq32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jeq32rbe: jeq32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jeq32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgtibe: jgt $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jgtibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgtrbe: jgt $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jgtrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgt32ibe: jgt32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jgt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgt32rbe: jgt32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jgt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgeibe: jge $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jgeibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgerbe: jge $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jgerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jge32ibe: jge32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jge32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jge32rbe: jge32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jge32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jltibe: jlt $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jltibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jltrbe: jlt $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jltrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jlt32ibe: jlt32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jlt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jlt32rbe: jlt32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jlt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jleibe: jle $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jleibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jlerbe: jle $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jlerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jle32ibe: jle32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jle32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jle32rbe: jle32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jle32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsetibe: jset $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsetibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsetrbe: jset $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsetrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jset32ibe: jset32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jset32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jset32rbe: jset32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jset32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jneibe: jne $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jneibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NEDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jnerbe: jne $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jnerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NEDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jne32ibe: jne32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jne32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NESI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jne32rbe: jne32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jne32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NESI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgtibe: jsgt $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsgtibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgtrbe: jsgt $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsgtrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgt32ibe: jsgt32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsgt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgt32rbe: jsgt32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsgt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgeibe: jsge $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsgeibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgerbe: jsge $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsgerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsge32ibe: jsge32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsge32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GESI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsge32rbe: jsge32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsge32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GESI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsltibe: jslt $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsltibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsltrbe: jslt $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsltrbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jslt32ibe: jslt32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jslt32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTSI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jslt32rbe: jslt32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jslt32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTSI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsleibe: jsle $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsleibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jslerbe: jsle $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jslerbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEDI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsle32ibe: jsle32 $dstbe,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsle32ibe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LESI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsle32rbe: jsle32 $dstbe,$srcbe,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,jsle32rbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LESI (CPU (h_gpr[FLD (f_dstbe)]), CPU (h_gpr[FLD (f_srcbe)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* callbe: call $disp32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,callbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+bpfbf_call (current_cpu, FLD (f_imm32), FLD (f_srcbe));
+
+ return vpc;
+#undef FLD
+}
+
+/* ja: ja $disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,ja) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* exit: exit */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,exit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+bpfbf_exit (current_cpu);
+
+ return vpc;
+#undef FLD
+}
+
+/* xadddwbe: xadddw [$dstbe+$offset16],$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,xadddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+{
+ DI tmp_tmp;
+ tmp_tmp = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)));
+ {
+ DI opval = ADDDI (tmp_tmp, CPU (h_gpr[FLD (f_srcbe)]));
+ SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xaddwbe: xaddw [$dstbe+$offset16],$srcbe */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,xaddwbe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwbe.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)));
+ {
+ SI opval = ADDSI (tmp_tmp, CPU (h_gpr[FLD (f_srcbe)]));
+ SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstbe)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* brkpt: brkpt */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfbe,brkpt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+bpfbf_breakpoint (current_cpu);
+
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { BPFBF_EBPFBE_INSN_X_INVALID, SEM_FN_NAME (bpfbf_ebpfbe,x_invalid) },
+ { BPFBF_EBPFBE_INSN_X_AFTER, SEM_FN_NAME (bpfbf_ebpfbe,x_after) },
+ { BPFBF_EBPFBE_INSN_X_BEFORE, SEM_FN_NAME (bpfbf_ebpfbe,x_before) },
+ { BPFBF_EBPFBE_INSN_X_CTI_CHAIN, SEM_FN_NAME (bpfbf_ebpfbe,x_cti_chain) },
+ { BPFBF_EBPFBE_INSN_X_CHAIN, SEM_FN_NAME (bpfbf_ebpfbe,x_chain) },
+ { BPFBF_EBPFBE_INSN_X_BEGIN, SEM_FN_NAME (bpfbf_ebpfbe,x_begin) },
+ { BPFBF_EBPFBE_INSN_ADDIBE, SEM_FN_NAME (bpfbf_ebpfbe,addibe) },
+ { BPFBF_EBPFBE_INSN_ADDRBE, SEM_FN_NAME (bpfbf_ebpfbe,addrbe) },
+ { BPFBF_EBPFBE_INSN_ADD32IBE, SEM_FN_NAME (bpfbf_ebpfbe,add32ibe) },
+ { BPFBF_EBPFBE_INSN_ADD32RBE, SEM_FN_NAME (bpfbf_ebpfbe,add32rbe) },
+ { BPFBF_EBPFBE_INSN_SUBIBE, SEM_FN_NAME (bpfbf_ebpfbe,subibe) },
+ { BPFBF_EBPFBE_INSN_SUBRBE, SEM_FN_NAME (bpfbf_ebpfbe,subrbe) },
+ { BPFBF_EBPFBE_INSN_SUB32IBE, SEM_FN_NAME (bpfbf_ebpfbe,sub32ibe) },
+ { BPFBF_EBPFBE_INSN_SUB32RBE, SEM_FN_NAME (bpfbf_ebpfbe,sub32rbe) },
+ { BPFBF_EBPFBE_INSN_MULIBE, SEM_FN_NAME (bpfbf_ebpfbe,mulibe) },
+ { BPFBF_EBPFBE_INSN_MULRBE, SEM_FN_NAME (bpfbf_ebpfbe,mulrbe) },
+ { BPFBF_EBPFBE_INSN_MUL32IBE, SEM_FN_NAME (bpfbf_ebpfbe,mul32ibe) },
+ { BPFBF_EBPFBE_INSN_MUL32RBE, SEM_FN_NAME (bpfbf_ebpfbe,mul32rbe) },
+ { BPFBF_EBPFBE_INSN_DIVIBE, SEM_FN_NAME (bpfbf_ebpfbe,divibe) },
+ { BPFBF_EBPFBE_INSN_DIVRBE, SEM_FN_NAME (bpfbf_ebpfbe,divrbe) },
+ { BPFBF_EBPFBE_INSN_DIV32IBE, SEM_FN_NAME (bpfbf_ebpfbe,div32ibe) },
+ { BPFBF_EBPFBE_INSN_DIV32RBE, SEM_FN_NAME (bpfbf_ebpfbe,div32rbe) },
+ { BPFBF_EBPFBE_INSN_ORIBE, SEM_FN_NAME (bpfbf_ebpfbe,oribe) },
+ { BPFBF_EBPFBE_INSN_ORRBE, SEM_FN_NAME (bpfbf_ebpfbe,orrbe) },
+ { BPFBF_EBPFBE_INSN_OR32IBE, SEM_FN_NAME (bpfbf_ebpfbe,or32ibe) },
+ { BPFBF_EBPFBE_INSN_OR32RBE, SEM_FN_NAME (bpfbf_ebpfbe,or32rbe) },
+ { BPFBF_EBPFBE_INSN_ANDIBE, SEM_FN_NAME (bpfbf_ebpfbe,andibe) },
+ { BPFBF_EBPFBE_INSN_ANDRBE, SEM_FN_NAME (bpfbf_ebpfbe,andrbe) },
+ { BPFBF_EBPFBE_INSN_AND32IBE, SEM_FN_NAME (bpfbf_ebpfbe,and32ibe) },
+ { BPFBF_EBPFBE_INSN_AND32RBE, SEM_FN_NAME (bpfbf_ebpfbe,and32rbe) },
+ { BPFBF_EBPFBE_INSN_LSHIBE, SEM_FN_NAME (bpfbf_ebpfbe,lshibe) },
+ { BPFBF_EBPFBE_INSN_LSHRBE, SEM_FN_NAME (bpfbf_ebpfbe,lshrbe) },
+ { BPFBF_EBPFBE_INSN_LSH32IBE, SEM_FN_NAME (bpfbf_ebpfbe,lsh32ibe) },
+ { BPFBF_EBPFBE_INSN_LSH32RBE, SEM_FN_NAME (bpfbf_ebpfbe,lsh32rbe) },
+ { BPFBF_EBPFBE_INSN_RSHIBE, SEM_FN_NAME (bpfbf_ebpfbe,rshibe) },
+ { BPFBF_EBPFBE_INSN_RSHRBE, SEM_FN_NAME (bpfbf_ebpfbe,rshrbe) },
+ { BPFBF_EBPFBE_INSN_RSH32IBE, SEM_FN_NAME (bpfbf_ebpfbe,rsh32ibe) },
+ { BPFBF_EBPFBE_INSN_RSH32RBE, SEM_FN_NAME (bpfbf_ebpfbe,rsh32rbe) },
+ { BPFBF_EBPFBE_INSN_MODIBE, SEM_FN_NAME (bpfbf_ebpfbe,modibe) },
+ { BPFBF_EBPFBE_INSN_MODRBE, SEM_FN_NAME (bpfbf_ebpfbe,modrbe) },
+ { BPFBF_EBPFBE_INSN_MOD32IBE, SEM_FN_NAME (bpfbf_ebpfbe,mod32ibe) },
+ { BPFBF_EBPFBE_INSN_MOD32RBE, SEM_FN_NAME (bpfbf_ebpfbe,mod32rbe) },
+ { BPFBF_EBPFBE_INSN_XORIBE, SEM_FN_NAME (bpfbf_ebpfbe,xoribe) },
+ { BPFBF_EBPFBE_INSN_XORRBE, SEM_FN_NAME (bpfbf_ebpfbe,xorrbe) },
+ { BPFBF_EBPFBE_INSN_XOR32IBE, SEM_FN_NAME (bpfbf_ebpfbe,xor32ibe) },
+ { BPFBF_EBPFBE_INSN_XOR32RBE, SEM_FN_NAME (bpfbf_ebpfbe,xor32rbe) },
+ { BPFBF_EBPFBE_INSN_ARSHIBE, SEM_FN_NAME (bpfbf_ebpfbe,arshibe) },
+ { BPFBF_EBPFBE_INSN_ARSHRBE, SEM_FN_NAME (bpfbf_ebpfbe,arshrbe) },
+ { BPFBF_EBPFBE_INSN_ARSH32IBE, SEM_FN_NAME (bpfbf_ebpfbe,arsh32ibe) },
+ { BPFBF_EBPFBE_INSN_ARSH32RBE, SEM_FN_NAME (bpfbf_ebpfbe,arsh32rbe) },
+ { BPFBF_EBPFBE_INSN_NEGBE, SEM_FN_NAME (bpfbf_ebpfbe,negbe) },
+ { BPFBF_EBPFBE_INSN_NEG32BE, SEM_FN_NAME (bpfbf_ebpfbe,neg32be) },
+ { BPFBF_EBPFBE_INSN_MOVIBE, SEM_FN_NAME (bpfbf_ebpfbe,movibe) },
+ { BPFBF_EBPFBE_INSN_MOVRBE, SEM_FN_NAME (bpfbf_ebpfbe,movrbe) },
+ { BPFBF_EBPFBE_INSN_MOV32IBE, SEM_FN_NAME (bpfbf_ebpfbe,mov32ibe) },
+ { BPFBF_EBPFBE_INSN_MOV32RBE, SEM_FN_NAME (bpfbf_ebpfbe,mov32rbe) },
+ { BPFBF_EBPFBE_INSN_ENDLEBE, SEM_FN_NAME (bpfbf_ebpfbe,endlebe) },
+ { BPFBF_EBPFBE_INSN_ENDBEBE, SEM_FN_NAME (bpfbf_ebpfbe,endbebe) },
+ { BPFBF_EBPFBE_INSN_LDDWBE, SEM_FN_NAME (bpfbf_ebpfbe,lddwbe) },
+ { BPFBF_EBPFBE_INSN_LDABSW, SEM_FN_NAME (bpfbf_ebpfbe,ldabsw) },
+ { BPFBF_EBPFBE_INSN_LDABSH, SEM_FN_NAME (bpfbf_ebpfbe,ldabsh) },
+ { BPFBF_EBPFBE_INSN_LDABSB, SEM_FN_NAME (bpfbf_ebpfbe,ldabsb) },
+ { BPFBF_EBPFBE_INSN_LDABSDW, SEM_FN_NAME (bpfbf_ebpfbe,ldabsdw) },
+ { BPFBF_EBPFBE_INSN_LDINDWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldindwbe) },
+ { BPFBF_EBPFBE_INSN_LDINDHBE, SEM_FN_NAME (bpfbf_ebpfbe,ldindhbe) },
+ { BPFBF_EBPFBE_INSN_LDINDBBE, SEM_FN_NAME (bpfbf_ebpfbe,ldindbbe) },
+ { BPFBF_EBPFBE_INSN_LDINDDWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldinddwbe) },
+ { BPFBF_EBPFBE_INSN_LDXWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxwbe) },
+ { BPFBF_EBPFBE_INSN_LDXHBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxhbe) },
+ { BPFBF_EBPFBE_INSN_LDXBBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxbbe) },
+ { BPFBF_EBPFBE_INSN_LDXDWBE, SEM_FN_NAME (bpfbf_ebpfbe,ldxdwbe) },
+ { BPFBF_EBPFBE_INSN_STXWBE, SEM_FN_NAME (bpfbf_ebpfbe,stxwbe) },
+ { BPFBF_EBPFBE_INSN_STXHBE, SEM_FN_NAME (bpfbf_ebpfbe,stxhbe) },
+ { BPFBF_EBPFBE_INSN_STXBBE, SEM_FN_NAME (bpfbf_ebpfbe,stxbbe) },
+ { BPFBF_EBPFBE_INSN_STXDWBE, SEM_FN_NAME (bpfbf_ebpfbe,stxdwbe) },
+ { BPFBF_EBPFBE_INSN_STBBE, SEM_FN_NAME (bpfbf_ebpfbe,stbbe) },
+ { BPFBF_EBPFBE_INSN_STHBE, SEM_FN_NAME (bpfbf_ebpfbe,sthbe) },
+ { BPFBF_EBPFBE_INSN_STWBE, SEM_FN_NAME (bpfbf_ebpfbe,stwbe) },
+ { BPFBF_EBPFBE_INSN_STDWBE, SEM_FN_NAME (bpfbf_ebpfbe,stdwbe) },
+ { BPFBF_EBPFBE_INSN_JEQIBE, SEM_FN_NAME (bpfbf_ebpfbe,jeqibe) },
+ { BPFBF_EBPFBE_INSN_JEQRBE, SEM_FN_NAME (bpfbf_ebpfbe,jeqrbe) },
+ { BPFBF_EBPFBE_INSN_JEQ32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jeq32ibe) },
+ { BPFBF_EBPFBE_INSN_JEQ32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jeq32rbe) },
+ { BPFBF_EBPFBE_INSN_JGTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jgtibe) },
+ { BPFBF_EBPFBE_INSN_JGTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jgtrbe) },
+ { BPFBF_EBPFBE_INSN_JGT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jgt32ibe) },
+ { BPFBF_EBPFBE_INSN_JGT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jgt32rbe) },
+ { BPFBF_EBPFBE_INSN_JGEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jgeibe) },
+ { BPFBF_EBPFBE_INSN_JGERBE, SEM_FN_NAME (bpfbf_ebpfbe,jgerbe) },
+ { BPFBF_EBPFBE_INSN_JGE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jge32ibe) },
+ { BPFBF_EBPFBE_INSN_JGE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jge32rbe) },
+ { BPFBF_EBPFBE_INSN_JLTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jltibe) },
+ { BPFBF_EBPFBE_INSN_JLTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jltrbe) },
+ { BPFBF_EBPFBE_INSN_JLT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jlt32ibe) },
+ { BPFBF_EBPFBE_INSN_JLT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jlt32rbe) },
+ { BPFBF_EBPFBE_INSN_JLEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jleibe) },
+ { BPFBF_EBPFBE_INSN_JLERBE, SEM_FN_NAME (bpfbf_ebpfbe,jlerbe) },
+ { BPFBF_EBPFBE_INSN_JLE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jle32ibe) },
+ { BPFBF_EBPFBE_INSN_JLE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jle32rbe) },
+ { BPFBF_EBPFBE_INSN_JSETIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsetibe) },
+ { BPFBF_EBPFBE_INSN_JSETRBE, SEM_FN_NAME (bpfbf_ebpfbe,jsetrbe) },
+ { BPFBF_EBPFBE_INSN_JSET32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jset32ibe) },
+ { BPFBF_EBPFBE_INSN_JSET32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jset32rbe) },
+ { BPFBF_EBPFBE_INSN_JNEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jneibe) },
+ { BPFBF_EBPFBE_INSN_JNERBE, SEM_FN_NAME (bpfbf_ebpfbe,jnerbe) },
+ { BPFBF_EBPFBE_INSN_JNE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jne32ibe) },
+ { BPFBF_EBPFBE_INSN_JNE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jne32rbe) },
+ { BPFBF_EBPFBE_INSN_JSGTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgtibe) },
+ { BPFBF_EBPFBE_INSN_JSGTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgtrbe) },
+ { BPFBF_EBPFBE_INSN_JSGT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgt32ibe) },
+ { BPFBF_EBPFBE_INSN_JSGT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgt32rbe) },
+ { BPFBF_EBPFBE_INSN_JSGEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgeibe) },
+ { BPFBF_EBPFBE_INSN_JSGERBE, SEM_FN_NAME (bpfbf_ebpfbe,jsgerbe) },
+ { BPFBF_EBPFBE_INSN_JSGE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jsge32ibe) },
+ { BPFBF_EBPFBE_INSN_JSGE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jsge32rbe) },
+ { BPFBF_EBPFBE_INSN_JSLTIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsltibe) },
+ { BPFBF_EBPFBE_INSN_JSLTRBE, SEM_FN_NAME (bpfbf_ebpfbe,jsltrbe) },
+ { BPFBF_EBPFBE_INSN_JSLT32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jslt32ibe) },
+ { BPFBF_EBPFBE_INSN_JSLT32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jslt32rbe) },
+ { BPFBF_EBPFBE_INSN_JSLEIBE, SEM_FN_NAME (bpfbf_ebpfbe,jsleibe) },
+ { BPFBF_EBPFBE_INSN_JSLERBE, SEM_FN_NAME (bpfbf_ebpfbe,jslerbe) },
+ { BPFBF_EBPFBE_INSN_JSLE32IBE, SEM_FN_NAME (bpfbf_ebpfbe,jsle32ibe) },
+ { BPFBF_EBPFBE_INSN_JSLE32RBE, SEM_FN_NAME (bpfbf_ebpfbe,jsle32rbe) },
+ { BPFBF_EBPFBE_INSN_CALLBE, SEM_FN_NAME (bpfbf_ebpfbe,callbe) },
+ { BPFBF_EBPFBE_INSN_JA, SEM_FN_NAME (bpfbf_ebpfbe,ja) },
+ { BPFBF_EBPFBE_INSN_EXIT, SEM_FN_NAME (bpfbf_ebpfbe,exit) },
+ { BPFBF_EBPFBE_INSN_XADDDWBE, SEM_FN_NAME (bpfbf_ebpfbe,xadddwbe) },
+ { BPFBF_EBPFBE_INSN_XADDWBE, SEM_FN_NAME (bpfbf_ebpfbe,xaddwbe) },
+ { BPFBF_EBPFBE_INSN_BRKPT, SEM_FN_NAME (bpfbf_ebpfbe,brkpt) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (bpfbf_ebpfbe,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (bpfbf_ebpfbe,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (bpfbf_ebpfbe,x_invalid);
+#endif
+ }
+}
+
diff --git a/sim/bpf/sem-le.c b/sim/bpf/sem-le.c
new file mode 100644
index 0000000000..8bb1debfb7
--- /dev/null
+++ b/sim/bpf/sem-le.c
@@ -0,0 +1,3207 @@
+/* Simulator instruction semantics for bpfbf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+ This file is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program; if not, write to the Free Software Foundation, Inc.,
+ 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#define WANT_CPU bpfbf
+#define WANT_CPU_BPFBF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFLE
+ bpfbf_ebpfle_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFLE
+ bpfbf_ebpfle_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFLE
+#ifdef DEFINE_SWITCH
+ vpc = bpfbf_ebpfle_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = bpfbf_ebpfle_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFLE
+ vpc = bpfbf_ebpfle_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_BPFBF_EBPFLE
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = bpfbf_ebpfle_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = bpfbf_ebpfle_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = bpfbf_ebpfle_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addile: add $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,addile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addrle: add $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,addrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ADDDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* add32ile: add32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,add32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ADDSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* add32rle: add32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,add32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ADDSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* subile: sub $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,subile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SUBDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* subrle: sub $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,subrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SUBDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sub32ile: sub32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,sub32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SUBSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sub32rle: sub32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,sub32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SUBSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mulile: mul $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mulile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MULDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mulrle: mul $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mulrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MULDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mul32ile: mul32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mul32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MULSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mul32rle: mul32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mul32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MULSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* divile: div $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,divile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = DIVDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* divrle: div $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,divrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = DIVDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* div32ile: div32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,div32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = DIVSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* div32rle: div32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,div32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = DIVSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* orile: or $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,orile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ORDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* orrle: or $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,orrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ORDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* or32ile: or32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,or32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ORSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* or32rle: or32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,or32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ORSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andile: and $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,andile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ANDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andrle: and $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,andrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ANDDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* and32ile: and32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,and32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ANDSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* and32rle: and32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,and32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = ANDSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lshile: lsh $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,lshile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SLLDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lshrle: lsh $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,lshrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SLLDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lsh32ile: lsh32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,lsh32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SLLSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lsh32rle: lsh32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,lsh32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SLLSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rshile: rsh $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,rshile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRLDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rshrle: rsh $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,rshrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRLDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rsh32ile: rsh32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,rsh32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRLSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rsh32rle: rsh32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,rsh32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRLSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* modile: mod $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,modile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MODDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* modrle: mod $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,modrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = MODDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mod32ile: mod32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mod32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MODSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mod32rle: mod32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mod32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = MODSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xorile: xor $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,xorile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = XORDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xorrle: xor $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,xorrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = XORDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xor32ile: xor32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,xor32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = XORSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xor32rle: xor32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,xor32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = XORSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arshile: arsh $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,arshile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRADI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arshrle: arsh $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,arshrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = SRADI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arsh32ile: arsh32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,arsh32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRASI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* arsh32rle: arsh32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,arsh32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = SRASI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* negle: neg $dstle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,negle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = NEGDI (CPU (h_gpr[FLD (f_dstle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* neg32le: neg32 $dstle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,neg32le) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = NEGSI (CPU (h_gpr[FLD (f_dstle)]));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movile: mov $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,movile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = FLD (f_imm32);
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movrle: mov $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,movrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = CPU (h_gpr[FLD (f_srcle)]);
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mov32ile: mov32 $dstle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mov32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = FLD (f_imm32);
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mov32rle: mov32 $dstle,$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,mov32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ USI opval = CPU (h_gpr[FLD (f_srcle)]);
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* endlele: endle $dstle,$endsize */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,endlele) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = bpfbf_endle (current_cpu, CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* endbele: endbe $dstle,$endsize */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,endbele) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = bpfbf_endbe (current_cpu, CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lddwle: lddw $dstle,$imm64 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,lddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 16);
+
+ {
+ DI opval = FLD (f_imm64);
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsw: ldabsw $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldabsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsh: ldabsh $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldabsh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsb: ldabsb $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldabsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldabsdw: ldabsdw $imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldabsdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), FLD (f_imm32)));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldindwle: ldindw $srcle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldindwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldindhle: ldindh $srcle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldindhle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = GETMEMHI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldindble: ldindb $srcle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldindble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = GETMEMQI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldinddwle: ldinddw $srcle,$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldinddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[((UINT) 6)]), bpfbf_skb_data_offset (current_cpu))), ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_imm32))));
+ CPU (h_gpr[((UINT) 0)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxwle: ldxw $dstle,[$srcle+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldxwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxhle: ldxh $dstle,[$srcle+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldxhle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = GETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxble: ldxb $dstle,[$srcle+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldxble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = GETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxdwle: ldxdw $dstle,[$srcle+$offset16] */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ldxdwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_srcle)]), FLD (f_offset16)));
+ CPU (h_gpr[FLD (f_dstle)]) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxwle: stxw [$dstle+$offset16],$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stxwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = CPU (h_gpr[FLD (f_srcle)]);
+ SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxhle: stxh [$dstle+$offset16],$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stxhle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = CPU (h_gpr[FLD (f_srcle)]);
+ SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxble: stxb [$dstle+$offset16],$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stxble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = CPU (h_gpr[FLD (f_srcle)]);
+ SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxdwle: stxdw [$dstle+$offset16],$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stxdwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = CPU (h_gpr[FLD (f_srcle)]);
+ SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stble: stb [$dstle+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stble) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ QI opval = FLD (f_imm32);
+ SETMEMQI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sthle: sth [$dstle+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,sthle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ HI opval = FLD (f_imm32);
+ SETMEMHI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stwle: stw [$dstle+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ SI opval = FLD (f_imm32);
+ SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stdwle: stdw [$dstle+$offset16],$imm32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,stdwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = FLD (f_imm32);
+ SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* jeqile: jeq $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jeqile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jeqrle: jeq $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jeqrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jeq32ile: jeq32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jeq32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jeq32rle: jeq32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jeq32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (EQSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgtile: jgt $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jgtile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgtrle: jgt $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jgtrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgt32ile: jgt32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jgt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgt32rle: jgt32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jgt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgeile: jge $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jgeile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jgerle: jge $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jgerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jge32ile: jge32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jge32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jge32rle: jge32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jge32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jltile: jlt $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jltile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jltrle: jlt $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jltrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jlt32ile: jlt32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jlt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jlt32rle: jlt32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jlt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jleile: jle $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jleile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jlerle: jle $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jlerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jle32ile: jle32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jle32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jle32rle: jle32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jle32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEUSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsetile: jset $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsetile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsetrle: jset $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsetrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jset32ile: jset32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jset32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jset32rle: jset32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jset32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (ANDSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jneile: jne $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jneile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NEDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jnerle: jne $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jnerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NEDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jne32ile: jne32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jne32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NESI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jne32rle: jne32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jne32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (NESI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgtile: jsgt $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsgtile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgtrle: jsgt $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsgtrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgt32ile: jsgt32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsgt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgt32rle: jsgt32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsgt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GTSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgeile: jsge $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsgeile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsgerle: jsge $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsgerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GEDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsge32ile: jsge32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsge32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GESI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsge32rle: jsge32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsge32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (GESI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsltile: jslt $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsltile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsltrle: jslt $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsltrle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jslt32ile: jslt32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jslt32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTSI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jslt32rle: jslt32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jslt32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LTSI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsleile: jsle $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsleile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jslerle: jsle $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jslerle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LEDI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsle32ile: jsle32 $dstle,$imm32,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsle32ile) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LESI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_imm32))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsle32rle: jsle32 $dstle,$srcle,$disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,jsle32rle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+if (LESI (CPU (h_gpr[FLD (f_dstle)]), CPU (h_gpr[FLD (f_srcle)]))) {
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* callle: call $disp32 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,callle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldindwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+bpfbf_call (current_cpu, FLD (f_imm32), FLD (f_srcle));
+
+ return vpc;
+#undef FLD
+}
+
+/* ja: ja $disp16 */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,ja) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stble.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+ {
+ DI opval = ADDDI (pc, MULDI (ADDHI (FLD (f_offset16), 1), 8));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* exit: exit */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,exit) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+bpfbf_exit (current_cpu);
+
+ return vpc;
+#undef FLD
+}
+
+/* xadddwle: xadddw [$dstle+$offset16],$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,xadddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+{
+ DI tmp_tmp;
+ tmp_tmp = GETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)));
+ {
+ DI opval = ADDDI (tmp_tmp, CPU (h_gpr[FLD (f_srcle)]));
+ SETMEMDI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xaddwle: xaddw [$dstle+$offset16],$srcle */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,xaddwle) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldxwle.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+{
+ SI tmp_tmp;
+ tmp_tmp = GETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)));
+ {
+ SI opval = ADDSI (tmp_tmp, CPU (h_gpr[FLD (f_srcle)]));
+ SETMEMSI (current_cpu, pc, ADDDI (CPU (h_gpr[FLD (f_dstle)]), FLD (f_offset16)), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* brkpt: brkpt */
+
+static SEM_PC
+SEM_FN_NAME (bpfbf_ebpfle,brkpt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 8);
+
+bpfbf_breakpoint (current_cpu);
+
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { BPFBF_EBPFLE_INSN_X_INVALID, SEM_FN_NAME (bpfbf_ebpfle,x_invalid) },
+ { BPFBF_EBPFLE_INSN_X_AFTER, SEM_FN_NAME (bpfbf_ebpfle,x_after) },
+ { BPFBF_EBPFLE_INSN_X_BEFORE, SEM_FN_NAME (bpfbf_ebpfle,x_before) },
+ { BPFBF_EBPFLE_INSN_X_CTI_CHAIN, SEM_FN_NAME (bpfbf_ebpfle,x_cti_chain) },
+ { BPFBF_EBPFLE_INSN_X_CHAIN, SEM_FN_NAME (bpfbf_ebpfle,x_chain) },
+ { BPFBF_EBPFLE_INSN_X_BEGIN, SEM_FN_NAME (bpfbf_ebpfle,x_begin) },
+ { BPFBF_EBPFLE_INSN_ADDILE, SEM_FN_NAME (bpfbf_ebpfle,addile) },
+ { BPFBF_EBPFLE_INSN_ADDRLE, SEM_FN_NAME (bpfbf_ebpfle,addrle) },
+ { BPFBF_EBPFLE_INSN_ADD32ILE, SEM_FN_NAME (bpfbf_ebpfle,add32ile) },
+ { BPFBF_EBPFLE_INSN_ADD32RLE, SEM_FN_NAME (bpfbf_ebpfle,add32rle) },
+ { BPFBF_EBPFLE_INSN_SUBILE, SEM_FN_NAME (bpfbf_ebpfle,subile) },
+ { BPFBF_EBPFLE_INSN_SUBRLE, SEM_FN_NAME (bpfbf_ebpfle,subrle) },
+ { BPFBF_EBPFLE_INSN_SUB32ILE, SEM_FN_NAME (bpfbf_ebpfle,sub32ile) },
+ { BPFBF_EBPFLE_INSN_SUB32RLE, SEM_FN_NAME (bpfbf_ebpfle,sub32rle) },
+ { BPFBF_EBPFLE_INSN_MULILE, SEM_FN_NAME (bpfbf_ebpfle,mulile) },
+ { BPFBF_EBPFLE_INSN_MULRLE, SEM_FN_NAME (bpfbf_ebpfle,mulrle) },
+ { BPFBF_EBPFLE_INSN_MUL32ILE, SEM_FN_NAME (bpfbf_ebpfle,mul32ile) },
+ { BPFBF_EBPFLE_INSN_MUL32RLE, SEM_FN_NAME (bpfbf_ebpfle,mul32rle) },
+ { BPFBF_EBPFLE_INSN_DIVILE, SEM_FN_NAME (bpfbf_ebpfle,divile) },
+ { BPFBF_EBPFLE_INSN_DIVRLE, SEM_FN_NAME (bpfbf_ebpfle,divrle) },
+ { BPFBF_EBPFLE_INSN_DIV32ILE, SEM_FN_NAME (bpfbf_ebpfle,div32ile) },
+ { BPFBF_EBPFLE_INSN_DIV32RLE, SEM_FN_NAME (bpfbf_ebpfle,div32rle) },
+ { BPFBF_EBPFLE_INSN_ORILE, SEM_FN_NAME (bpfbf_ebpfle,orile) },
+ { BPFBF_EBPFLE_INSN_ORRLE, SEM_FN_NAME (bpfbf_ebpfle,orrle) },
+ { BPFBF_EBPFLE_INSN_OR32ILE, SEM_FN_NAME (bpfbf_ebpfle,or32ile) },
+ { BPFBF_EBPFLE_INSN_OR32RLE, SEM_FN_NAME (bpfbf_ebpfle,or32rle) },
+ { BPFBF_EBPFLE_INSN_ANDILE, SEM_FN_NAME (bpfbf_ebpfle,andile) },
+ { BPFBF_EBPFLE_INSN_ANDRLE, SEM_FN_NAME (bpfbf_ebpfle,andrle) },
+ { BPFBF_EBPFLE_INSN_AND32ILE, SEM_FN_NAME (bpfbf_ebpfle,and32ile) },
+ { BPFBF_EBPFLE_INSN_AND32RLE, SEM_FN_NAME (bpfbf_ebpfle,and32rle) },
+ { BPFBF_EBPFLE_INSN_LSHILE, SEM_FN_NAME (bpfbf_ebpfle,lshile) },
+ { BPFBF_EBPFLE_INSN_LSHRLE, SEM_FN_NAME (bpfbf_ebpfle,lshrle) },
+ { BPFBF_EBPFLE_INSN_LSH32ILE, SEM_FN_NAME (bpfbf_ebpfle,lsh32ile) },
+ { BPFBF_EBPFLE_INSN_LSH32RLE, SEM_FN_NAME (bpfbf_ebpfle,lsh32rle) },
+ { BPFBF_EBPFLE_INSN_RSHILE, SEM_FN_NAME (bpfbf_ebpfle,rshile) },
+ { BPFBF_EBPFLE_INSN_RSHRLE, SEM_FN_NAME (bpfbf_ebpfle,rshrle) },
+ { BPFBF_EBPFLE_INSN_RSH32ILE, SEM_FN_NAME (bpfbf_ebpfle,rsh32ile) },
+ { BPFBF_EBPFLE_INSN_RSH32RLE, SEM_FN_NAME (bpfbf_ebpfle,rsh32rle) },
+ { BPFBF_EBPFLE_INSN_MODILE, SEM_FN_NAME (bpfbf_ebpfle,modile) },
+ { BPFBF_EBPFLE_INSN_MODRLE, SEM_FN_NAME (bpfbf_ebpfle,modrle) },
+ { BPFBF_EBPFLE_INSN_MOD32ILE, SEM_FN_NAME (bpfbf_ebpfle,mod32ile) },
+ { BPFBF_EBPFLE_INSN_MOD32RLE, SEM_FN_NAME (bpfbf_ebpfle,mod32rle) },
+ { BPFBF_EBPFLE_INSN_XORILE, SEM_FN_NAME (bpfbf_ebpfle,xorile) },
+ { BPFBF_EBPFLE_INSN_XORRLE, SEM_FN_NAME (bpfbf_ebpfle,xorrle) },
+ { BPFBF_EBPFLE_INSN_XOR32ILE, SEM_FN_NAME (bpfbf_ebpfle,xor32ile) },
+ { BPFBF_EBPFLE_INSN_XOR32RLE, SEM_FN_NAME (bpfbf_ebpfle,xor32rle) },
+ { BPFBF_EBPFLE_INSN_ARSHILE, SEM_FN_NAME (bpfbf_ebpfle,arshile) },
+ { BPFBF_EBPFLE_INSN_ARSHRLE, SEM_FN_NAME (bpfbf_ebpfle,arshrle) },
+ { BPFBF_EBPFLE_INSN_ARSH32ILE, SEM_FN_NAME (bpfbf_ebpfle,arsh32ile) },
+ { BPFBF_EBPFLE_INSN_ARSH32RLE, SEM_FN_NAME (bpfbf_ebpfle,arsh32rle) },
+ { BPFBF_EBPFLE_INSN_NEGLE, SEM_FN_NAME (bpfbf_ebpfle,negle) },
+ { BPFBF_EBPFLE_INSN_NEG32LE, SEM_FN_NAME (bpfbf_ebpfle,neg32le) },
+ { BPFBF_EBPFLE_INSN_MOVILE, SEM_FN_NAME (bpfbf_ebpfle,movile) },
+ { BPFBF_EBPFLE_INSN_MOVRLE, SEM_FN_NAME (bpfbf_ebpfle,movrle) },
+ { BPFBF_EBPFLE_INSN_MOV32ILE, SEM_FN_NAME (bpfbf_ebpfle,mov32ile) },
+ { BPFBF_EBPFLE_INSN_MOV32RLE, SEM_FN_NAME (bpfbf_ebpfle,mov32rle) },
+ { BPFBF_EBPFLE_INSN_ENDLELE, SEM_FN_NAME (bpfbf_ebpfle,endlele) },
+ { BPFBF_EBPFLE_INSN_ENDBELE, SEM_FN_NAME (bpfbf_ebpfle,endbele) },
+ { BPFBF_EBPFLE_INSN_LDDWLE, SEM_FN_NAME (bpfbf_ebpfle,lddwle) },
+ { BPFBF_EBPFLE_INSN_LDABSW, SEM_FN_NAME (bpfbf_ebpfle,ldabsw) },
+ { BPFBF_EBPFLE_INSN_LDABSH, SEM_FN_NAME (bpfbf_ebpfle,ldabsh) },
+ { BPFBF_EBPFLE_INSN_LDABSB, SEM_FN_NAME (bpfbf_ebpfle,ldabsb) },
+ { BPFBF_EBPFLE_INSN_LDABSDW, SEM_FN_NAME (bpfbf_ebpfle,ldabsdw) },
+ { BPFBF_EBPFLE_INSN_LDINDWLE, SEM_FN_NAME (bpfbf_ebpfle,ldindwle) },
+ { BPFBF_EBPFLE_INSN_LDINDHLE, SEM_FN_NAME (bpfbf_ebpfle,ldindhle) },
+ { BPFBF_EBPFLE_INSN_LDINDBLE, SEM_FN_NAME (bpfbf_ebpfle,ldindble) },
+ { BPFBF_EBPFLE_INSN_LDINDDWLE, SEM_FN_NAME (bpfbf_ebpfle,ldinddwle) },
+ { BPFBF_EBPFLE_INSN_LDXWLE, SEM_FN_NAME (bpfbf_ebpfle,ldxwle) },
+ { BPFBF_EBPFLE_INSN_LDXHLE, SEM_FN_NAME (bpfbf_ebpfle,ldxhle) },
+ { BPFBF_EBPFLE_INSN_LDXBLE, SEM_FN_NAME (bpfbf_ebpfle,ldxble) },
+ { BPFBF_EBPFLE_INSN_LDXDWLE, SEM_FN_NAME (bpfbf_ebpfle,ldxdwle) },
+ { BPFBF_EBPFLE_INSN_STXWLE, SEM_FN_NAME (bpfbf_ebpfle,stxwle) },
+ { BPFBF_EBPFLE_INSN_STXHLE, SEM_FN_NAME (bpfbf_ebpfle,stxhle) },
+ { BPFBF_EBPFLE_INSN_STXBLE, SEM_FN_NAME (bpfbf_ebpfle,stxble) },
+ { BPFBF_EBPFLE_INSN_STXDWLE, SEM_FN_NAME (bpfbf_ebpfle,stxdwle) },
+ { BPFBF_EBPFLE_INSN_STBLE, SEM_FN_NAME (bpfbf_ebpfle,stble) },
+ { BPFBF_EBPFLE_INSN_STHLE, SEM_FN_NAME (bpfbf_ebpfle,sthle) },
+ { BPFBF_EBPFLE_INSN_STWLE, SEM_FN_NAME (bpfbf_ebpfle,stwle) },
+ { BPFBF_EBPFLE_INSN_STDWLE, SEM_FN_NAME (bpfbf_ebpfle,stdwle) },
+ { BPFBF_EBPFLE_INSN_JEQILE, SEM_FN_NAME (bpfbf_ebpfle,jeqile) },
+ { BPFBF_EBPFLE_INSN_JEQRLE, SEM_FN_NAME (bpfbf_ebpfle,jeqrle) },
+ { BPFBF_EBPFLE_INSN_JEQ32ILE, SEM_FN_NAME (bpfbf_ebpfle,jeq32ile) },
+ { BPFBF_EBPFLE_INSN_JEQ32RLE, SEM_FN_NAME (bpfbf_ebpfle,jeq32rle) },
+ { BPFBF_EBPFLE_INSN_JGTILE, SEM_FN_NAME (bpfbf_ebpfle,jgtile) },
+ { BPFBF_EBPFLE_INSN_JGTRLE, SEM_FN_NAME (bpfbf_ebpfle,jgtrle) },
+ { BPFBF_EBPFLE_INSN_JGT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jgt32ile) },
+ { BPFBF_EBPFLE_INSN_JGT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jgt32rle) },
+ { BPFBF_EBPFLE_INSN_JGEILE, SEM_FN_NAME (bpfbf_ebpfle,jgeile) },
+ { BPFBF_EBPFLE_INSN_JGERLE, SEM_FN_NAME (bpfbf_ebpfle,jgerle) },
+ { BPFBF_EBPFLE_INSN_JGE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jge32ile) },
+ { BPFBF_EBPFLE_INSN_JGE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jge32rle) },
+ { BPFBF_EBPFLE_INSN_JLTILE, SEM_FN_NAME (bpfbf_ebpfle,jltile) },
+ { BPFBF_EBPFLE_INSN_JLTRLE, SEM_FN_NAME (bpfbf_ebpfle,jltrle) },
+ { BPFBF_EBPFLE_INSN_JLT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jlt32ile) },
+ { BPFBF_EBPFLE_INSN_JLT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jlt32rle) },
+ { BPFBF_EBPFLE_INSN_JLEILE, SEM_FN_NAME (bpfbf_ebpfle,jleile) },
+ { BPFBF_EBPFLE_INSN_JLERLE, SEM_FN_NAME (bpfbf_ebpfle,jlerle) },
+ { BPFBF_EBPFLE_INSN_JLE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jle32ile) },
+ { BPFBF_EBPFLE_INSN_JLE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jle32rle) },
+ { BPFBF_EBPFLE_INSN_JSETILE, SEM_FN_NAME (bpfbf_ebpfle,jsetile) },
+ { BPFBF_EBPFLE_INSN_JSETRLE, SEM_FN_NAME (bpfbf_ebpfle,jsetrle) },
+ { BPFBF_EBPFLE_INSN_JSET32ILE, SEM_FN_NAME (bpfbf_ebpfle,jset32ile) },
+ { BPFBF_EBPFLE_INSN_JSET32RLE, SEM_FN_NAME (bpfbf_ebpfle,jset32rle) },
+ { BPFBF_EBPFLE_INSN_JNEILE, SEM_FN_NAME (bpfbf_ebpfle,jneile) },
+ { BPFBF_EBPFLE_INSN_JNERLE, SEM_FN_NAME (bpfbf_ebpfle,jnerle) },
+ { BPFBF_EBPFLE_INSN_JNE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jne32ile) },
+ { BPFBF_EBPFLE_INSN_JNE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jne32rle) },
+ { BPFBF_EBPFLE_INSN_JSGTILE, SEM_FN_NAME (bpfbf_ebpfle,jsgtile) },
+ { BPFBF_EBPFLE_INSN_JSGTRLE, SEM_FN_NAME (bpfbf_ebpfle,jsgtrle) },
+ { BPFBF_EBPFLE_INSN_JSGT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jsgt32ile) },
+ { BPFBF_EBPFLE_INSN_JSGT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jsgt32rle) },
+ { BPFBF_EBPFLE_INSN_JSGEILE, SEM_FN_NAME (bpfbf_ebpfle,jsgeile) },
+ { BPFBF_EBPFLE_INSN_JSGERLE, SEM_FN_NAME (bpfbf_ebpfle,jsgerle) },
+ { BPFBF_EBPFLE_INSN_JSGE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jsge32ile) },
+ { BPFBF_EBPFLE_INSN_JSGE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jsge32rle) },
+ { BPFBF_EBPFLE_INSN_JSLTILE, SEM_FN_NAME (bpfbf_ebpfle,jsltile) },
+ { BPFBF_EBPFLE_INSN_JSLTRLE, SEM_FN_NAME (bpfbf_ebpfle,jsltrle) },
+ { BPFBF_EBPFLE_INSN_JSLT32ILE, SEM_FN_NAME (bpfbf_ebpfle,jslt32ile) },
+ { BPFBF_EBPFLE_INSN_JSLT32RLE, SEM_FN_NAME (bpfbf_ebpfle,jslt32rle) },
+ { BPFBF_EBPFLE_INSN_JSLEILE, SEM_FN_NAME (bpfbf_ebpfle,jsleile) },
+ { BPFBF_EBPFLE_INSN_JSLERLE, SEM_FN_NAME (bpfbf_ebpfle,jslerle) },
+ { BPFBF_EBPFLE_INSN_JSLE32ILE, SEM_FN_NAME (bpfbf_ebpfle,jsle32ile) },
+ { BPFBF_EBPFLE_INSN_JSLE32RLE, SEM_FN_NAME (bpfbf_ebpfle,jsle32rle) },
+ { BPFBF_EBPFLE_INSN_CALLLE, SEM_FN_NAME (bpfbf_ebpfle,callle) },
+ { BPFBF_EBPFLE_INSN_JA, SEM_FN_NAME (bpfbf_ebpfle,ja) },
+ { BPFBF_EBPFLE_INSN_EXIT, SEM_FN_NAME (bpfbf_ebpfle,exit) },
+ { BPFBF_EBPFLE_INSN_XADDDWLE, SEM_FN_NAME (bpfbf_ebpfle,xadddwle) },
+ { BPFBF_EBPFLE_INSN_XADDWLE, SEM_FN_NAME (bpfbf_ebpfle,xaddwle) },
+ { BPFBF_EBPFLE_INSN_BRKPT, SEM_FN_NAME (bpfbf_ebpfle,brkpt) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (bpfbf_ebpfle,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (bpfbf_ebpfle,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (bpfbf_ebpfle,x_invalid);
+#endif
+ }
+}
+
--
2.25.0.2.g232378479e
^ permalink raw reply [flat|nested] 10+ messages in thread