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[143.159.223.185]) by smtp.gmail.com with ESMTPSA id q25-20020a056000137900b003455d32e944sm3871520wrz.96.2024.04.12.03.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 03:14:25 -0700 (PDT) From: Andrew Burgess To: Bernd Edlinger , "gdb-patches@sourceware.org" Subject: Re: [PATCH v2] sim: riscv: Fix some compatibility issues with gcc In-Reply-To: References: Date: Fri, 12 Apr 2024 11:14:24 +0100 Message-ID: <87edba6g73.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Bernd Edlinger writes: > This makes the riscv simulator able to execute a simple > "hello world" program when gcc is configured > with: > > .../gcc-trunk/configure --target=riscv-unknown-elf > > The first problem is that gcc generates rv32 > code by default in this configuration, while > riscv64-unknown-elf generates rv64 code by default. > > So change the riscv/acinclude.m4 to use the same > logic here. > > And the second issue is that gcc does by default > generate instructions in INSN_CLASS_C, so move > the M(GC) to top of list, in riscv/model_list.def. > > Then there was apparently a confusion which cpu > model uses JAL and which ADDIW. Fixed that in > execute_c, case MATCH_C_JAL | MATCH_C_ADDIW. > > With these changes a simple c-prgram can be executed, > however there is still work to do, since when the > program does floating point operations, gcc starts to > generate hardware floating point instructions, with no > obvious opt-out option. > > Note the gcc test suite can be used to test the > simulator in this way: > > make check-gcc RUNTESTFLAGS="--target_board=multi-sim SIM=riscv-unknown-elf-run" > > Now many tests are passed, except those which use > floating point instructions. > > To work around the not supported float instructions the > following gcc configuration can be used, which makes > most of the gcc test cases successfully executed: > > .../gcc-trunk/configure --prefix=... --target=riscv-unknown-elf > --disable-multilib --with-arch=rv32imac --with-abi=ilp32 > > Note: binutils are installed at prefix path and newlib/libgloss in-tree. > > Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer instructions") > --- > sim/configure | 6 +++--- > sim/riscv/acinclude.m4 | 4 ++-- > sim/riscv/model_list.def | 2 +- > sim/riscv/sim-main.c | 4 ++-- > 4 files changed, 8 insertions(+), 8 deletions(-) > > v2: updated the commit message, with some hints > how to compile a compatible gcc toolchain. > > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index adff99921c6..9c0d070aa60 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -1018,7 +1018,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > case MATCH_C_JAL | MATCH_C_ADDIW: > /* JAL and ADDIW have the same mask but are only available on RV64 or > RV32 respectively. */ This comment needs fixing too please. Thanks, Andrew > - if (RISCV_XLEN (cpu) == 64) > + if (RISCV_XLEN (cpu) == 32) > { > imm = EXTRACT_CJTYPE_IMM (iw); > TRACE_INSN (cpu, "c.jal %" PRIxTW, > @@ -1027,7 +1027,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > pc = riscv_cpu->pc + imm; > TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); > } > - else if (RISCV_XLEN (cpu) == 32) > + else if (RISCV_XLEN (cpu) == 64) > { > imm = EXTRACT_CITYPE_IMM (iw); > TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW, > -- > 2.39.2