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Wed, 18 Oct 2023 09:58:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFi9DPT2k/LkTDnVPHuoBQHTDJMsckxrb3YxJsTVK3vz19szr0DUDYrjgiYDzs7G3nrCtSABA== X-Received: by 2002:ac8:5a83:0:b0:419:7e82:91bb with SMTP id c3-20020ac85a83000000b004197e8291bbmr6610892qtc.61.1697648327421; Wed, 18 Oct 2023 09:58:47 -0700 (PDT) Received: from localhost ([31.111.84.209]) by smtp.gmail.com with ESMTPSA id l4-20020ac84584000000b0041b9b6eb309sm82180qtn.93.2023.10.18.09.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 09:58:46 -0700 (PDT) From: Andrew Burgess To: Jaydeep Patil , "gdb-patches@sourceware.org" Cc: "vapier@gentoo.org" , Joseph Faulls , Bhushan Attarde Subject: Re: [PATCH 2/4] [sim/riscv] Fix JALR instruction simulation In-Reply-To: References: Date: Wed, 18 Oct 2023 17:58:44 +0100 Message-ID: <87h6mn50l7.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Jaydeep Patil writes: > Fixed 32bit JALR ra,ra,imm integer instruction, where RD was written before > using it to calculate target PC. > --- > sim/riscv/sim-main.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index 2b184aea554..3cf6e3fc4b0 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -598,8 +598,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > break; > case MATCH_JALR: > TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm); > - store_rd (cpu, rd, riscv_cpu->pc + 4); > pc = riscv_cpu->regs[rs1] + i_imm; > + store_rd (cpu, rd, riscv_cpu->pc + 4); > TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); > break; > Thanks for fixing this. I added a test for this change -- ideally change will come with an associated test -- and pushed this patch. What I pushed is below. Thanks, Andrew --- commit 1c37b30945073f34bbb685d2ac47ab01e0c93d45 Author: Jaydeep Patil Date: Wed Oct 18 17:37:59 2023 +0100 sim/riscv: fix JALR instruction simulation Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 250791634a1..afdfcf50656 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -449,8 +449,8 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) break; case MATCH_JALR: TRACE_INSN (cpu, "jalr %s, %s, %" PRIiTW ";", rd_name, rs1_name, i_imm); - store_rd (cpu, rd, riscv_cpu->pc + 4); pc = riscv_cpu->regs[rs1] + i_imm; + store_rd (cpu, rd, riscv_cpu->pc + 4); TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); break; diff --git a/sim/testsuite/riscv/jalr.s b/sim/testsuite/riscv/jalr.s new file mode 100644 index 00000000000..daccf4fb5a0 --- /dev/null +++ b/sim/testsuite/riscv/jalr.s @@ -0,0 +1,22 @@ +# Basic jalr tests. +# mach: riscv + +.include "testutils.inc" + + start + + # Load desination into register a0. + la a0, good_dest + + # Jump to the destination in a0. + jalr a0, a0, 0 + + # If we write destination into a0 before reading it in order + # to jump, we might end up here. +bad_dest: + fail + + # We should end up here. +good_dest: + pass + fail diff --git a/sim/testsuite/riscv/testutils.inc b/sim/testsuite/riscv/testutils.inc index b9680b9c22e..c5e09eb5ea3 100644 --- a/sim/testsuite/riscv/testutils.inc +++ b/sim/testsuite/riscv/testutils.inc @@ -21,8 +21,9 @@ # Trigger OS trap. ecall; exit 0; - .data + .pushsection .data 1: .asciz "pass\n" + .popsection .endm # MACRO: fail @@ -33,14 +34,15 @@ # Use stdout. li a0, 1; # Point to the string. - lla a1, 1f; + la a1, 1f; # Number of bytes to write. li a2, 5; # Trigger OS trap. ecall; exit 0; - .data + .pushsection .data 1: .asciz "fail\n" + .popsection .endm # MACRO: start @@ -49,4 +51,8 @@ .text .global _start _start: + .option push + .option norelax + lla gp, __global_pointer$ + .option pop .endm