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Tue, 11 Jun 2024 08:38:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH5HSYLYMlABa8CtCDU9eJXgEiJnZFzzW9uu0MvQtety0wTfn0ZW3LR18ZJPFRfvlY3z5b49A== X-Received: by 2002:ac2:5bc9:0:b0:52b:b8c9:9cd7 with SMTP id 2adb3069b0e04-52bb9f6e5cbmr7000930e87.18.1718120334228; Tue, 11 Jun 2024 08:38:54 -0700 (PDT) Received: from localhost ([31.111.84.186]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35f1f109346sm7403567f8f.27.2024.06.11.08.38.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 08:38:53 -0700 (PDT) From: Andrew Burgess To: Bernd Edlinger , "gdb-patches@sourceware.org" Subject: Re: [PATCH 1/2] sim: riscv: fix a divw division by -1 bug In-Reply-To: References: Date: Tue, 11 Jun 2024 16:38:52 +0100 Message-ID: <87ikyfa3qr.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Bernd Edlinger writes: > There is a bug in divw for riscv64 target > with dividing by -1, the result was always 0, > when it should in fact be sign-extended -dividend. > It did not affect the rv32 target, because > these instructions are rv64 only. > Since 1 << 31 is an integer overflow this avoids > an undefined behaviour bug at the same time. > > This caused test failures in the gcc testsuite like: > > FAIL: gcc.c-torture/execute/arith-rand-ll.c -O0 execution test > FAIL: gcc.c-torture/execute/arith-rand-ll.c -O1 execution test > FAIL: gcc.c-torture/execute/arith-rand-ll.c -O2 execution test > FAIL: gcc.c-torture/execute/arith-rand-ll.c -O3 execution test > FAIL: gcc.c-torture/execute/arith-rand.c -O0 execution test > FAIL: gcc.c-torture/execute/arith-rand.c -O1 execution test > FAIL: gcc.c-torture/execute/arith-rand.c -O2 execution test > FAIL: gcc.c-torture/execute/arith-rand.c -O3 execution test > ... > --- > sim/riscv/sim-main.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index c8adb65139b..515ff835223 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -724,7 +724,7 @@ execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > rd_name, rs1_name, rs2_name, rd_name, rs1_name, rs2_name); > RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name); > if (EXTEND32 (riscv_cpu->regs[rs2]) == -1) > - tmp = 1 << 31; > + tmp = EXTEND32 (-(uint32_t) riscv_cpu->regs[rs1]); I think this part of the if tree is no longer needed, the following... > else if (EXTEND32 (riscv_cpu->regs[rs2])) > tmp = EXTEND32 (riscv_cpu->regs[rs1]) / EXTEND32 (riscv_cpu->regs[rs2]); ... should give the correct answer, right? Additionally, we should be adding tests for these bugs as we fix them. Below is what I wrote in order to check this patch, feel free to include this with a v2 of this patch, or do your own thing if you prefer. Thanks, Andrew --- diff --git a/sim/testsuite/riscv/divw.s b/sim/testsuite/riscv/divw.s new file mode 100644 index 00000000000..ed130358607 --- /dev/null +++ b/sim/testsuite/riscv/divw.s @@ -0,0 +1,31 @@ +# Basic divw tests. +# mach: riscv64 +# sim(riscv64): --model RV64GC +# ld(riscv64): -m elf64lriscv +# as(riscv64): -march=rv64gc + +.include "testutils.inc" + + .macro test_divw dividend, divisor, answer + # Setup inputs. + li a1, \dividend + li a2, \divisor + + # Do the divide. + divw a3, a1, a2 + + # Check answer is correct. + li a4, \answer + bne a3, a4, test_failed + .endm + + + start + + test_divw 1, -1, -1 + test_divw 6, 2, 3 + + pass + +test_failed: + fail