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[143.159.223.185]) by smtp.gmail.com with ESMTPSA id l12-20020a5d668c000000b003375c072fbcsm4509979wru.100.2024.01.10.02.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 02:22:13 -0800 (PST) From: Andrew Burgess To: jaydeep.patil@imgtec.com, gdb-patches@sourceware.org Cc: vapier@gentoo.org, joseph.faulls@imgtec.com, bhushan.attarde@imgtec.com, jaydeep.patil@imgtec.com Subject: Re: [PATCH v5 1/2] [sim/riscv] Fix crash during instruction decoding In-Reply-To: <20231222052658.2102802-2-jaydeep.patil@imgtec.com> References: <20231222052658.2102802-1-jaydeep.patil@imgtec.com> <20231222052658.2102802-2-jaydeep.patil@imgtec.com> Date: Wed, 10 Jan 2024 10:22:12 +0000 Message-ID: <87mstd8p4b.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: writes: > From: Jaydeep Patil > > The match_never() function has been removed and thus step_once() crashes > during instruction decoding. Fixed it by checking for null pointer before > invoking function attached to match_func member of riscv_opcode structure. > --- > opcodes/riscv-dis.c | 2 +- > sim/riscv/sim-main.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c > index 68674380797..a89ebdd32ac 100644 > --- a/opcodes/riscv-dis.c > +++ b/opcodes/riscv-dis.c > @@ -818,7 +818,7 @@ riscv_disassemble_insn (bfd_vma memaddr, > if (op->pinfo == INSN_MACRO) > continue; > /* Does the opcode match? */ > - if (! (op->match_func) (op, word)) > + if (! op->match_func || ! (op->match_func) (op, word)) > continue; > /* Is this a pseudo-instruction and may we print it as such? */ > if (no_aliases && (op->pinfo & INSN_ALIAS)) Sorry to be a pain, but changes in opcodes/ need to go through the binutils@sourceware.org mailing list. I took a little dive into the history of the match_never() removal, and found these two commits: commit 2ec31e54dff83130fbde8d2f674469078ee203d5 Date: Fri Nov 24 10:15:59 2023 +0100 RISC-V: drop leftover match_never() references And maybe more interesting: commit 27b33966b18ed8bf1701a60999448224b1d28273 Date: Fri Nov 24 09:53:15 2023 +0100 RISC-V: disallow x0 with certain macro-insns This second commit talks about treating a NULL as actually meaning match_always. I've not dug into this beyond looking at those commits, but that second commit does include some code similar to yours, except in that case they've gone with something like: if (op->match_func && !(op->match_func) (op, word)) continue; I'd like to see a commit message that references this history, and explains why this commit does something different. Also, does your change indicate that there exists an instruction encoding which, if we try to disassemble it, will cause the disassembler to segfault? That would be a good candidate for making into a test, maybe in the gas testsuite? Thanks, Andrew > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index 4d205345395..65c0ea245b2 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -1042,7 +1042,7 @@ void step_once (SIM_CPU *cpu) > for (; op->name; op++) > { > /* Does the opcode match? */ > - if (! op->match_func (op, iw)) > + if (! op->match_func || ! op->match_func (op, iw)) > continue; > /* Is this a pseudo-instruction and may we print it as such? */ > if (op->pinfo & INSN_ALIAS) > -- > 2.25.1