[PATCH 0/4] sim: riscv: Compressed instruction simulation and semi-hosting support

[PATCH 0/4] sim: riscv: Compressed instruction simulation and semi-hosting support

[Jaydeep Patil]

[-- Attachment #1: Type: text/plain, Size: 1891 bytes --]

Hi,

This is a collection of patches that add simulation of compressed integer
instruction set ("c") and semi-hosting support to the RISC-V simulator. It also
fixes 32bit JALR instruction simulation when RD is same as RS1. Two tests are
added in gdb.arch to test basic semi-hosting and then the simulation of
compressed integer instructions.

Patch #1 adds basic semi-hosting support (OPEN, EXIT and GET_CMDLINE) and
         gdb.arch/riscv-exit-getcmd.c test
Patch #2 fixes JALR instruction simulation when RD is same as RS1
Patch #3 adds support for compressed integer instruction set ("c") and
         gdb.arch/riscv-insn-simulation.c test
Patch #4 adds support for remaining semi-hosting calls

Contributions from:
  Joseph Faulls (Joseph.Faulls@imgtec.com<mailto:Joseph.Faulls@imgtec.com>)
  Jaydeep Patil (Jaydeep.Patil@imgtec.com<mailto:Jaydeep.Patil@imgtec.com>)
  Bhushan Attarde (Bhushan.Attarde@imgtec.com<mailto:Bhushan.Attarde@imgtec.com>)

Jaydeep Patil (4):
  [sim/riscv] Add basic semi-hosting support
  [sim/riscv] Fix JALR instruction simulation
  [sim/riscv] Add support for compressed integer instruction set
  [sim/riscv] Add semi-hosting support

gdb/testsuite/gdb.arch/riscv-exit-getcmd.c    |    6 +
gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp  |   31 +
.../gdb.arch/riscv-insn-simulation.c          | 1590 +++++++++++++++++
.../gdb.arch/riscv-insn-simulation.exp        |   35 +
sim/riscv/riscv-sim.h                         |   54 +
sim/riscv/sim-main.c                          |  952 +++++++++-
6 files changed, 2652 insertions(+), 16 deletions(-)
create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c
create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp
create mode 100644 gdb/testsuite/gdb.arch/riscv-insn-simulation.c
create mode 100644 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp

--
2.25.1

Re: [PATCH 0/4] sim: riscv: Compressed instruction simulation and semi-hosting support

[Andrew Burgess]

Jaydeep Patil <Jaydeep.Patil@imgtec.com> writes:

> Hi,
>
> This is a collection of patches that add simulation of compressed integer
> instruction set ("c") and semi-hosting support to the RISC-V simulator. It also
> fixes 32bit JALR instruction simulation when RD is same as RS1. Two tests are
> added in gdb.arch to test basic semi-hosting and then the simulation of
> compressed integer instructions.

Thanks for working on this.  Better risc-v sim support has been
something I've wanted for a while.

I noticed that your email client has mangled the patches during sending,
making applying them harder than necessary.  I recently found this site:

  https://git-send-email.io/

which has some pretty extensive guides for setting up git to send email
directly, which is by far the best way to send patches.

Additionally, in order to test patches like this it would be great if
you could include details of the compiler build you're using (e.g. what
--target=... flag I should build gcc with to ensure I'm testing the same
thing you are), and additionally, to run these tests you must have a
riscv-sim dejagnu board file, it would be great if you could share that
too.  Then I (or others) can easily reproduce your environment and test
these patches.

Thanks,
Andrew


>
> Patch #1 adds basic semi-hosting support (OPEN, EXIT and GET_CMDLINE) and
>          gdb.arch/riscv-exit-getcmd.c test
> Patch #2 fixes JALR instruction simulation when RD is same as RS1
> Patch #3 adds support for compressed integer instruction set ("c") and
>          gdb.arch/riscv-insn-simulation.c test
> Patch #4 adds support for remaining semi-hosting calls
>
> Contributions from:
>   Joseph Faulls (Joseph.Faulls@imgtec.com<mailto:Joseph.Faulls@imgtec.com>)
>   Jaydeep Patil (Jaydeep.Patil@imgtec.com<mailto:Jaydeep.Patil@imgtec.com>)
>   Bhushan Attarde (Bhushan.Attarde@imgtec.com<mailto:Bhushan.Attarde@imgtec.com>)
>
> Jaydeep Patil (4):
>   [sim/riscv] Add basic semi-hosting support
>   [sim/riscv] Fix JALR instruction simulation
>   [sim/riscv] Add support for compressed integer instruction set
>   [sim/riscv] Add semi-hosting support
>
> gdb/testsuite/gdb.arch/riscv-exit-getcmd.c    |    6 +
> gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp  |   31 +
> .../gdb.arch/riscv-insn-simulation.c          | 1590 +++++++++++++++++
> .../gdb.arch/riscv-insn-simulation.exp        |   35 +
> sim/riscv/riscv-sim.h                         |   54 +
> sim/riscv/sim-main.c                          |  952 +++++++++-
> 6 files changed, 2652 insertions(+), 16 deletions(-)
> create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.c
> create mode 100644 gdb/testsuite/gdb.arch/riscv-exit-getcmd.exp
> create mode 100644 gdb/testsuite/gdb.arch/riscv-insn-simulation.c
> create mode 100644 gdb/testsuite/gdb.arch/riscv-insn-simulation.exp
>
> --
> 2.25.1

RE: [EXTERNAL] Re: [PATCH 0/4] sim: riscv: Compressed instruction simulation and semi-hosting support

[Jaydeep Patil]

Andrew Burgess <aburgess@redhat.com> writes:

> Thanks for working on this.  Better risc-v sim support has been
> something I've wanted for a while.
> 
> I noticed that your email client has mangled the patches during sending,
> making applying them harder than necessary.  I recently found this site:
> 
>   https://urldefense.com/v3/__https://git-send-email.io/__;!!KCwjcDI!3xH-JYp0hLFW2vfmp5cY5pABSk8Os_bk18e-uc1eHL3KF5KoIrwMzN6qvxyoeT9-EfHWRLF2b7tsEo6iwgXNwQ$ 
> 
> which has some pretty extensive guides for setting up git to send email
> directly, which is by far the best way to send patches.
> 
> Additionally, in order to test patches like this it would be great if
> you could include details of the compiler build you're using (e.g. what
> --target=... flag I should build gcc with to ensure I'm testing the same
> thing you are), and additionally, to run these tests you must have a
> riscv-sim dejagnu board file, it would be great if you could share that
> too.  Then I (or others) can easily reproduce your environment and test
> these patches.
> 
> Thanks,
> Andrew

Hi Andrew,

Thanks for looking into it.

The GDB has been configured with --target=riscv64-img-elf option.
The test suite is run with following options:

RUNTESTFLAGS="--target_board='riscv-sim-picolibc/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow'"
Baseboard is riscv-sim-picolibc.exp which is based on riscv-sim.exp.
Please refer to the attached file.

I will address all your review comments and submit version 2 of the patches.

Thank you,
Jaydeep

-----
# Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2012, 2016
# Free Software Foundation, Inc.
#
# This file is part of DejaGnu. For RISC-V target simulation.
#
# DejaGnu is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# DejaGnu is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with DejaGnu; if not, write to the Free Software Foundation,
# Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.

# Load the generic configuration for this board. This will define a basic
# set of routines used to communicate with the board.
load_generic_config "sim"

# basic-sim.exp is a basic description for the standard Cygnus simulator.
load_base_board_description "basic-sim"

# No multilib flags are set by default.
process_multilib_options ""

# The compiler used to build for this board. This has *nothing* to do
# with what compiler is tested if we're testing gcc.
set_board_info compiler "[find_gcc]"

# The basic set of flags needed to build "hello world" for this
# board. This board uses libgloss and newlib.
set_board_info cflags 	"[libgloss_include_flags] [newlib_include_flags]"

# Set ldflags with:
# 1. --oslib=semihost to include semihosting lib
# 2. -lc -lsemihost -lgcc to link, so the libraries will be grouped by
#    --start-group and --end-group in the linking command line.
# 3. Define __ram_size=0x2000000 to set SP to higher place to avoid some gcc
#    test cases allocate big trunk of local memory and let the SP underflow.
# 4. Define __heap_end=0x1000000 to avoid heap overflow in some gcc test
#    cases.
set_board_info ldflags "--oslib=semihost -e 0 -lc -lgcc -Xlinker --defsym=__ram_size=0x2000000 -Xlinker --defsym=__heap_end=0x1000000"

# This board doesn't use a linker script.
set_board_info ldscript ""

# And, it can't do arguments, and doesn't have real signals.

set_board_info noargs 1
set_board_info gdb,nosignals 1

# skip gdb.reverse
set_board_info gdb,can_reverse 0
set_board_info gdb,use_precord 0

# Setup the timeout
set_board_info gcc,timeout 600