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[87.115.72.52]) by smtp.gmail.com with ESMTPSA id m1-20020a1c2601000000b003c452678025sm10038710wmm.4.2022.10.11.04.43.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 04:43:30 -0700 (PDT) From: Andrew Burgess To: Palmer Dabbelt , research_trasio@irq.a4lg.com, vapier@gentoo.org Cc: gdb-patches@sourceware.org Subject: Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions In-Reply-To: References: Date: Tue, 11 Oct 2022 12:43:29 +0100 Message-ID: <87pmeyd1r2.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, BODY_8BITS, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Oct 2022 11:43:35 -0000 Palmer Dabbelt writes: > On Thu, 06 Oct 2022 09:14:37 PDT (-0700), research_trasio@irq.a4lg.com wr= ote: >> On 2022/10/07 0:58, Palmer Dabbelt wrote: >>> On Thu, 06 Oct 2022 03:33:00 PDT (-0700), research_trasio@irq.a4lg.com >>> wrote: >>>> Because of recent 'Zmmul' support, the simulator is now broken.=C2=A0 = This is >>>> caused by instruction classification changes: >>>> >>>> [Before] >>>> -=C2=A0=C2=A0 INSN_CLASS_M=C2=A0=C2=A0=C2=A0=C2=A0 : multiply / divide >>>> [After Zmmul] >>>> -=C2=A0=C2=A0 INSN_CLASS_M=C2=A0=C2=A0=C2=A0=C2=A0 : divide >>>> -=C2=A0=C2=A0 INSN_CLASS_ZMMUL : multiply >>>> >>>> The simulator checks the instruction class to execute an instruction: >>>> >>>> -=C2=A0=C2=A0 INSN_CLASS_I=C2=A0 : 'I' >>>> -=C2=A0=C2=A0 INSN_CLASS_M=C2=A0 : 'M' (multiply / divide) >>>> -=C2=A0=C2=A0 INSN_CLASS_A=C2=A0 : 'A' >>>> >>>> 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that >>>> instruction >>>> class is not handled by the simulator. >>>> >>>> This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds= a >>>> testcase to test all RV32M instructions run without any faults. >>>> --- >>>> =C2=A0sim/riscv/sim-main.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |= =C2=A0 1 + >>>> =C2=A0sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ >>>> =C2=A02 files changed, 19 insertions(+) >>>> =C2=A0create mode 100644 sim/testsuite/riscv/m-ext.s >>>> >>>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c >>>> index 30d2f1e1c9a..0156f791d4b 100644 >>>> --- a/sim/riscv/sim-main.c >>>> +++ b/sim/riscv/sim-main.c >>>> @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const >>>> struct riscv_opcode *op) >>>> =C2=A0=C2=A0=C2=A0=C2=A0 case INSN_CLASS_I: >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return execute_i (cpu, iw, op); >>>> =C2=A0=C2=A0=C2=A0=C2=A0 case INSN_CLASS_M: >>>> +=C2=A0=C2=A0=C2=A0 case INSN_CLASS_ZMMUL: >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return execute_m (cpu, iw, op); >>>> =C2=A0=C2=A0=C2=A0=C2=A0 default: >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 TRACE_INSN (cpu, "UNHANDLED EXTEN= SION: %d", op->insn_class); >>>> diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s >>>> new file mode 100644 >>>> index 00000000000..b85397a32a0 >>>> --- /dev/null >>>> +++ b/sim/testsuite/riscv/m-ext.s >>>> @@ -0,0 +1,18 @@ >>>> +# check that the RV32M instructions run without any fault. >>>> +# mach: riscv >>>> + >>>> +.include "testutils.inc" >>>> + >>>> +=C2=A0=C2=A0=C2=A0 start >>>> + >>>> +=C2=A0=C2=A0=C2=A0 .option=C2=A0=C2=A0=C2=A0 arch, +m >>>> +=C2=A0=C2=A0=C2=A0 mul=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 mulh=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 mulhu=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 mulhsu=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 div=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 divu=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 rem=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> +=C2=A0=C2=A0=C2=A0 remu=C2=A0=C2=A0=C2=A0 x0, x1, x2 >>>> + >>>> +=C2=A0=C2=A0=C2=A0 pass >>> >>> Reviewed-by: Palmer Dabbelt >>> Acked-by: Palmer Dabbelt >>> >>> though as we're talking about in this meeting, I'm not actually a gdbsi= m >>> maintainer so I'm not sure I can formally approve it. >>> >> >> Palmer, >> >> I saw following files and thought you are one of the person who can >> formally approve my patch. >> >> Quoting sim/MAINTAINERS: >>> SIM Maintainers >>> >>> The simulator is part of the GDB project, so see the file >>> gdb/MAINTAINERS for general information about maintaining these files..= .. >>> common Frank Ch. Eigler >>> * (target, then global maintainers) >> >> I know that Andrew and Palmer are RISC-V target maintainers of GDB so I >> assumed you are responsible for this area. But it seems... no one knows >> exactly. It seems very few people is interested in the simulator so... >> well... for now, I will continue pinging until someone who thinks >> responsible notices. > > Ah, I guess I wasn't looking close enough. I also didn't write the sim= =20 > port, Mike Frysinger did and he's a sim gloabal maintainer so I'd=20 > generally just deferred to him on these things. > > +Mike and Andrew: I'm OK reviewing sim patches, at least for the stuff=20 > that's pretty much just ISA encoding. The port certainly needs some=20 > love and I don't really have the time to write the code, but I'm OK=20 > finding some time to review stuff if that's what's necessary for patches= =20 > to land (though I'd be very happy to have someone else do the work, as=20 > usual ;)). Hi Palmer, Apologies for letting some of the sim/ reviews lag. I've been pretty rushed for the last few weeks, but I'm trying to get on top of any outstanding sim/ patches, and hopefully will try to keep on top of the reviews going forward. Thanks, Andrew