From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oa1-x2d.google.com (mail-oa1-x2d.google.com [IPv6:2001:4860:4864:20::2d]) by sourceware.org (Postfix) with ESMTPS id 790063858005 for ; Tue, 27 Sep 2022 20:08:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 790063858005 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-12803ac8113so14739406fac.8 for ; Tue, 27 Sep 2022 13:08:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:in-reply-to :subject:cc:to:from:user-agent:references:x-gm-message-state:from:to :cc:subject:date; bh=aK6Ycr7sudLfzGSLVL0NVmd4GcA/JvyK6oVudqDq6sA=; b=PMbZzbrxgp0sRdqv8MtjwROz7IJMnNku0LQuzUB9qgSnGu2J5X7hRwLltVb0g+VQZ5 BzMS0731Ii7zwmPyHKbOlcYeJT/2hoCaV6veigXPrl1bcDCgGv7T1DLs8ux6rM0e05Fw fuu/IoZ1Dk/3Eibqj1dt/5dvHFqISK6gMpI0Tm5arjFQjPoTLDII3tBuZnUrG+cltpcJ KtC7BSWCfA6mhs1P77s4fVTsu+mF6IMFs8XT7l+scBSOKPLv7oBkoPiXBij0K8p59ZQs nqnKTLTIJ6maJUPiMYkOalZMlD+t+nEkEuWSlmQLklxiy1+25gKE4GXxNY5f10kpn+id VeDA== X-Gm-Message-State: ACrzQf0moQbqnr/YElkMsj6UZMstJ0jXQ3ieoxyfIEOo2AUbMHTteCTi PS7Vjxtcv+Qg5FvAHupTOlG/c2r0FfSvKg== X-Google-Smtp-Source: AMsMyM7okXYZEsCQ/JSf6DaeBc2wCiEVRQz7AZYXTHDIjQUHvsa2NpUlskftBv/Ew4OYxZqTP+y7HQ== X-Received: by 2002:a05:6870:5808:b0:128:afd5:491f with SMTP id r8-20020a056870580800b00128afd5491fmr3365580oap.136.1664309325909; Tue, 27 Sep 2022 13:08:45 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8470:b00c:7850:ebea:3ab6]) by smtp.gmail.com with ESMTPSA id y4-20020a056808130400b003512f3195d7sm1028221oiv.30.2022.09.27.13.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 13:08:45 -0700 (PDT) References: <20220927190944.201748-1-torbjorn.svensson@foss.st.com> User-agent: mu4e 1.8.9; emacs 28.1 From: Thiago Jung Bauermann To: =?utf-8?Q?Torbj=C3=B6rn?= SVENSSON Cc: tom@tromey.com, brobecker@adacore.com, gdb-patches@sourceware.org Subject: Re: [PATCH v3] gdb/arm: Handle lazy FPU register stacking In-reply-to: <20220927190944.201748-1-torbjorn.svensson@foss.st.com> Date: Tue, 27 Sep 2022 20:08:42 +0000 Message-ID: <87pmfgeg1h.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Sep 2022 20:08:49 -0000 Hello, Torbj=C3=B6rn SVENSSON via Gdb-patches writes: > diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c > index 2810232fcb8..43ce1a45782 100644 > --- a/gdb/arm-tdep.c > +++ b/gdb/arm-tdep.c > @@ -68,6 +68,7 @@ > #endif >=20=20 > static bool arm_debug; > +static bool force_fpu_regs_from_stack =3D false; I'm a bit concerned about having a global variable to indicate what is (IIUC) a per-CPU state. Does this logic work with multi-processor inferiors? Instead of using a global variable, can arm_m_exception_cache use =E2=80=9Cthis_frame->level > 0=E2=80=9D to decide whether to get the FPU re= gisters from the stack? --=20 Thiago