From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi1-x236.google.com (mail-oi1-x236.google.com [IPv6:2607:f8b0:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 1C1723858D32 for ; Fri, 25 Aug 2023 23:33:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1C1723858D32 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-oi1-x236.google.com with SMTP id 5614622812f47-3a36b52b4a4so806757b6e.1 for ; Fri, 25 Aug 2023 16:33:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693006437; x=1693611237; h=mime-version:message-id:date:in-reply-to:subject:cc:to:from :user-agent:references:from:to:cc:subject:date:message-id:reply-to; bh=s7lU/OC1y6oWi3KWdIRuu/l8CAMOfiRRzUJdain2VkI=; b=le+8HxTLJIBBHl62+dn5vpASuOcQQIbuidCllBShWIMFFFalOho3jhzcAojnxfb4Gn 2V/7bDYpjymTngk8nRXwxlGUVcu/Vo8yILrofdCYE7WOdR9FVTm/2GloO38KeOxHZwUX tnHbvc41yHMiFeCC6KdwE0F2rrfSZo0IvcbOQkggAM8iAz4RreDK5PH7n0jf80v4cZfD RAs6xWCUElsiqw/YurRVz8YeSdnrcRnY69Dh4Na9XDrV0/O/RtQf++iyBKzJs71+ZzXB usr6OMJ4LlO2a+bmekBqM6HUlSU/OaYbu0YdDpahO+ikpc8s3tUr7FeMJnHvhlq3vVuc L1tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693006437; x=1693611237; h=mime-version:message-id:date:in-reply-to:subject:cc:to:from :user-agent:references:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=s7lU/OC1y6oWi3KWdIRuu/l8CAMOfiRRzUJdain2VkI=; b=DM6zcNFHXMY40MQ0hibLELbVkMDdgSy6ivTHRmzkSk93BbUYNiW7VnuRyMkx0kj6H6 DZQjVVVgzI9KAOSMpv5gD9BPJejqlF3lGMoY7bNXr1gMwQN+F3ECYWktlvfmfIi9cruc 5Qu+PZxgcq187LEmR1mo+RVamDj2KoMgDJYHA2frvkOyG2LHRF6rqvOU+KkMN9yN7STm Ul4SL+ksBAelT0/kRsFlX2dfjAqa07ucaH5KFzDzoLPc2iRhMXgbc7+rB4DXnTTwtFtK DdlQ78lWj6GUIKe1F7HFZquoYIPNjltLnltA0uXn5H4ecucUk3EhlX1TWxRPY0rLKoGd LSdQ== X-Gm-Message-State: AOJu0YxN7viaAeghicI3dugZyv56Tx/et7NaQOqgUzrlRvJlX1KXV7MX Qerv7E8GxYl9Bruacf5DUkN+Og== X-Google-Smtp-Source: AGHT+IEerj1fpw/6jjBG9cHKg9ww6y5zVKVWfLdz/KOSsyS4Nq1TxXDbBTbtL6VrDPnjdCfCHDSxRQ== X-Received: by 2002:a05:6808:1828:b0:3a7:272d:2f1c with SMTP id bh40-20020a056808182800b003a7272d2f1cmr2481157oib.25.1693006437331; Fri, 25 Aug 2023 16:33:57 -0700 (PDT) Received: from localhost ([2804:14d:7e39:8470:734d:f1d5:96bb:b4ea]) by smtp.gmail.com with ESMTPSA id a20-20020a056808129400b003a8715d7f9esm1259371oiw.19.2023.08.25.16.33.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Aug 2023 16:33:56 -0700 (PDT) References: <20230822112130.1513216-1-luis.machado@arm.com> <20230822112130.1513216-15-luis.machado@arm.com> User-agent: mu4e 1.10.5; emacs 28.2 From: Thiago Jung Bauermann To: Luis Machado Cc: gdb-patches@sourceware.org Subject: Re: [PATCH v4 14/16] [gdb/aarch64] sme: Core file support for Linux In-reply-to: <20230822112130.1513216-15-luis.machado@arm.com> Date: Fri, 25 Aug 2023 20:33:53 -0300 Message-ID: <87r0nqn1cu.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hello Luis, Just one minor comment: Luis Machado writes: > +/* Collect an inactive SVE register set state. This is equivalent to a > + fpsimd layout. > + > + Collect the data from REGCACHE to BUF, using the register > + map in REGSET. */ > + > +static void > +collect_inactive_sve_regset (const struct regcache *regcache, > + void *buf, size_t size, int vg_regnum) > +{ > + gdb_byte *header = (gdb_byte *) buf; > + struct gdbarch *gdbarch = regcache->arch (); > + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); > + > + gdb_assert (buf != nullptr); > + gdb_assert (size >= SVE_CORE_DUMMY_SIZE); > + > + /* Zero out everything first. */ > + memset ((gdb_byte *) buf, 0, SVE_CORE_DUMMY_SIZE); > + > + /* BUF starts with a SVE header prior to the register dump. */ > + > + /* Dump the default size of an empty SVE payload. */ > + uint32_t real_size = SVE_CORE_DUMMY_SIZE; > + store_unsigned_integer (header + SVE_HEADER_SIZE_OFFSET, > + SVE_HEADER_SIZE_LENGTH, byte_order, real_size); > + > + /* Dump a dummy max size. */ > + uint32_t max_size = SVE_CORE_DUMMY_MAX_SIZE; > + store_unsigned_integer (header + SVE_HEADER_MAX_SIZE_OFFSET, > + SVE_HEADER_MAX_SIZE_LENGTH, byte_order, max_size); > + > + /* Dump the vector length. */ > + ULONGEST vg = 0; > + regcache->raw_collect (vg_regnum, &vg); > + uint16_t vl = sve_vl_from_vg (vg); > + store_unsigned_integer (header + SVE_HEADER_VL_OFFSET, SVE_HEADER_VL_LENGTH, > + byte_order, vl); > + > + /* Dump the standard maximum vector length. */ > + uint16_t max_vl = SVE_CORE_DUMMY_MAX_VL; > + store_unsigned_integer (header + SVE_HEADER_MAX_VL_OFFSET, > + SVE_HEADER_MAX_VL_LENGTH, byte_order, > + max_vl); > + > + /* The rest of the fields are zero. */ > + uint16_t flags = SVE_CORE_DUMMY_FLAGS; > + store_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET, > + SVE_HEADER_FLAGS_LENGTH, byte_order, > + flags); > + uint16_t reserved = SVE_CORE_DUMMY_RESERVED; > + store_unsigned_integer (header + SVE_HEADER_RESERVED_OFFSET, > + SVE_HEADER_RESERVED_LENGTH, byte_order, reserved); > + > + /* We are done with the header part of it. Now dump the register state > + in the FPSIMD format. */ > + > + /* Dump the first 128 bits of each of the Z registers. */ > + header += AARCH64_SVE_CONTEXT_REGS_OFFSET; > + for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++) > + regcache->raw_collect_part (AARCH64_SVE_Z0_REGNUM + i, 0, V_REGISTER_SIZE, > + header + V_REGISTER_SIZE * i); > + > + /* Dump FPSR and FPCR. */ > + header += 32 * V_REGISTER_SIZE; > + regcache->raw_collect (AARCH64_FPSR_REGNUM, header); > + header += 4; > + regcache->raw_collect (AARCH64_FPCR_REGNUM, header); > + > + /* Dump two reserved empty fields of 4 bytes. */ > + header += 8; Sorry, I missed this on my previous review: the header adjustment position above looks a bit strange. Shouldn't the two reserved fields come right after FPCR, instead of having a 4-byte gap? > + memset (header, 0, 8); > + > + /* We should have a FPSIMD-formatted register dump now. */ > +} -- Thiago