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[87.115.72.52]) by smtp.gmail.com with ESMTPSA id i29-20020a1c541d000000b003c41144b3cfsm10326479wmb.20.2022.10.11.04.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 04:41:47 -0700 (PDT) From: Andrew Burgess To: Tsukasa OI via Gdb-patches , Tsukasa OI , Palmer Dabbelt Cc: gdb-patches@sourceware.org Subject: Re: [PING^3 PATCH 1/1] sim/riscv: PR29595, Fix multiply instructions In-Reply-To: References: Date: Tue, 11 Oct 2022 12:41:46 +0100 Message-ID: <87sfjud1tx.fsf@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Oct 2022 11:41:51 -0000 Tsukasa OI via Gdb-patches writes: > Because of recent 'Zmmul' support, the simulator is now broken. This is > caused by instruction classification changes: > > [Before] > - INSN_CLASS_M : multiply / divide > [After Zmmul] > - INSN_CLASS_M : divide > - INSN_CLASS_ZMMUL : multiply > > The simulator checks the instruction class to execute an instruction: > > - INSN_CLASS_I : 'I' > - INSN_CLASS_M : 'M' (multiply / divide) > - INSN_CLASS_A : 'A' > > 'Zmmul' moved multiply instructions to INSN_CLASS_ZMMUL and that instruction > class is not handled by the simulator. > > This commit handles INSN_CLASS_ZMMUL for all 'M' instructions and adds a > testcase to test all RV32M instructions run without any faults. Tsukasa, Thanks for fixing this. I've pushed a version of this patch, the biggest change was that I rewrote the commit message, merging in the useful information from the cover letter. There was also one nit which I fixed, pointed out below... > --- > sim/riscv/sim-main.c | 1 + > sim/testsuite/riscv/m-ext.s | 18 ++++++++++++++++++ > 2 files changed, 19 insertions(+) > create mode 100644 sim/testsuite/riscv/m-ext.s > > diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c > index 30d2f1e1c9a..0156f791d4b 100644 > --- a/sim/riscv/sim-main.c > +++ b/sim/riscv/sim-main.c > @@ -936,6 +936,7 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) > case INSN_CLASS_I: > return execute_i (cpu, iw, op); > case INSN_CLASS_M: > + case INSN_CLASS_ZMMUL: > return execute_m (cpu, iw, op); > default: > TRACE_INSN (cpu, "UNHANDLED EXTENSION: %d", op->insn_class); > diff --git a/sim/testsuite/riscv/m-ext.s b/sim/testsuite/riscv/m-ext.s > new file mode 100644 > index 00000000000..b85397a32a0 > --- /dev/null > +++ b/sim/testsuite/riscv/m-ext.s > @@ -0,0 +1,18 @@ > +# check that the RV32M instructions run without any fault. Missing capital letter here, 'Check that ....'. Thanks, Andrew > +# mach: riscv > + > +.include "testutils.inc" > + > + start > + > + .option arch, +m > + mul x0, x1, x2 > + mulh x0, x1, x2 > + mulhu x0, x1, x2 > + mulhsu x0, x1, x2 > + div x0, x1, x2 > + divu x0, x1, x2 > + rem x0, x1, x2 > + remu x0, x1, x2 > + > + pass > -- > 2.34.1