* [0/1] RISC-V: Update CSR to priv 1.11.
@ 2020-03-12 10:00 Nelson Chu
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
0 siblings, 2 replies; 34+ messages in thread
From: Nelson Chu @ 2020-03-12 10:00 UTC (permalink / raw)
To: gdb-patches, andrew.burgess
Hi gdb,
Since RISCV priv spec 1.11 has been officially released, it would be good if
binutils, gdb, qemu and OpenOCD can support the new CSR. Therfore, I update
the CSR to 1.11 in binutils, and the gdm xml files and gas/testsuite/gas/riscv/csr-dw-regnums
also need to be updated. There are two difference between 1.10 and 1.11,
1. 0x320 is mcountinhibit rather than mucounteren. You can still use the
mucounteren, but objdump will show mcountinhibit for it.
2. 0x7b2 is dscratch0 rather than dscratch, and 0x7b3 is dscratch1. You
can still use the old naming, but objdump will show the new one.
Thanks
Nelson
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH] RISC-V: Update CSR to privileged spec 1.11.
2020-03-12 10:00 [0/1] RISC-V: Update CSR to priv 1.11 Nelson Chu
@ 2020-03-12 10:00 ` Nelson Chu
2020-03-24 5:05 ` [PING] " Nelson Chu
2020-03-24 8:51 ` Andrew Burgess
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
1 sibling, 2 replies; 34+ messages in thread
From: Nelson Chu @ 2020-03-12 10:00 UTC (permalink / raw)
To: gdb-patches, andrew.burgess
gas/
* testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
* testsuite/gas/riscv/alias-csr.s: Likewise.
* testsuite/gas/riscv/no-aliases-csr.d: Move this
to priv-reg-pseudo-noalias.
* testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
* testsuite/gas/riscv/bad-csr.l: Likewise.
* testsuite/gas/riscv/bad-csr.s: Likewise.
* testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
* testsuite/gas/riscv/satp.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
csr instruction, including alias-csr testcase.
* testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
* testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
pseudo instruction with objdump -Mno-aliases.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
* testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
* testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
* testsuite/gas/riscv/priv-reg.s: Likewise.
* testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
* testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
include/
* opcode/riscv-opc.h: Update CSR to 1.11.
gdb/
* features/riscv/32bit-csr.xml: Regenerated.
* features/riscv/64bit-csr.xml: Regenerated.
---
gas/testsuite/gas/riscv/alias-csr.d | 23 -
gas/testsuite/gas/riscv/alias-csr.s | 14 -
gas/testsuite/gas/riscv/bad-csr.d | 3 -
gas/testsuite/gas/riscv/bad-csr.l | 2 -
gas/testsuite/gas/riscv/bad-csr.s | 1 -
gas/testsuite/gas/riscv/csr-dw-regnums.d | 7 +-
gas/testsuite/gas/riscv/csr-dw-regnums.s | 9 +-
gas/testsuite/gas/riscv/no-aliases-csr.d | 23 -
.../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
.../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
.../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 4 +-
gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d | 36 ++
gas/testsuite/gas/riscv/priv-reg-pseudo.d | 36 ++
gas/testsuite/gas/riscv/priv-reg-pseudo.s | 33 ++
gas/testsuite/gas/riscv/priv-reg.d | 491 +++++++++++----------
gas/testsuite/gas/riscv/priv-reg.s | 114 ++---
gas/testsuite/gas/riscv/satp.d | 11 -
gas/testsuite/gas/riscv/satp.s | 3 -
gdb/features/riscv/32bit-csr.xml | 5 +-
gdb/features/riscv/64bit-csr.xml | 5 +-
include/opcode/riscv-opc.h | 25 +-
22 files changed, 454 insertions(+), 397 deletions(-)
delete mode 100644 gas/testsuite/gas/riscv/alias-csr.d
delete mode 100644 gas/testsuite/gas/riscv/alias-csr.s
delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
delete mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.d
create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.s
delete mode 100644 gas/testsuite/gas/riscv/satp.d
delete mode 100644 gas/testsuite/gas/riscv/satp.s
diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
deleted file mode 100644
index af5c591..0000000
--- a/gas/testsuite/gas/riscv/alias-csr.d
+++ /dev/null
@@ -1,23 +0,0 @@
-#source: alias-csr.s
-#as: -march=rv64if
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <alias_csr>:
-[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
-[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
-[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
-[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
-[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
-[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
-[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
-[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
-[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
-[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
-[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
-[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
-[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
deleted file mode 100644
index 8577de1..0000000
--- a/gas/testsuite/gas/riscv/alias-csr.s
+++ /dev/null
@@ -1,14 +0,0 @@
-alias_csr:
- frcsr t0
- fscsr t0, t2
- fscsr t2
- frrm t0
- fsrm t0, t1
- fsrm t1
- fsrmi t0, 31
- fsrmi 31
- frflags t0
- fsflags t0, t1
- fsflags t1
- fsflagsi t0, 31
- fsflagsi 31
diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
deleted file mode 100644
index 6863123..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as:
-#source: bad-csr.s
-#error_output: bad-csr.l
diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
deleted file mode 100644
index a0bb8a6..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*: Error: unknown CSR `nonexistent'
diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
deleted file mode 100644
index 6e6d27e..0000000
--- a/gas/testsuite/gas/riscv/bad-csr.s
+++ /dev/null
@@ -1 +0,0 @@
- csrr a0, nonexistent
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index a7b415e..df9642f 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -202,6 +202,7 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
+ DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
@@ -237,7 +238,8 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
- DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
+ DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
+ DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
@@ -254,12 +256,13 @@ Contents of the .* section:
DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
- DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
+ DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
+ DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
DW_CFA_nop
#...
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index b29e9da..4101a41 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -192,6 +192,7 @@ _start:
.cfi_offset mhpmcounter29h, 11892
.cfi_offset mhpmcounter30h, 11896
.cfi_offset mhpmcounter31h, 11900
+ .cfi_offset mcountinhibit, 3200
.cfi_offset mhpmevent3, 3212
.cfi_offset mhpmevent4, 3216
.cfi_offset mhpmevent5, 3220
@@ -227,7 +228,10 @@ _start:
.cfi_offset tdata3, 7820
.cfi_offset dcsr, 7872
.cfi_offset dpc, 7876
- .cfi_offset dscratch, 7880
+ .cfi_offset dscratch0, 7880
+ .cfi_offset dscratch1, 7884
+
+ # dropped in the current 1.11 priv spec.
.cfi_offset hstatus, 2048
.cfi_offset hedeleg, 2056
.cfi_offset hideleg, 2060
@@ -244,12 +248,13 @@ _start:
.cfi_offset mibound, 3596
.cfi_offset mdbase, 3600
.cfi_offset mdbound, 3604
- .cfi_offset mucounteren, 3200
.cfi_offset mscounteren, 3204
.cfi_offset mhcounteren, 3208
.cfi_offset ubadaddr, 268
.cfi_offset sbadaddr, 1292
.cfi_offset sptbr, 1536
.cfi_offset mbadaddr, 3340
+ .cfi_offset mucounteren, 3200
+ .cfi_offset dscratch, 7880
nop
.cfi_endproc
diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
deleted file mode 100644
index 2275330..0000000
--- a/gas/testsuite/gas/riscv/no-aliases-csr.d
+++ /dev/null
@@ -1,23 +0,0 @@
-#source: alias-csr.s
-#as: -march=rv64if
-#objdump: -dr -Mno-aliases
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <alias_csr>:
-[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
-[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
-[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
-[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
-[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
-[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
-[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
-[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
-[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
-[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
-[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
-[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
-[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
new file mode 100644
index 0000000..9bb3f82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
@@ -0,0 +1,3 @@
+#as:
+#source: priv-reg-fail-nonexistent.s
+#error_output: priv-reg-fail-nonexistent.l
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
new file mode 100644
index 0000000..a0bb8a6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unknown CSR `nonexistent'
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
new file mode 100644
index 0000000..6e6d27e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
@@ -0,0 +1 @@
+ csrr a0, nonexistent
diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
index 9123672..fa5a1b4 100644
--- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
+++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
@@ -31,6 +31,8 @@
.*Warning: Invalid CSR `hpmcounter29h' for the current ISA
.*Warning: Invalid CSR `hpmcounter30h' for the current ISA
.*Warning: Invalid CSR `hpmcounter31h' for the current ISA
+.*Warning: Invalid CSR `pmpcfg1' for the current ISA
+.*Warning: Invalid CSR `pmpcfg3' for the current ISA
.*Warning: Invalid CSR `mcycleh' for the current ISA
.*Warning: Invalid CSR `minstreth' for the current ISA
.*Warning: Invalid CSR `mhpmcounter3h' for the current ISA
@@ -62,5 +64,3 @@
.*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
.*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
-.*Warning: Invalid CSR `pmpcfg1' for the current ISA
-.*Warning: Invalid CSR `pmpcfg3' for the current ISA
diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
new file mode 100644
index 0000000..e0acb18
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
@@ -0,0 +1,36 @@
+#source: priv-reg-pseudo.s
+#as: -march=rv32if
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <pseudo_csr_insn>:
+[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrrs[ ]+t0,ustatus,zero
+[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrrw[ ]+zero,ustatus,t0
+[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrrs[ ]+zero,ustatus,t0
+[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrrc[ ]+zero,ustatus,t0
+[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrrwi[ ]+zero,ustatus,31
+[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrrsi[ ]+zero,ustatus,31
+[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrrci[ ]+zero,ustatus,31
+[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+csrrs[ ]+t0,cycle,zero
+[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+csrrs[ ]+t0,time,zero
+[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+csrrs[ ]+t0,instret,zero
+[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+csrrs[ ]+t0,cycleh,zero
+[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+csrrs[ ]+t0,timeh,zero
+[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+csrrs[ ]+t0,instreth,zero
+[ ]+[0-9a-f]+:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
+[ ]+[0-9a-f]+:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
+[ ]+[0-9a-f]+:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
+[ ]+[0-9a-f]+:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
+[ ]+[0-9a-f]+:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
+[ ]+[0-9a-f]+:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
+[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
+[ ]+[0-9a-f]+:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
+[ ]+[0-9a-f]+:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
+[ ]+[0-9a-f]+:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
+[ ]+[0-9a-f]+:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
+[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
+[ ]+[0-9a-f]+:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.d b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
new file mode 100644
index 0000000..4243510
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
@@ -0,0 +1,36 @@
+#source: priv-reg-pseudo.s
+#as: -march=rv32if
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <pseudo_csr_insn>:
+[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus
+[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0
+[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0
+[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0
+[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31
+[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31
+[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31
+[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0
+[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0
+[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0
+[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0
+[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0
+[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0
+[ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0
+[ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
+[ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2
+[ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0
+[ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1
+[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
+[ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
+[ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0
+[ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
+[ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1
+[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
+[ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.s b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
new file mode 100644
index 0000000..8efaa4e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
@@ -0,0 +1,33 @@
+pseudo_csr_insn:
+ # i-ext
+ csrr t0, 0x0
+ csrw 0x0, t0
+ csrs 0x0, t0
+ csrc 0x0, t0
+ csrwi 0x0, 31
+ csrsi 0x0, 31
+ csrci 0x0, 31
+
+ rdcycle t0
+ rdtime t0
+ rdinstret t0
+
+ # rv32i-ext
+ rdcycleh t0
+ rdtimeh t0
+ rdinstreth t0
+
+ # f-ext
+ frcsr t0 # frsr
+ fscsr t0, t2 # fssr
+ fscsr t2 # fssr
+ frrm t0
+ fsrm t0, t1
+ fsrm t1
+ fsrmi t0, 31
+ fsrmi 31
+ frflags t0
+ fsflags t0, t1
+ fsflags t1
+ fsflagsi t0, 31
+ fsflagsi 31
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
index 8b7a7bf..8fc41d2 100644
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ b/gas/testsuite/gas/riscv/priv-reg.d
@@ -7,247 +7,250 @@
Disassembly of section .text:
0+000 <.text>:
-[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
-[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
-[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
-[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
-[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
-[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
-[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
-[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
-[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
-[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
-[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
-[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
-[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
-[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
-[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
-[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
-[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
-[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
-[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
-[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
-[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
-[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
-[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
-[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
-[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
-[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
-[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
-[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
-[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
-[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
-[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
-[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
-[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
-[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
-[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
-[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
-[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
-[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
-[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
-[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
-[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
-[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
-[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
-[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
-[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
-[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
-[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
-[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
-[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
-[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
-[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
-[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
-[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
-[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
-[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
-[ ]+dc:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
-[ ]+e0:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
-[ ]+e4:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
-[ ]+e8:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
-[ ]+ec:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
-[ ]+f0:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
-[ ]+f4:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
-[ ]+f8:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
-[ ]+fc:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
-[ ]+100:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
-[ ]+104:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
-[ ]+108:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
-[ ]+10c:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
-[ ]+110:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
-[ ]+114:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
-[ ]+118:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
-[ ]+11c:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
-[ ]+120:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
-[ ]+124:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
-[ ]+128:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
-[ ]+12c:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
-[ ]+130:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
-[ ]+134:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
-[ ]+138:[ ]+10402573[ ]+csrr[ ]+a0,sie
-[ ]+13c:[ ]+10502573[ ]+csrr[ ]+a0,stvec
-[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
-[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
-[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
-[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
-[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
-[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
-[ ]+15c:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
-[ ]+160:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
-[ ]+164:[ ]+20402573[ ]+csrr[ ]+a0,hie
-[ ]+168:[ ]+20502573[ ]+csrr[ ]+a0,htvec
-[ ]+16c:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
-[ ]+170:[ ]+24102573[ ]+csrr[ ]+a0,hepc
-[ ]+174:[ ]+24202573[ ]+csrr[ ]+a0,hcause
-[ ]+178:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
-[ ]+17c:[ ]+24402573[ ]+csrr[ ]+a0,hip
-[ ]+180:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
-[ ]+184:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
-[ ]+188:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
-[ ]+18c:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
-[ ]+190:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
-[ ]+194:[ ]+30102573[ ]+csrr[ ]+a0,misa
-[ ]+198:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
-[ ]+19c:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
-[ ]+1a0:[ ]+30402573[ ]+csrr[ ]+a0,mie
-[ ]+1a4:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
-[ ]+1a8:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
-[ ]+1ac:[ ]+34102573[ ]+csrr[ ]+a0,mepc
-[ ]+1b0:[ ]+34202573[ ]+csrr[ ]+a0,mcause
-[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mtval
-[ ]+1b8:[ ]+34402573[ ]+csrr[ ]+a0,mip
-[ ]+1bc:[ ]+38002573[ ]+csrr[ ]+a0,mbase
-[ ]+1c0:[ ]+38102573[ ]+csrr[ ]+a0,mbound
-[ ]+1c4:[ ]+38202573[ ]+csrr[ ]+a0,mibase
-[ ]+1c8:[ ]+38302573[ ]+csrr[ ]+a0,mibound
-[ ]+1cc:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
-[ ]+1d0:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
-[ ]+1d4:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
-[ ]+1d8:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
-[ ]+1dc:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
-[ ]+1e0:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
-[ ]+1e4:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
-[ ]+1e8:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
-[ ]+1ec:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
-[ ]+1f0:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
-[ ]+1f4:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
-[ ]+1f8:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
-[ ]+1fc:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
-[ ]+200:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
-[ ]+204:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
-[ ]+208:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
-[ ]+20c:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
-[ ]+210:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
-[ ]+214:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
-[ ]+218:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
-[ ]+21c:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
-[ ]+220:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
-[ ]+224:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
-[ ]+228:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
-[ ]+22c:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
-[ ]+230:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
-[ ]+234:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
-[ ]+238:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
-[ ]+23c:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
-[ ]+240:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
-[ ]+244:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
-[ ]+248:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
-[ ]+24c:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
-[ ]+250:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
-[ ]+254:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
-[ ]+258:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
-[ ]+25c:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
-[ ]+260:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
-[ ]+264:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
-[ ]+268:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
-[ ]+26c:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
-[ ]+270:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
-[ ]+274:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
-[ ]+278:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
-[ ]+27c:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
-[ ]+280:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
-[ ]+284:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
-[ ]+288:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
-[ ]+28c:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
-[ ]+290:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
-[ ]+294:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
-[ ]+298:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
-[ ]+29c:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
-[ ]+2a0:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
-[ ]+2a4:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
-[ ]+2a8:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
-[ ]+2ac:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
-[ ]+2b0:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
-[ ]+2b4:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
-[ ]+2b8:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
-[ ]+2bc:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
-[ ]+2c0:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
-[ ]+2c4:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
-[ ]+2c8:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
-[ ]+2cc:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
-[ ]+2d0:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
-[ ]+2d4:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
-[ ]+2d8:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
-[ ]+2dc:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
-[ ]+2e0:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
-[ ]+2e4:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
-[ ]+2e8:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
-[ ]+2ec:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
-[ ]+2f0:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
-[ ]+2f4:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
-[ ]+2f8:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
-[ ]+2fc:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
-[ ]+300:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
-[ ]+304:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
-[ ]+308:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
-[ ]+30c:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
-[ ]+310:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
-[ ]+314:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
-[ ]+318:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
-[ ]+31c:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
-[ ]+320:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
-[ ]+324:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
-[ ]+328:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
-[ ]+32c:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
-[ ]+330:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
-[ ]+334:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
-[ ]+338:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
-[ ]+33c:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
-[ ]+340:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
-[ ]+344:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
-[ ]+348:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
-[ ]+34c:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
-[ ]+350:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
-[ ]+354:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
-[ ]+358:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
-[ ]+35c:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
-[ ]+360:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
-[ ]+364:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
-[ ]+368:[ ]+04302573[ ]+csrr[ ]+a0,utval
-[ ]+36c:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
-[ ]+370:[ ]+14302573[ ]+csrr[ ]+a0,stval
-[ ]+374:[ ]+18002573[ ]+csrr[ ]+a0,satp
-[ ]+378:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
-[ ]+37c:[ ]+34302573[ ]+csrr[ ]+a0,mtval
-[ ]+380:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
-[ ]+384:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
-[ ]+388:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
-[ ]+38c:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
-[ ]+390:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
-[ ]+394:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
-[ ]+398:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
-[ ]+39c:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
-[ ]+3a0:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
-[ ]+3a4:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
-[ ]+3a8:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
-[ ]+3ac:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
-[ ]+3b0:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
-[ ]+3b4:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
-[ ]+3b8:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
-[ ]+3bc:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
-[ ]+3c0:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
-[ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
-[ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
-[ ]+3cc:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
+[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
+[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
+[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
+[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
+[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
+[ ]+[0-9a-f]+:[ ]+04202573[ ]+csrr[ ]+a0,ucause
+[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
+[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
+[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
+[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
+[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
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+[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
+[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
+[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
+[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
+[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
+[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
+[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
+[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
+[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
index 72d97f9..8353f70 100644
--- a/gas/testsuite/gas/riscv/priv-reg.s
+++ b/gas/testsuite/gas/riscv/priv-reg.s
@@ -1,7 +1,8 @@
.macro csr val
csrr a0,\val
.endm
-# 1.9.1 registers
+
+ # Supported the current priv spec 1.11.
csr ustatus
csr uie
csr utvec
@@ -9,7 +10,7 @@
csr uscratch
csr uepc
csr ucause
- csr ubadaddr
+ csr utval # Added in 1.10
csr uip
csr fflags
@@ -86,26 +87,15 @@
csr sideleg
csr sie
csr stvec
+ csr scounteren # Added in 1.10
csr sscratch
csr sepc
csr scause
- csr sbadaddr
+ csr stval # Added in 1.10
csr sip
- csr sptbr
-
- csr hstatus
- csr hedeleg
- csr hideleg
- csr hie
- csr htvec
-
- csr hscratch
- csr hepc
- csr hcause
- csr hbadaddr
- csr hip
+ csr satp # Added in 1.10
csr mvendorid
csr marchid
@@ -113,24 +103,39 @@
csr mhartid
csr mstatus
- csr misa
+ csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
csr medeleg
csr mideleg
csr mie
csr mtvec
+ csr mcounteren # Added in 1.10
csr mscratch
csr mepc
csr mcause
- csr mbadaddr
+ csr mtval # Added in 1.10
csr mip
- csr mbase
- csr mbound
- csr mibase
- csr mibound
- csr mdbase
- csr mdbound
+ csr pmpcfg0 # Added in 1.10
+ csr pmpcfg1 # Added in 1.10
+ csr pmpcfg2 # Added in 1.10
+ csr pmpcfg3 # Added in 1.10
+ csr pmpaddr0 # Added in 1.10
+ csr pmpaddr1 # Added in 1.10
+ csr pmpaddr2 # Added in 1.10
+ csr pmpaddr3 # Added in 1.10
+ csr pmpaddr4 # Added in 1.10
+ csr pmpaddr5 # Added in 1.10
+ csr pmpaddr6 # Added in 1.10
+ csr pmpaddr7 # Added in 1.10
+ csr pmpaddr8 # Added in 1.10
+ csr pmpaddr9 # Added in 1.10
+ csr pmpaddr10 # Added in 1.10
+ csr pmpaddr11 # Added in 1.10
+ csr pmpaddr12 # Added in 1.10
+ csr pmpaddr13 # Added in 1.10
+ csr pmpaddr14 # Added in 1.10
+ csr pmpaddr15 # Added in 1.10
csr mcycle
csr minstret
@@ -195,10 +200,7 @@
csr mhpmcounter30h
csr mhpmcounter31h
- csr mucounteren
- csr mscounteren
- csr mhcounteren
-
+ csr mcountinhibit # Added in 1.11
csr mhpmevent3
csr mhpmevent4
csr mhpmevent5
@@ -236,34 +238,32 @@
csr dcsr
csr dpc
- csr dscratch
-# 1.10 registers
- csr utval
-
- csr scounteren
- csr stval
- csr satp
+ csr dscratch0 # Added in 1.11
+ csr dscratch1 # Added in 1.11
- csr mcounteren
- csr mtval
+ # Supported in previous priv spec, but dropped now.
+ csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
+ csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
+ csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
+ csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
+ csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
+ csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
- csr pmpcfg0
- csr pmpcfg1
- csr pmpcfg2
- csr pmpcfg3
- csr pmpaddr0
- csr pmpaddr1
- csr pmpaddr2
- csr pmpaddr3
- csr pmpaddr4
- csr pmpaddr5
- csr pmpaddr6
- csr pmpaddr7
- csr pmpaddr8
- csr pmpaddr9
- csr pmpaddr10
- csr pmpaddr11
- csr pmpaddr12
- csr pmpaddr13
- csr pmpaddr14
- csr pmpaddr15
+ csr hstatus # 0x200, dropped in 1.10
+ csr hedeleg # 0x202, dropped in 1.10
+ csr hideleg # 0x203, dropped in 1.10
+ csr hie # 0x204, dropped in 1.10
+ csr htvec # 0x205, dropped in 1.10
+ csr hscratch # 0x240, dropped in 1.10
+ csr hepc # 0x241, dropped in 1.10
+ csr hcause # 0x242, dropped in 1.10
+ csr hbadaddr # 0x243, dropped in 1.10
+ csr hip # 0x244, dropped in 1.10
+ csr mbase # 0x380, dropped in 1.10
+ csr mbound # 0x381, dropped in 1.10
+ csr mibase # 0x382, dropped in 1.10
+ csr mibound # 0x383, dropped in 1.10
+ csr mdbase # 0x384, dropped in 1.10
+ csr mdbound # 0x385, dropped in 1.10
+ csr mscounteren # 0x321, dropped in 1.10
+ csr mhcounteren # 0x322, dropped in 1.10
diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
deleted file mode 100644
index 823601c..0000000
--- a/gas/testsuite/gas/riscv/satp.d
+++ /dev/null
@@ -1,11 +0,0 @@
-#as:
-#objdump: -dr
-
-.*:[ ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <target>:
-[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
-[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
deleted file mode 100644
index f8aa766..0000000
--- a/gas/testsuite/gas/riscv/satp.s
+++ /dev/null
@@ -1,3 +0,0 @@
-target:
- csrr t0, satp
- csrr t0, sptbr
diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
index 5b79499..8173eeb 100644
--- a/gdb/features/riscv/32bit-csr.xml
+++ b/gdb/features/riscv/32bit-csr.xml
@@ -192,6 +192,7 @@
<reg name="mhpmcounter29h" bitsize="32"/>
<reg name="mhpmcounter30h" bitsize="32"/>
<reg name="mhpmcounter31h" bitsize="32"/>
+ <reg name="mcountinhibit" bitsize="32"/>
<reg name="mhpmevent3" bitsize="32"/>
<reg name="mhpmevent4" bitsize="32"/>
<reg name="mhpmevent5" bitsize="32"/>
@@ -227,7 +228,8 @@
<reg name="tdata3" bitsize="32"/>
<reg name="dcsr" bitsize="32"/>
<reg name="dpc" bitsize="32"/>
- <reg name="dscratch" bitsize="32"/>
+ <reg name="dscratch0" bitsize="32"/>
+ <reg name="dscratch1" bitsize="32"/>
<reg name="hstatus" bitsize="32"/>
<reg name="hedeleg" bitsize="32"/>
<reg name="hideleg" bitsize="32"/>
@@ -244,7 +246,6 @@
<reg name="mibound" bitsize="32"/>
<reg name="mdbase" bitsize="32"/>
<reg name="mdbound" bitsize="32"/>
- <reg name="mucounteren" bitsize="32"/>
<reg name="mscounteren" bitsize="32"/>
<reg name="mhcounteren" bitsize="32"/>
</feature>
diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
index 8ec0ffe..ed28964 100644
--- a/gdb/features/riscv/64bit-csr.xml
+++ b/gdb/features/riscv/64bit-csr.xml
@@ -127,6 +127,7 @@
<reg name="mhpmcounter29" bitsize="64"/>
<reg name="mhpmcounter30" bitsize="64"/>
<reg name="mhpmcounter31" bitsize="64"/>
+ <reg name="mcountinhibit" bitsize="64"/>
<reg name="mhpmevent3" bitsize="64"/>
<reg name="mhpmevent4" bitsize="64"/>
<reg name="mhpmevent5" bitsize="64"/>
@@ -162,7 +163,8 @@
<reg name="tdata3" bitsize="64"/>
<reg name="dcsr" bitsize="64"/>
<reg name="dpc" bitsize="64"/>
- <reg name="dscratch" bitsize="64"/>
+ <reg name="dscratch0" bitsize="64"/>
+ <reg name="dscratch1" bitsize="64"/>
<reg name="hstatus" bitsize="64"/>
<reg name="hedeleg" bitsize="64"/>
<reg name="hideleg" bitsize="64"/>
@@ -179,7 +181,6 @@
<reg name="mibound" bitsize="64"/>
<reg name="mdbase" bitsize="64"/>
<reg name="mdbound" bitsize="64"/>
- <reg name="mucounteren" bitsize="64"/>
<reg name="mscounteren" bitsize="64"/>
<reg name="mhcounteren" bitsize="64"/>
</feature>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 18d0b15..fe00bb6 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -575,6 +575,7 @@
#define MASK_CUSTOM3_RD_RS1 0x707f
#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+/* Support CSR to priv spec 1.11. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
#define CSR_UTVEC 0x5
@@ -655,6 +656,7 @@
#define CSR_SIDELEG 0x103
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
+/* scounteren is present int priv spec 1.10. */
#define CSR_SCOUNTEREN 0x106
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
@@ -667,17 +669,20 @@
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#define CSR_MSTATUS 0x300
+/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
#define CSR_MISA 0x301
#define CSR_MEDELEG 0x302
#define CSR_MIDELEG 0x303
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
+/* mcounteren is present in priv spec 1.10. */
#define CSR_MCOUNTEREN 0x306
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
+/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
@@ -760,6 +765,8 @@
#define CSR_MHPMCOUNTER29H 0xb9d
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* mcountinhibit is present in priv spec 1.11. */
+#define CSR_MCOUNTINHIBIT 0x320
#define CSR_MHPMEVENT3 0x323
#define CSR_MHPMEVENT4 0x324
#define CSR_MHPMEVENT5 0x325
@@ -795,8 +802,10 @@
#define CSR_TDATA3 0x7a3
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
-#define CSR_DSCRATCH 0x7b2
-/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
+/* dscratch0 and dscratch1 are present in priv spec 1.11. */
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
+/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
#define CSR_HSTATUS 0x200
#define CSR_HEDELEG 0x202
#define CSR_HIDELEG 0x203
@@ -807,16 +816,15 @@
#define CSR_HCAUSE 0x242
#define CSR_HBADADDR 0x243
#define CSR_HIP 0x244
-/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
#define CSR_MIBASE 0x382
#define CSR_MIBOUND 0x383
#define CSR_MDBASE 0x384
#define CSR_MDBOUND 0x385
-#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
+
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FAULT_FETCH 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
@@ -1301,6 +1309,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
+DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
@@ -1336,7 +1345,8 @@ DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
-DECLARE_CSR(dscratch, CSR_DSCRATCH, CSR_CLASS_I)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
@@ -1354,7 +1364,6 @@ DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
-DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN, CSR_CLASS_I)
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
#endif
@@ -1367,6 +1376,10 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
/* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
+/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
+DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
+/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
+DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
#endif
#ifdef DECLARE_CAUSE
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
--
2.7.4
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PING] [PATCH] RISC-V: Update CSR to privileged spec 1.11.
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
@ 2020-03-24 5:05 ` Nelson Chu
2020-03-24 8:51 ` Andrew Burgess
1 sibling, 0 replies; 34+ messages in thread
From: Nelson Chu @ 2020-03-24 5:05 UTC (permalink / raw)
To: gdb-patches, Andrew Burgess
Hi gdb,
PING :)
Thanks
Nelson
On Thu, Mar 12, 2020 at 6:01 PM Nelson Chu <nelson.chu@sifive.com> wrote:
>
> gas/
> * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
> * testsuite/gas/riscv/alias-csr.s: Likewise.
> * testsuite/gas/riscv/no-aliases-csr.d: Move this
> to priv-reg-pseudo-noalias.
> * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
> * testsuite/gas/riscv/bad-csr.l: Likewise.
> * testsuite/gas/riscv/bad-csr.s: Likewise.
> * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
> * testsuite/gas/riscv/satp.s: Likewise.
> * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
> csr instruction, including alias-csr testcase.
> * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
> * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
> pseudo instruction with objdump -Mno-aliases.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
> * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
> * testsuite/gas/riscv/priv-reg.s: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
>
> include/
> * opcode/riscv-opc.h: Update CSR to 1.11.
>
> gdb/
> * features/riscv/32bit-csr.xml: Regenerated.
> * features/riscv/64bit-csr.xml: Regenerated.
> ---
> gas/testsuite/gas/riscv/alias-csr.d | 23 -
> gas/testsuite/gas/riscv/alias-csr.s | 14 -
> gas/testsuite/gas/riscv/bad-csr.d | 3 -
> gas/testsuite/gas/riscv/bad-csr.l | 2 -
> gas/testsuite/gas/riscv/bad-csr.s | 1 -
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 7 +-
> gas/testsuite/gas/riscv/csr-dw-regnums.s | 9 +-
> gas/testsuite/gas/riscv/no-aliases-csr.d | 23 -
> .../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
> .../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
> .../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 4 +-
> gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d | 36 ++
> gas/testsuite/gas/riscv/priv-reg-pseudo.d | 36 ++
> gas/testsuite/gas/riscv/priv-reg-pseudo.s | 33 ++
> gas/testsuite/gas/riscv/priv-reg.d | 491 +++++++++++----------
> gas/testsuite/gas/riscv/priv-reg.s | 114 ++---
> gas/testsuite/gas/riscv/satp.d | 11 -
> gas/testsuite/gas/riscv/satp.s | 3 -
> gdb/features/riscv/32bit-csr.xml | 5 +-
> gdb/features/riscv/64bit-csr.xml | 5 +-
> include/opcode/riscv-opc.h | 25 +-
> 22 files changed, 454 insertions(+), 397 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/alias-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/alias-csr.s
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
> delete mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.s
> delete mode 100644 gas/testsuite/gas/riscv/satp.d
> delete mode 100644 gas/testsuite/gas/riscv/satp.s
>
> diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
> deleted file mode 100644
> index af5c591..0000000
> --- a/gas/testsuite/gas/riscv/alias-csr.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#source: alias-csr.s
> -#as: -march=rv64if
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <alias_csr>:
> -[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
> -[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> -[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
> -[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
> -[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> -[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
> -[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> -[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> -[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
> -[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> -[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
> -[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> -[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
> deleted file mode 100644
> index 8577de1..0000000
> --- a/gas/testsuite/gas/riscv/alias-csr.s
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -alias_csr:
> - frcsr t0
> - fscsr t0, t2
> - fscsr t2
> - frrm t0
> - fsrm t0, t1
> - fsrm t1
> - fsrmi t0, 31
> - fsrmi 31
> - frflags t0
> - fsflags t0, t1
> - fsflags t1
> - fsflagsi t0, 31
> - fsflagsi 31
> diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
> deleted file mode 100644
> index 6863123..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as:
> -#source: bad-csr.s
> -#error_output: bad-csr.l
> diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
> deleted file mode 100644
> index a0bb8a6..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
> deleted file mode 100644
> index 6e6d27e..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.s
> +++ /dev/null
> @@ -1 +0,0 @@
> - csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index a7b415e..df9642f 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -202,6 +202,7 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
> DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
> DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
> DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
> DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
> @@ -237,7 +238,8 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
> DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
> DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
> - DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
> DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
> DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
> DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
> @@ -254,12 +256,13 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
> DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
> DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
> - DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
> DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
> DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
> DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> DW_CFA_nop
> #...
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> index b29e9da..4101a41 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> @@ -192,6 +192,7 @@ _start:
> .cfi_offset mhpmcounter29h, 11892
> .cfi_offset mhpmcounter30h, 11896
> .cfi_offset mhpmcounter31h, 11900
> + .cfi_offset mcountinhibit, 3200
> .cfi_offset mhpmevent3, 3212
> .cfi_offset mhpmevent4, 3216
> .cfi_offset mhpmevent5, 3220
> @@ -227,7 +228,10 @@ _start:
> .cfi_offset tdata3, 7820
> .cfi_offset dcsr, 7872
> .cfi_offset dpc, 7876
> - .cfi_offset dscratch, 7880
> + .cfi_offset dscratch0, 7880
> + .cfi_offset dscratch1, 7884
> +
> + # dropped in the current 1.11 priv spec.
> .cfi_offset hstatus, 2048
> .cfi_offset hedeleg, 2056
> .cfi_offset hideleg, 2060
> @@ -244,12 +248,13 @@ _start:
> .cfi_offset mibound, 3596
> .cfi_offset mdbase, 3600
> .cfi_offset mdbound, 3604
> - .cfi_offset mucounteren, 3200
> .cfi_offset mscounteren, 3204
> .cfi_offset mhcounteren, 3208
> .cfi_offset ubadaddr, 268
> .cfi_offset sbadaddr, 1292
> .cfi_offset sptbr, 1536
> .cfi_offset mbadaddr, 3340
> + .cfi_offset mucounteren, 3200
> + .cfi_offset dscratch, 7880
> nop
> .cfi_endproc
> diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
> deleted file mode 100644
> index 2275330..0000000
> --- a/gas/testsuite/gas/riscv/no-aliases-csr.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#source: alias-csr.s
> -#as: -march=rv64if
> -#objdump: -dr -Mno-aliases
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <alias_csr>:
> -[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> -[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> -[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> -[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> -[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> -[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> -[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> -[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> -[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> -[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> -[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> -[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> -[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> new file mode 100644
> index 0000000..9bb3f82
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> @@ -0,0 +1,3 @@
> +#as:
> +#source: priv-reg-fail-nonexistent.s
> +#error_output: priv-reg-fail-nonexistent.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> new file mode 100644
> index 0000000..a0bb8a6
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> new file mode 100644
> index 0000000..6e6d27e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> @@ -0,0 +1 @@
> + csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> index 9123672..fa5a1b4 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> @@ -31,6 +31,8 @@
> .*Warning: Invalid CSR `hpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `hpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `hpmcounter31h' for the current ISA
> +.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> +.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> .*Warning: Invalid CSR `mcycleh' for the current ISA
> .*Warning: Invalid CSR `minstreth' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter3h' for the current ISA
> @@ -62,5 +64,3 @@
> .*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
> -.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> -.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> new file mode 100644
> index 0000000..e0acb18
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> @@ -0,0 +1,36 @@
> +#source: priv-reg-pseudo.s
> +#as: -march=rv32if
> +#objdump: -dr -Mno-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <pseudo_csr_insn>:
> +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrrs[ ]+t0,ustatus,zero
> +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrrw[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrrs[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrrc[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrrwi[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrrsi[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrrci[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+csrrs[ ]+t0,cycle,zero
> +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+csrrs[ ]+t0,time,zero
> +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+csrrs[ ]+t0,instret,zero
> +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+csrrs[ ]+t0,cycleh,zero
> +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+csrrs[ ]+t0,timeh,zero
> +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+csrrs[ ]+t0,instreth,zero
> +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> +[ ]+[0-9a-f]+:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> +[ ]+[0-9a-f]+:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> +[ ]+[0-9a-f]+:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.d b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> new file mode 100644
> index 0000000..4243510
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> @@ -0,0 +1,36 @@
> +#source: priv-reg-pseudo.s
> +#as: -march=rv32if
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <pseudo_csr_insn>:
> +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus
> +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> +[ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2
> +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> +[ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1
> +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> +[ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1
> +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.s b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> new file mode 100644
> index 0000000..8efaa4e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> @@ -0,0 +1,33 @@
> +pseudo_csr_insn:
> + # i-ext
> + csrr t0, 0x0
> + csrw 0x0, t0
> + csrs 0x0, t0
> + csrc 0x0, t0
> + csrwi 0x0, 31
> + csrsi 0x0, 31
> + csrci 0x0, 31
> +
> + rdcycle t0
> + rdtime t0
> + rdinstret t0
> +
> + # rv32i-ext
> + rdcycleh t0
> + rdtimeh t0
> + rdinstreth t0
> +
> + # f-ext
> + frcsr t0 # frsr
> + fscsr t0, t2 # fssr
> + fscsr t2 # fssr
> + frrm t0
> + fsrm t0, t1
> + fsrm t1
> + fsrmi t0, 31
> + fsrmi 31
> + frflags t0
> + fsflags t0, t1
> + fsflags t1
> + fsflagsi t0, 31
> + fsflagsi 31
> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> index 8b7a7bf..8fc41d2 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ b/gas/testsuite/gas/riscv/priv-reg.d
> @@ -7,247 +7,250 @@
> Disassembly of section .text:
>
> 0+000 <.text>:
> -[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> -[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
> -[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> -[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> -[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> -[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> -[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
> -[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
> -[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
> -[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
> -[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
> -[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
> -[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
> -[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> -[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> -[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> -[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> -[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> -[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> -[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> -[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> -[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> -[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> -[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> -[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> -[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> -[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> -[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> -[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> -[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> -[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> -[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> -[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> -[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> -[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> -[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> -[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> -[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> -[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> -[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> -[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> -[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> -[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> -[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> -[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> -[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> -[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> -[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> -[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> -[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> -[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> -[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> -[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> -[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
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> +[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> +[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> +[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> +[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> +[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> +[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> +[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> +[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> +[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> +[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> +[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> +[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> +[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> +[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> +[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> +[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> +[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> +[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
> +[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> +[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
> +[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> +[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> +[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
> +[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> +[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
> +[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> +[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
> +[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
> +[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
> +[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
> +[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
> +[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
> +[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> +[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> +[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
> +[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> +[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> +[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> +[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> +[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> +[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> +[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> +[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> +[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> +[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> +[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> +[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> +[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> +[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> +[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> +[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> +[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> +[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> +[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> +[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> +[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> +[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> +[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> +[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> +[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> +[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> +[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> +[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> +[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> +[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> +[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> +[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> +[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> +[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> +[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> +[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> +[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> +[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> +[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> +[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> +[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> +[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> +[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> +[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> +[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> +[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> +[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> +[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> +[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> +[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> +[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> +[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> +[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> +[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> +[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> +[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> +[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> +[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> +[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> +[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> +[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> +[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> +[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> +[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> +[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> +[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> +[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> +[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> +[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> +[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> +[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> +[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> +[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> +[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> +[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> +[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> +[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> +[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> +[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> +[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> +[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> +[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> +[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> +[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> +[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> +[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> +[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> +[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> +[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> +[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> +[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> +[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> +[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> +[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> +[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> +[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> +[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> +[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> +[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> +[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> +[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> +[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> +[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> +[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> +[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> +[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> +[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> +[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> +[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> +[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> +[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> +[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> +[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> +[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> +[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> +[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> +[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> +[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> +[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> +[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> +[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> +[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> +[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> +[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> +[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> +[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
> +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
> +[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> +[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> +[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> +[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> +[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> +[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> +[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> +[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
> index 72d97f9..8353f70 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.s
> +++ b/gas/testsuite/gas/riscv/priv-reg.s
> @@ -1,7 +1,8 @@
> .macro csr val
> csrr a0,\val
> .endm
> -# 1.9.1 registers
> +
> + # Supported the current priv spec 1.11.
> csr ustatus
> csr uie
> csr utvec
> @@ -9,7 +10,7 @@
> csr uscratch
> csr uepc
> csr ucause
> - csr ubadaddr
> + csr utval # Added in 1.10
> csr uip
>
> csr fflags
> @@ -86,26 +87,15 @@
> csr sideleg
> csr sie
> csr stvec
> + csr scounteren # Added in 1.10
>
> csr sscratch
> csr sepc
> csr scause
> - csr sbadaddr
> + csr stval # Added in 1.10
> csr sip
>
> - csr sptbr
> -
> - csr hstatus
> - csr hedeleg
> - csr hideleg
> - csr hie
> - csr htvec
> -
> - csr hscratch
> - csr hepc
> - csr hcause
> - csr hbadaddr
> - csr hip
> + csr satp # Added in 1.10
>
> csr mvendorid
> csr marchid
> @@ -113,24 +103,39 @@
> csr mhartid
>
> csr mstatus
> - csr misa
> + csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
> csr medeleg
> csr mideleg
> csr mie
> csr mtvec
> + csr mcounteren # Added in 1.10
>
> csr mscratch
> csr mepc
> csr mcause
> - csr mbadaddr
> + csr mtval # Added in 1.10
> csr mip
>
> - csr mbase
> - csr mbound
> - csr mibase
> - csr mibound
> - csr mdbase
> - csr mdbound
> + csr pmpcfg0 # Added in 1.10
> + csr pmpcfg1 # Added in 1.10
> + csr pmpcfg2 # Added in 1.10
> + csr pmpcfg3 # Added in 1.10
> + csr pmpaddr0 # Added in 1.10
> + csr pmpaddr1 # Added in 1.10
> + csr pmpaddr2 # Added in 1.10
> + csr pmpaddr3 # Added in 1.10
> + csr pmpaddr4 # Added in 1.10
> + csr pmpaddr5 # Added in 1.10
> + csr pmpaddr6 # Added in 1.10
> + csr pmpaddr7 # Added in 1.10
> + csr pmpaddr8 # Added in 1.10
> + csr pmpaddr9 # Added in 1.10
> + csr pmpaddr10 # Added in 1.10
> + csr pmpaddr11 # Added in 1.10
> + csr pmpaddr12 # Added in 1.10
> + csr pmpaddr13 # Added in 1.10
> + csr pmpaddr14 # Added in 1.10
> + csr pmpaddr15 # Added in 1.10
>
> csr mcycle
> csr minstret
> @@ -195,10 +200,7 @@
> csr mhpmcounter30h
> csr mhpmcounter31h
>
> - csr mucounteren
> - csr mscounteren
> - csr mhcounteren
> -
> + csr mcountinhibit # Added in 1.11
> csr mhpmevent3
> csr mhpmevent4
> csr mhpmevent5
> @@ -236,34 +238,32 @@
>
> csr dcsr
> csr dpc
> - csr dscratch
> -# 1.10 registers
> - csr utval
> -
> - csr scounteren
> - csr stval
> - csr satp
> + csr dscratch0 # Added in 1.11
> + csr dscratch1 # Added in 1.11
>
> - csr mcounteren
> - csr mtval
> + # Supported in previous priv spec, but dropped now.
> + csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
> + csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
> + csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
> + csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
> + csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
> + csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
>
> - csr pmpcfg0
> - csr pmpcfg1
> - csr pmpcfg2
> - csr pmpcfg3
> - csr pmpaddr0
> - csr pmpaddr1
> - csr pmpaddr2
> - csr pmpaddr3
> - csr pmpaddr4
> - csr pmpaddr5
> - csr pmpaddr6
> - csr pmpaddr7
> - csr pmpaddr8
> - csr pmpaddr9
> - csr pmpaddr10
> - csr pmpaddr11
> - csr pmpaddr12
> - csr pmpaddr13
> - csr pmpaddr14
> - csr pmpaddr15
> + csr hstatus # 0x200, dropped in 1.10
> + csr hedeleg # 0x202, dropped in 1.10
> + csr hideleg # 0x203, dropped in 1.10
> + csr hie # 0x204, dropped in 1.10
> + csr htvec # 0x205, dropped in 1.10
> + csr hscratch # 0x240, dropped in 1.10
> + csr hepc # 0x241, dropped in 1.10
> + csr hcause # 0x242, dropped in 1.10
> + csr hbadaddr # 0x243, dropped in 1.10
> + csr hip # 0x244, dropped in 1.10
> + csr mbase # 0x380, dropped in 1.10
> + csr mbound # 0x381, dropped in 1.10
> + csr mibase # 0x382, dropped in 1.10
> + csr mibound # 0x383, dropped in 1.10
> + csr mdbase # 0x384, dropped in 1.10
> + csr mdbound # 0x385, dropped in 1.10
> + csr mscounteren # 0x321, dropped in 1.10
> + csr mhcounteren # 0x322, dropped in 1.10
> diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
> deleted file mode 100644
> index 823601c..0000000
> --- a/gas/testsuite/gas/riscv/satp.d
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -#as:
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> -[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
> deleted file mode 100644
> index f8aa766..0000000
> --- a/gas/testsuite/gas/riscv/satp.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - csrr t0, satp
> - csrr t0, sptbr
> diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
> index 5b79499..8173eeb 100644
> --- a/gdb/features/riscv/32bit-csr.xml
> +++ b/gdb/features/riscv/32bit-csr.xml
> @@ -192,6 +192,7 @@
> <reg name="mhpmcounter29h" bitsize="32"/>
> <reg name="mhpmcounter30h" bitsize="32"/>
> <reg name="mhpmcounter31h" bitsize="32"/>
> + <reg name="mcountinhibit" bitsize="32"/>
> <reg name="mhpmevent3" bitsize="32"/>
> <reg name="mhpmevent4" bitsize="32"/>
> <reg name="mhpmevent5" bitsize="32"/>
> @@ -227,7 +228,8 @@
> <reg name="tdata3" bitsize="32"/>
> <reg name="dcsr" bitsize="32"/>
> <reg name="dpc" bitsize="32"/>
> - <reg name="dscratch" bitsize="32"/>
> + <reg name="dscratch0" bitsize="32"/>
> + <reg name="dscratch1" bitsize="32"/>
> <reg name="hstatus" bitsize="32"/>
> <reg name="hedeleg" bitsize="32"/>
> <reg name="hideleg" bitsize="32"/>
> @@ -244,7 +246,6 @@
> <reg name="mibound" bitsize="32"/>
> <reg name="mdbase" bitsize="32"/>
> <reg name="mdbound" bitsize="32"/>
> - <reg name="mucounteren" bitsize="32"/>
> <reg name="mscounteren" bitsize="32"/>
> <reg name="mhcounteren" bitsize="32"/>
> </feature>
> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
> index 8ec0ffe..ed28964 100644
> --- a/gdb/features/riscv/64bit-csr.xml
> +++ b/gdb/features/riscv/64bit-csr.xml
> @@ -127,6 +127,7 @@
> <reg name="mhpmcounter29" bitsize="64"/>
> <reg name="mhpmcounter30" bitsize="64"/>
> <reg name="mhpmcounter31" bitsize="64"/>
> + <reg name="mcountinhibit" bitsize="64"/>
> <reg name="mhpmevent3" bitsize="64"/>
> <reg name="mhpmevent4" bitsize="64"/>
> <reg name="mhpmevent5" bitsize="64"/>
> @@ -162,7 +163,8 @@
> <reg name="tdata3" bitsize="64"/>
> <reg name="dcsr" bitsize="64"/>
> <reg name="dpc" bitsize="64"/>
> - <reg name="dscratch" bitsize="64"/>
> + <reg name="dscratch0" bitsize="64"/>
> + <reg name="dscratch1" bitsize="64"/>
> <reg name="hstatus" bitsize="64"/>
> <reg name="hedeleg" bitsize="64"/>
> <reg name="hideleg" bitsize="64"/>
> @@ -179,7 +181,6 @@
> <reg name="mibound" bitsize="64"/>
> <reg name="mdbase" bitsize="64"/>
> <reg name="mdbound" bitsize="64"/>
> - <reg name="mucounteren" bitsize="64"/>
> <reg name="mscounteren" bitsize="64"/>
> <reg name="mhcounteren" bitsize="64"/>
> </feature>
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 18d0b15..fe00bb6 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -575,6 +575,7 @@
> #define MASK_CUSTOM3_RD_RS1 0x707f
> #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
> #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
> +/* Support CSR to priv spec 1.11. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> #define CSR_UTVEC 0x5
> @@ -655,6 +656,7 @@
> #define CSR_SIDELEG 0x103
> #define CSR_SIE 0x104
> #define CSR_STVEC 0x105
> +/* scounteren is present int priv spec 1.10. */
> #define CSR_SCOUNTEREN 0x106
> #define CSR_SSCRATCH 0x140
> #define CSR_SEPC 0x141
> @@ -667,17 +669,20 @@
> #define CSR_MIMPID 0xf13
> #define CSR_MHARTID 0xf14
> #define CSR_MSTATUS 0x300
> +/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MISA 0x301
> #define CSR_MEDELEG 0x302
> #define CSR_MIDELEG 0x303
> #define CSR_MIE 0x304
> #define CSR_MTVEC 0x305
> +/* mcounteren is present in priv spec 1.10. */
> #define CSR_MCOUNTEREN 0x306
> #define CSR_MSCRATCH 0x340
> #define CSR_MEPC 0x341
> #define CSR_MCAUSE 0x342
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> +/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
> #define CSR_PMPCFG0 0x3a0
> #define CSR_PMPCFG1 0x3a1
> #define CSR_PMPCFG2 0x3a2
> @@ -760,6 +765,8 @@
> #define CSR_MHPMCOUNTER29H 0xb9d
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
> +/* mcountinhibit is present in priv spec 1.11. */
> +#define CSR_MCOUNTINHIBIT 0x320
> #define CSR_MHPMEVENT3 0x323
> #define CSR_MHPMEVENT4 0x324
> #define CSR_MHPMEVENT5 0x325
> @@ -795,8 +802,10 @@
> #define CSR_TDATA3 0x7a3
> #define CSR_DCSR 0x7b0
> #define CSR_DPC 0x7b1
> -#define CSR_DSCRATCH 0x7b2
> -/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> +/* dscratch0 and dscratch1 are present in priv spec 1.11. */
> +#define CSR_DSCRATCH0 0x7b2
> +#define CSR_DSCRATCH1 0x7b3
> +/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
> #define CSR_HSTATUS 0x200
> #define CSR_HEDELEG 0x202
> #define CSR_HIDELEG 0x203
> @@ -807,16 +816,15 @@
> #define CSR_HCAUSE 0x242
> #define CSR_HBADADDR 0x243
> #define CSR_HIP 0x244
> -/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MBASE 0x380
> #define CSR_MBOUND 0x381
> #define CSR_MIBASE 0x382
> #define CSR_MIBOUND 0x383
> #define CSR_MDBASE 0x384
> #define CSR_MDBOUND 0x385
> -#define CSR_MUCOUNTEREN 0x320
> #define CSR_MSCOUNTEREN 0x321
> #define CSR_MHCOUNTEREN 0x322
> +
> #define CAUSE_MISALIGNED_FETCH 0x0
> #define CAUSE_FAULT_FETCH 0x1
> #define CAUSE_ILLEGAL_INSTRUCTION 0x2
> @@ -1301,6 +1309,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
> +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
> @@ -1336,7 +1345,8 @@ DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
> DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
> DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
> DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
> -DECLARE_CSR(dscratch, CSR_DSCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
> +DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
> /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
> DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
> @@ -1354,7 +1364,6 @@ DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
> DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
> DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
> DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
> -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN, CSR_CLASS_I)
> DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
> DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
> #endif
> @@ -1367,6 +1376,10 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
> DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
> /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
> +/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
> +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> +/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
> +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
> #endif
> #ifdef DECLARE_CAUSE
> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] RISC-V: Update CSR to privileged spec 1.11.
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
2020-03-24 5:05 ` [PING] " Nelson Chu
@ 2020-03-24 8:51 ` Andrew Burgess
2020-03-24 9:11 ` Nelson Chu
1 sibling, 1 reply; 34+ messages in thread
From: Andrew Burgess @ 2020-03-24 8:51 UTC (permalink / raw)
To: Nelson Chu; +Cc: gdb-patches, jimw
* Nelson Chu <nelson.chu@sifive.com> [2020-03-12 03:00:57 -0700]:
> gas/
> * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
> * testsuite/gas/riscv/alias-csr.s: Likewise.
> * testsuite/gas/riscv/no-aliases-csr.d: Move this
> to priv-reg-pseudo-noalias.
> * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
> * testsuite/gas/riscv/bad-csr.l: Likewise.
> * testsuite/gas/riscv/bad-csr.s: Likewise.
> * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
> * testsuite/gas/riscv/satp.s: Likewise.
> * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
> csr instruction, including alias-csr testcase.
> * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
> * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
> pseudo instruction with objdump -Mno-aliases.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
> * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
> * testsuite/gas/riscv/priv-reg.s: Likewise.
> * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
> * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
>
> include/
> * opcode/riscv-opc.h: Update CSR to 1.11.
>
> gdb/
> * features/riscv/32bit-csr.xml: Regenerated.
> * features/riscv/64bit-csr.xml: Regenerated.
Sorry for missing this. The gdb/* parts are approved. I can't
approve any of the other changes.
Thanks,
Andrew
> ---
> gas/testsuite/gas/riscv/alias-csr.d | 23 -
> gas/testsuite/gas/riscv/alias-csr.s | 14 -
> gas/testsuite/gas/riscv/bad-csr.d | 3 -
> gas/testsuite/gas/riscv/bad-csr.l | 2 -
> gas/testsuite/gas/riscv/bad-csr.s | 1 -
> gas/testsuite/gas/riscv/csr-dw-regnums.d | 7 +-
> gas/testsuite/gas/riscv/csr-dw-regnums.s | 9 +-
> gas/testsuite/gas/riscv/no-aliases-csr.d | 23 -
> .../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
> .../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
> .../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
> gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 4 +-
> gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d | 36 ++
> gas/testsuite/gas/riscv/priv-reg-pseudo.d | 36 ++
> gas/testsuite/gas/riscv/priv-reg-pseudo.s | 33 ++
> gas/testsuite/gas/riscv/priv-reg.d | 491 +++++++++++----------
> gas/testsuite/gas/riscv/priv-reg.s | 114 ++---
> gas/testsuite/gas/riscv/satp.d | 11 -
> gas/testsuite/gas/riscv/satp.s | 3 -
> gdb/features/riscv/32bit-csr.xml | 5 +-
> gdb/features/riscv/64bit-csr.xml | 5 +-
> include/opcode/riscv-opc.h | 25 +-
> 22 files changed, 454 insertions(+), 397 deletions(-)
> delete mode 100644 gas/testsuite/gas/riscv/alias-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/alias-csr.s
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
> delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
> delete mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.d
> create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.s
> delete mode 100644 gas/testsuite/gas/riscv/satp.d
> delete mode 100644 gas/testsuite/gas/riscv/satp.s
>
> diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
> deleted file mode 100644
> index af5c591..0000000
> --- a/gas/testsuite/gas/riscv/alias-csr.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#source: alias-csr.s
> -#as: -march=rv64if
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <alias_csr>:
> -[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
> -[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> -[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
> -[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
> -[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> -[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
> -[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> -[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> -[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
> -[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> -[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
> -[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> -[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
> deleted file mode 100644
> index 8577de1..0000000
> --- a/gas/testsuite/gas/riscv/alias-csr.s
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -alias_csr:
> - frcsr t0
> - fscsr t0, t2
> - fscsr t2
> - frrm t0
> - fsrm t0, t1
> - fsrm t1
> - fsrmi t0, 31
> - fsrmi 31
> - frflags t0
> - fsflags t0, t1
> - fsflags t1
> - fsflagsi t0, 31
> - fsflagsi 31
> diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
> deleted file mode 100644
> index 6863123..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.d
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -#as:
> -#source: bad-csr.s
> -#error_output: bad-csr.l
> diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
> deleted file mode 100644
> index a0bb8a6..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.l
> +++ /dev/null
> @@ -1,2 +0,0 @@
> -.*: Assembler messages:
> -.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
> deleted file mode 100644
> index 6e6d27e..0000000
> --- a/gas/testsuite/gas/riscv/bad-csr.s
> +++ /dev/null
> @@ -1 +0,0 @@
> - csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> index a7b415e..df9642f 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> @@ -202,6 +202,7 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
> DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
> DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
> DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
> DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
> @@ -237,7 +238,8 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
> DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
> DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
> - DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> + DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
> DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
> DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
> DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
> @@ -254,12 +256,13 @@ Contents of the .* section:
> DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
> DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
> DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
> - DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
> DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
> DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
> DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
> DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> DW_CFA_nop
> #...
> diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> index b29e9da..4101a41 100644
> --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> @@ -192,6 +192,7 @@ _start:
> .cfi_offset mhpmcounter29h, 11892
> .cfi_offset mhpmcounter30h, 11896
> .cfi_offset mhpmcounter31h, 11900
> + .cfi_offset mcountinhibit, 3200
> .cfi_offset mhpmevent3, 3212
> .cfi_offset mhpmevent4, 3216
> .cfi_offset mhpmevent5, 3220
> @@ -227,7 +228,10 @@ _start:
> .cfi_offset tdata3, 7820
> .cfi_offset dcsr, 7872
> .cfi_offset dpc, 7876
> - .cfi_offset dscratch, 7880
> + .cfi_offset dscratch0, 7880
> + .cfi_offset dscratch1, 7884
> +
> + # dropped in the current 1.11 priv spec.
> .cfi_offset hstatus, 2048
> .cfi_offset hedeleg, 2056
> .cfi_offset hideleg, 2060
> @@ -244,12 +248,13 @@ _start:
> .cfi_offset mibound, 3596
> .cfi_offset mdbase, 3600
> .cfi_offset mdbound, 3604
> - .cfi_offset mucounteren, 3200
> .cfi_offset mscounteren, 3204
> .cfi_offset mhcounteren, 3208
> .cfi_offset ubadaddr, 268
> .cfi_offset sbadaddr, 1292
> .cfi_offset sptbr, 1536
> .cfi_offset mbadaddr, 3340
> + .cfi_offset mucounteren, 3200
> + .cfi_offset dscratch, 7880
> nop
> .cfi_endproc
> diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
> deleted file mode 100644
> index 2275330..0000000
> --- a/gas/testsuite/gas/riscv/no-aliases-csr.d
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#source: alias-csr.s
> -#as: -march=rv64if
> -#objdump: -dr -Mno-aliases
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <alias_csr>:
> -[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> -[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> -[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> -[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> -[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> -[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> -[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> -[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> -[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> -[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> -[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> -[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> -[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> new file mode 100644
> index 0000000..9bb3f82
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> @@ -0,0 +1,3 @@
> +#as:
> +#source: priv-reg-fail-nonexistent.s
> +#error_output: priv-reg-fail-nonexistent.l
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> new file mode 100644
> index 0000000..a0bb8a6
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*: Error: unknown CSR `nonexistent'
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> new file mode 100644
> index 0000000..6e6d27e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> @@ -0,0 +1 @@
> + csrr a0, nonexistent
> diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> index 9123672..fa5a1b4 100644
> --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> @@ -31,6 +31,8 @@
> .*Warning: Invalid CSR `hpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `hpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `hpmcounter31h' for the current ISA
> +.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> +.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> .*Warning: Invalid CSR `mcycleh' for the current ISA
> .*Warning: Invalid CSR `minstreth' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter3h' for the current ISA
> @@ -62,5 +64,3 @@
> .*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
> .*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
> -.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> -.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> new file mode 100644
> index 0000000..e0acb18
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> @@ -0,0 +1,36 @@
> +#source: priv-reg-pseudo.s
> +#as: -march=rv32if
> +#objdump: -dr -Mno-aliases
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <pseudo_csr_insn>:
> +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrrs[ ]+t0,ustatus,zero
> +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrrw[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrrs[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrrc[ ]+zero,ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrrwi[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrrsi[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrrci[ ]+zero,ustatus,31
> +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+csrrs[ ]+t0,cycle,zero
> +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+csrrs[ ]+t0,time,zero
> +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+csrrs[ ]+t0,instret,zero
> +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+csrrs[ ]+t0,cycleh,zero
> +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+csrrs[ ]+t0,timeh,zero
> +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+csrrs[ ]+t0,instreth,zero
> +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> +[ ]+[0-9a-f]+:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> +[ ]+[0-9a-f]+:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> +[ ]+[0-9a-f]+:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.d b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> new file mode 100644
> index 0000000..4243510
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> @@ -0,0 +1,36 @@
> +#source: priv-reg-pseudo.s
> +#as: -march=rv32if
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <pseudo_csr_insn>:
> +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus
> +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0
> +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31
> +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> +[ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2
> +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> +[ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1
> +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0
> +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> +[ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1
> +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.s b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> new file mode 100644
> index 0000000..8efaa4e
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> @@ -0,0 +1,33 @@
> +pseudo_csr_insn:
> + # i-ext
> + csrr t0, 0x0
> + csrw 0x0, t0
> + csrs 0x0, t0
> + csrc 0x0, t0
> + csrwi 0x0, 31
> + csrsi 0x0, 31
> + csrci 0x0, 31
> +
> + rdcycle t0
> + rdtime t0
> + rdinstret t0
> +
> + # rv32i-ext
> + rdcycleh t0
> + rdtimeh t0
> + rdinstreth t0
> +
> + # f-ext
> + frcsr t0 # frsr
> + fscsr t0, t2 # fssr
> + fscsr t2 # fssr
> + frrm t0
> + fsrm t0, t1
> + fsrm t1
> + fsrmi t0, 31
> + fsrmi 31
> + frflags t0
> + fsflags t0, t1
> + fsflags t1
> + fsflagsi t0, 31
> + fsflagsi 31
> diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> index 8b7a7bf..8fc41d2 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.d
> +++ b/gas/testsuite/gas/riscv/priv-reg.d
> @@ -7,247 +7,250 @@
> Disassembly of section .text:
>
> 0+000 <.text>:
> -[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> -[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
> -[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> -[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> -[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> -[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> -[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
> -[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
> -[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
> -[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
> -[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
> -[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
> -[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
> -[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
> -[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> -[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> -[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> -[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> -[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> -[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> -[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> -[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> -[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> -[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> -[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> -[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> -[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> -[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> -[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> -[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> -[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> -[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> -[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> -[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> -[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> -[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> -[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> -[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> -[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> -[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> -[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> -[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> -[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> -[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> -[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> -[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> -[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> -[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> -[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> -[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> -[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> -[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> -[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> -[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> -[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
> -[ ]+dc:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
> -[ ]+e0:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
> -[ ]+e4:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
> -[ ]+e8:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
> -[ ]+ec:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
> -[ ]+f0:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
> -[ ]+f4:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> -[ ]+f8:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> -[ ]+fc:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> -[ ]+100:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> -[ ]+104:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> -[ ]+108:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> -[ ]+10c:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> -[ ]+110:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> -[ ]+114:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> -[ ]+118:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> -[ ]+11c:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> -[ ]+120:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> -[ ]+124:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> -[ ]+128:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> -[ ]+12c:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> -[ ]+130:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> -[ ]+134:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> -[ ]+138:[ ]+10402573[ ]+csrr[ ]+a0,sie
> -[ ]+13c:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> -[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> -[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> -[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
> -[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
> -[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
> -[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
> -[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> -[ ]+15c:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> -[ ]+160:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> -[ ]+164:[ ]+20402573[ ]+csrr[ ]+a0,hie
> -[ ]+168:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> -[ ]+16c:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
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> +[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
> +[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> +[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> +[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
> +[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> +[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> +[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> +[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> +[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> +[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> +[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> +[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> +[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> +[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> +[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> +[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> +[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> +[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> +[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> +[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> +[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> +[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> +[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> +[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> +[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> +[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> +[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> +[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> +[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> +[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> +[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> +[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> +[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> +[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> +[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> +[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> +[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> +[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> +[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> +[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> +[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> +[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> +[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> +[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> +[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> +[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> +[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> +[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> +[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> +[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> +[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> +[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> +[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> +[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> +[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> +[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> +[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> +[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> +[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> +[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> +[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> +[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> +[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> +[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> +[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> +[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> +[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> +[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> +[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> +[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> +[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> +[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> +[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> +[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> +[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> +[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> +[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> +[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> +[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> +[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> +[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> +[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> +[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> +[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> +[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> +[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> +[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> +[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> +[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> +[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> +[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> +[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> +[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> +[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> +[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> +[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> +[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> +[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> +[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> +[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> +[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> +[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> +[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> +[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> +[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> +[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> +[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> +[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> +[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> +[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> +[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> +[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> +[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> +[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> +[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> +[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> +[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> +[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> +[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> +[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> +[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> +[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> +[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> +[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> +[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> +[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> +[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> +[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> +[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> +[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
> +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
> +[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> +[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> +[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> +[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> +[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> +[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> +[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> +[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
> index 72d97f9..8353f70 100644
> --- a/gas/testsuite/gas/riscv/priv-reg.s
> +++ b/gas/testsuite/gas/riscv/priv-reg.s
> @@ -1,7 +1,8 @@
> .macro csr val
> csrr a0,\val
> .endm
> -# 1.9.1 registers
> +
> + # Supported the current priv spec 1.11.
> csr ustatus
> csr uie
> csr utvec
> @@ -9,7 +10,7 @@
> csr uscratch
> csr uepc
> csr ucause
> - csr ubadaddr
> + csr utval # Added in 1.10
> csr uip
>
> csr fflags
> @@ -86,26 +87,15 @@
> csr sideleg
> csr sie
> csr stvec
> + csr scounteren # Added in 1.10
>
> csr sscratch
> csr sepc
> csr scause
> - csr sbadaddr
> + csr stval # Added in 1.10
> csr sip
>
> - csr sptbr
> -
> - csr hstatus
> - csr hedeleg
> - csr hideleg
> - csr hie
> - csr htvec
> -
> - csr hscratch
> - csr hepc
> - csr hcause
> - csr hbadaddr
> - csr hip
> + csr satp # Added in 1.10
>
> csr mvendorid
> csr marchid
> @@ -113,24 +103,39 @@
> csr mhartid
>
> csr mstatus
> - csr misa
> + csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
> csr medeleg
> csr mideleg
> csr mie
> csr mtvec
> + csr mcounteren # Added in 1.10
>
> csr mscratch
> csr mepc
> csr mcause
> - csr mbadaddr
> + csr mtval # Added in 1.10
> csr mip
>
> - csr mbase
> - csr mbound
> - csr mibase
> - csr mibound
> - csr mdbase
> - csr mdbound
> + csr pmpcfg0 # Added in 1.10
> + csr pmpcfg1 # Added in 1.10
> + csr pmpcfg2 # Added in 1.10
> + csr pmpcfg3 # Added in 1.10
> + csr pmpaddr0 # Added in 1.10
> + csr pmpaddr1 # Added in 1.10
> + csr pmpaddr2 # Added in 1.10
> + csr pmpaddr3 # Added in 1.10
> + csr pmpaddr4 # Added in 1.10
> + csr pmpaddr5 # Added in 1.10
> + csr pmpaddr6 # Added in 1.10
> + csr pmpaddr7 # Added in 1.10
> + csr pmpaddr8 # Added in 1.10
> + csr pmpaddr9 # Added in 1.10
> + csr pmpaddr10 # Added in 1.10
> + csr pmpaddr11 # Added in 1.10
> + csr pmpaddr12 # Added in 1.10
> + csr pmpaddr13 # Added in 1.10
> + csr pmpaddr14 # Added in 1.10
> + csr pmpaddr15 # Added in 1.10
>
> csr mcycle
> csr minstret
> @@ -195,10 +200,7 @@
> csr mhpmcounter30h
> csr mhpmcounter31h
>
> - csr mucounteren
> - csr mscounteren
> - csr mhcounteren
> -
> + csr mcountinhibit # Added in 1.11
> csr mhpmevent3
> csr mhpmevent4
> csr mhpmevent5
> @@ -236,34 +238,32 @@
>
> csr dcsr
> csr dpc
> - csr dscratch
> -# 1.10 registers
> - csr utval
> -
> - csr scounteren
> - csr stval
> - csr satp
> + csr dscratch0 # Added in 1.11
> + csr dscratch1 # Added in 1.11
>
> - csr mcounteren
> - csr mtval
> + # Supported in previous priv spec, but dropped now.
> + csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
> + csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
> + csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
> + csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
> + csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
> + csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
>
> - csr pmpcfg0
> - csr pmpcfg1
> - csr pmpcfg2
> - csr pmpcfg3
> - csr pmpaddr0
> - csr pmpaddr1
> - csr pmpaddr2
> - csr pmpaddr3
> - csr pmpaddr4
> - csr pmpaddr5
> - csr pmpaddr6
> - csr pmpaddr7
> - csr pmpaddr8
> - csr pmpaddr9
> - csr pmpaddr10
> - csr pmpaddr11
> - csr pmpaddr12
> - csr pmpaddr13
> - csr pmpaddr14
> - csr pmpaddr15
> + csr hstatus # 0x200, dropped in 1.10
> + csr hedeleg # 0x202, dropped in 1.10
> + csr hideleg # 0x203, dropped in 1.10
> + csr hie # 0x204, dropped in 1.10
> + csr htvec # 0x205, dropped in 1.10
> + csr hscratch # 0x240, dropped in 1.10
> + csr hepc # 0x241, dropped in 1.10
> + csr hcause # 0x242, dropped in 1.10
> + csr hbadaddr # 0x243, dropped in 1.10
> + csr hip # 0x244, dropped in 1.10
> + csr mbase # 0x380, dropped in 1.10
> + csr mbound # 0x381, dropped in 1.10
> + csr mibase # 0x382, dropped in 1.10
> + csr mibound # 0x383, dropped in 1.10
> + csr mdbase # 0x384, dropped in 1.10
> + csr mdbound # 0x385, dropped in 1.10
> + csr mscounteren # 0x321, dropped in 1.10
> + csr mhcounteren # 0x322, dropped in 1.10
> diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
> deleted file mode 100644
> index 823601c..0000000
> --- a/gas/testsuite/gas/riscv/satp.d
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -#as:
> -#objdump: -dr
> -
> -.*:[ ]+file format .*
> -
> -
> -Disassembly of section .text:
> -
> -0+000 <target>:
> -[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> -[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
> deleted file mode 100644
> index f8aa766..0000000
> --- a/gas/testsuite/gas/riscv/satp.s
> +++ /dev/null
> @@ -1,3 +0,0 @@
> -target:
> - csrr t0, satp
> - csrr t0, sptbr
> diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
> index 5b79499..8173eeb 100644
> --- a/gdb/features/riscv/32bit-csr.xml
> +++ b/gdb/features/riscv/32bit-csr.xml
> @@ -192,6 +192,7 @@
> <reg name="mhpmcounter29h" bitsize="32"/>
> <reg name="mhpmcounter30h" bitsize="32"/>
> <reg name="mhpmcounter31h" bitsize="32"/>
> + <reg name="mcountinhibit" bitsize="32"/>
> <reg name="mhpmevent3" bitsize="32"/>
> <reg name="mhpmevent4" bitsize="32"/>
> <reg name="mhpmevent5" bitsize="32"/>
> @@ -227,7 +228,8 @@
> <reg name="tdata3" bitsize="32"/>
> <reg name="dcsr" bitsize="32"/>
> <reg name="dpc" bitsize="32"/>
> - <reg name="dscratch" bitsize="32"/>
> + <reg name="dscratch0" bitsize="32"/>
> + <reg name="dscratch1" bitsize="32"/>
> <reg name="hstatus" bitsize="32"/>
> <reg name="hedeleg" bitsize="32"/>
> <reg name="hideleg" bitsize="32"/>
> @@ -244,7 +246,6 @@
> <reg name="mibound" bitsize="32"/>
> <reg name="mdbase" bitsize="32"/>
> <reg name="mdbound" bitsize="32"/>
> - <reg name="mucounteren" bitsize="32"/>
> <reg name="mscounteren" bitsize="32"/>
> <reg name="mhcounteren" bitsize="32"/>
> </feature>
> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
> index 8ec0ffe..ed28964 100644
> --- a/gdb/features/riscv/64bit-csr.xml
> +++ b/gdb/features/riscv/64bit-csr.xml
> @@ -127,6 +127,7 @@
> <reg name="mhpmcounter29" bitsize="64"/>
> <reg name="mhpmcounter30" bitsize="64"/>
> <reg name="mhpmcounter31" bitsize="64"/>
> + <reg name="mcountinhibit" bitsize="64"/>
> <reg name="mhpmevent3" bitsize="64"/>
> <reg name="mhpmevent4" bitsize="64"/>
> <reg name="mhpmevent5" bitsize="64"/>
> @@ -162,7 +163,8 @@
> <reg name="tdata3" bitsize="64"/>
> <reg name="dcsr" bitsize="64"/>
> <reg name="dpc" bitsize="64"/>
> - <reg name="dscratch" bitsize="64"/>
> + <reg name="dscratch0" bitsize="64"/>
> + <reg name="dscratch1" bitsize="64"/>
> <reg name="hstatus" bitsize="64"/>
> <reg name="hedeleg" bitsize="64"/>
> <reg name="hideleg" bitsize="64"/>
> @@ -179,7 +181,6 @@
> <reg name="mibound" bitsize="64"/>
> <reg name="mdbase" bitsize="64"/>
> <reg name="mdbound" bitsize="64"/>
> - <reg name="mucounteren" bitsize="64"/>
> <reg name="mscounteren" bitsize="64"/>
> <reg name="mhcounteren" bitsize="64"/>
> </feature>
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 18d0b15..fe00bb6 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -575,6 +575,7 @@
> #define MASK_CUSTOM3_RD_RS1 0x707f
> #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
> #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
> +/* Support CSR to priv spec 1.11. */
> #define CSR_USTATUS 0x0
> #define CSR_UIE 0x4
> #define CSR_UTVEC 0x5
> @@ -655,6 +656,7 @@
> #define CSR_SIDELEG 0x103
> #define CSR_SIE 0x104
> #define CSR_STVEC 0x105
> +/* scounteren is present int priv spec 1.10. */
> #define CSR_SCOUNTEREN 0x106
> #define CSR_SSCRATCH 0x140
> #define CSR_SEPC 0x141
> @@ -667,17 +669,20 @@
> #define CSR_MIMPID 0xf13
> #define CSR_MHARTID 0xf14
> #define CSR_MSTATUS 0x300
> +/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MISA 0x301
> #define CSR_MEDELEG 0x302
> #define CSR_MIDELEG 0x303
> #define CSR_MIE 0x304
> #define CSR_MTVEC 0x305
> +/* mcounteren is present in priv spec 1.10. */
> #define CSR_MCOUNTEREN 0x306
> #define CSR_MSCRATCH 0x340
> #define CSR_MEPC 0x341
> #define CSR_MCAUSE 0x342
> #define CSR_MTVAL 0x343
> #define CSR_MIP 0x344
> +/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
> #define CSR_PMPCFG0 0x3a0
> #define CSR_PMPCFG1 0x3a1
> #define CSR_PMPCFG2 0x3a2
> @@ -760,6 +765,8 @@
> #define CSR_MHPMCOUNTER29H 0xb9d
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
> +/* mcountinhibit is present in priv spec 1.11. */
> +#define CSR_MCOUNTINHIBIT 0x320
> #define CSR_MHPMEVENT3 0x323
> #define CSR_MHPMEVENT4 0x324
> #define CSR_MHPMEVENT5 0x325
> @@ -795,8 +802,10 @@
> #define CSR_TDATA3 0x7a3
> #define CSR_DCSR 0x7b0
> #define CSR_DPC 0x7b1
> -#define CSR_DSCRATCH 0x7b2
> -/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> +/* dscratch0 and dscratch1 are present in priv spec 1.11. */
> +#define CSR_DSCRATCH0 0x7b2
> +#define CSR_DSCRATCH1 0x7b3
> +/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
> #define CSR_HSTATUS 0x200
> #define CSR_HEDELEG 0x202
> #define CSR_HIDELEG 0x203
> @@ -807,16 +816,15 @@
> #define CSR_HCAUSE 0x242
> #define CSR_HBADADDR 0x243
> #define CSR_HIP 0x244
> -/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> #define CSR_MBASE 0x380
> #define CSR_MBOUND 0x381
> #define CSR_MIBASE 0x382
> #define CSR_MIBOUND 0x383
> #define CSR_MDBASE 0x384
> #define CSR_MDBOUND 0x385
> -#define CSR_MUCOUNTEREN 0x320
> #define CSR_MSCOUNTEREN 0x321
> #define CSR_MHCOUNTEREN 0x322
> +
> #define CAUSE_MISALIGNED_FETCH 0x0
> #define CAUSE_FAULT_FETCH 0x1
> #define CAUSE_ILLEGAL_INSTRUCTION 0x2
> @@ -1301,6 +1309,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
> DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
> +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
> DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
> @@ -1336,7 +1345,8 @@ DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
> DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
> DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
> DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
> -DECLARE_CSR(dscratch, CSR_DSCRATCH, CSR_CLASS_I)
> +DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
> +DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
> /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
> DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
> @@ -1354,7 +1364,6 @@ DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
> DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
> DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
> DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
> -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN, CSR_CLASS_I)
> DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
> DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
> #endif
> @@ -1367,6 +1376,10 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
> DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
> /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
> +/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
> +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> +/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
> +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
> #endif
> #ifdef DECLARE_CAUSE
> DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH] RISC-V: Update CSR to privileged spec 1.11.
2020-03-24 8:51 ` Andrew Burgess
@ 2020-03-24 9:11 ` Nelson Chu
0 siblings, 0 replies; 34+ messages in thread
From: Nelson Chu @ 2020-03-24 9:11 UTC (permalink / raw)
To: Andrew Burgess; +Cc: gdb-patches, Jim Wilson
Thank you very much Andrew :)
Nelson
On Tue, Mar 24, 2020 at 4:51 PM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
>
> * Nelson Chu <nelson.chu@sifive.com> [2020-03-12 03:00:57 -0700]:
>
> > gas/
> > * testsuite/gas/riscv/alias-csr.d: Move this to priv-reg-pseudo.
> > * testsuite/gas/riscv/alias-csr.s: Likewise.
> > * testsuite/gas/riscv/no-aliases-csr.d: Move this
> > to priv-reg-pseudo-noalias.
> > * testsuite/gas/riscv/bad-csr.d: Rename to priv-reg-fail-nonexistent.
> > * testsuite/gas/riscv/bad-csr.l: Likewise.
> > * testsuite/gas/riscv/bad-csr.s: Likewise.
> > * testsuite/gas/riscv/satp.d: Removed. Already included in priv-reg.
> > * testsuite/gas/riscv/satp.s: Likewise.
> > * testsuite/gas/riscv/priv-reg-pseudo.d: New testcase for all pseudo
> > csr instruction, including alias-csr testcase.
> > * testsuite/gas/riscv/priv-reg-pseudo.s: Likewise.
> > * testsuite/gas/riscv/priv-reg-pseudo-noalias.d: New testcase for all
> > pseudo instruction with objdump -Mno-aliases.
> > * testsuite/gas/riscv/priv-reg-fail-nonexistent.d: New testcase.
> > * testsuite/gas/riscv/priv-reg-fail-nonexistent.l: Likewise.
> > * testsuite/gas/riscv/priv-reg-fail-nonexistent.s: Likewise.
> > * testsuite/gas/riscv/priv-reg.d: Update CSR to 1.11.
> > * testsuite/gas/riscv/priv-reg.s: Likewise.
> > * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise.
> > * testsuite/gas/riscv/csr-dw-regnums.d: Likewise.
> > * testsuite/gas/riscv/csr-dw-regnums.s: Likewise.
> >
> > include/
> > * opcode/riscv-opc.h: Update CSR to 1.11.
> >
> > gdb/
> > * features/riscv/32bit-csr.xml: Regenerated.
> > * features/riscv/64bit-csr.xml: Regenerated.
>
> Sorry for missing this. The gdb/* parts are approved. I can't
> approve any of the other changes.
>
> Thanks,
> Andrew
>
>
>
> > ---
> > gas/testsuite/gas/riscv/alias-csr.d | 23 -
> > gas/testsuite/gas/riscv/alias-csr.s | 14 -
> > gas/testsuite/gas/riscv/bad-csr.d | 3 -
> > gas/testsuite/gas/riscv/bad-csr.l | 2 -
> > gas/testsuite/gas/riscv/bad-csr.s | 1 -
> > gas/testsuite/gas/riscv/csr-dw-regnums.d | 7 +-
> > gas/testsuite/gas/riscv/csr-dw-regnums.s | 9 +-
> > gas/testsuite/gas/riscv/no-aliases-csr.d | 23 -
> > .../gas/riscv/priv-reg-fail-nonexistent.d | 3 +
> > .../gas/riscv/priv-reg-fail-nonexistent.l | 2 +
> > .../gas/riscv/priv-reg-fail-nonexistent.s | 1 +
> > gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 4 +-
> > gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d | 36 ++
> > gas/testsuite/gas/riscv/priv-reg-pseudo.d | 36 ++
> > gas/testsuite/gas/riscv/priv-reg-pseudo.s | 33 ++
> > gas/testsuite/gas/riscv/priv-reg.d | 491 +++++++++++----------
> > gas/testsuite/gas/riscv/priv-reg.s | 114 ++---
> > gas/testsuite/gas/riscv/satp.d | 11 -
> > gas/testsuite/gas/riscv/satp.s | 3 -
> > gdb/features/riscv/32bit-csr.xml | 5 +-
> > gdb/features/riscv/64bit-csr.xml | 5 +-
> > include/opcode/riscv-opc.h | 25 +-
> > 22 files changed, 454 insertions(+), 397 deletions(-)
> > delete mode 100644 gas/testsuite/gas/riscv/alias-csr.d
> > delete mode 100644 gas/testsuite/gas/riscv/alias-csr.s
> > delete mode 100644 gas/testsuite/gas/riscv/bad-csr.d
> > delete mode 100644 gas/testsuite/gas/riscv/bad-csr.l
> > delete mode 100644 gas/testsuite/gas/riscv/bad-csr.s
> > delete mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
> > create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> > create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> > create mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> > create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> > create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.d
> > create mode 100644 gas/testsuite/gas/riscv/priv-reg-pseudo.s
> > delete mode 100644 gas/testsuite/gas/riscv/satp.d
> > delete mode 100644 gas/testsuite/gas/riscv/satp.s
> >
> > diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
> > deleted file mode 100644
> > index af5c591..0000000
> > --- a/gas/testsuite/gas/riscv/alias-csr.d
> > +++ /dev/null
> > @@ -1,23 +0,0 @@
> > -#source: alias-csr.s
> > -#as: -march=rv64if
> > -#objdump: -dr
> > -
> > -.*:[ ]+file format .*
> > -
> > -
> > -Disassembly of section .text:
> > -
> > -0+000 <alias_csr>:
> > -[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
> > -[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> > -[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
> > -[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
> > -[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> > -[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
> > -[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> > -[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> > -[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
> > -[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> > -[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
> > -[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> > -[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> > diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
> > deleted file mode 100644
> > index 8577de1..0000000
> > --- a/gas/testsuite/gas/riscv/alias-csr.s
> > +++ /dev/null
> > @@ -1,14 +0,0 @@
> > -alias_csr:
> > - frcsr t0
> > - fscsr t0, t2
> > - fscsr t2
> > - frrm t0
> > - fsrm t0, t1
> > - fsrm t1
> > - fsrmi t0, 31
> > - fsrmi 31
> > - frflags t0
> > - fsflags t0, t1
> > - fsflags t1
> > - fsflagsi t0, 31
> > - fsflagsi 31
> > diff --git a/gas/testsuite/gas/riscv/bad-csr.d b/gas/testsuite/gas/riscv/bad-csr.d
> > deleted file mode 100644
> > index 6863123..0000000
> > --- a/gas/testsuite/gas/riscv/bad-csr.d
> > +++ /dev/null
> > @@ -1,3 +0,0 @@
> > -#as:
> > -#source: bad-csr.s
> > -#error_output: bad-csr.l
> > diff --git a/gas/testsuite/gas/riscv/bad-csr.l b/gas/testsuite/gas/riscv/bad-csr.l
> > deleted file mode 100644
> > index a0bb8a6..0000000
> > --- a/gas/testsuite/gas/riscv/bad-csr.l
> > +++ /dev/null
> > @@ -1,2 +0,0 @@
> > -.*: Assembler messages:
> > -.*: Error: unknown CSR `nonexistent'
> > diff --git a/gas/testsuite/gas/riscv/bad-csr.s b/gas/testsuite/gas/riscv/bad-csr.s
> > deleted file mode 100644
> > index 6e6d27e..0000000
> > --- a/gas/testsuite/gas/riscv/bad-csr.s
> > +++ /dev/null
> > @@ -1 +0,0 @@
> > - csrr a0, nonexistent
> > diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> > index a7b415e..df9642f 100644
> > --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
> > +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
> > @@ -202,6 +202,7 @@ Contents of the .* section:
> > DW_CFA_offset_extended_sf: r7069 \(mhpmcounter29h\) at cfa\+11892
> > DW_CFA_offset_extended_sf: r7070 \(mhpmcounter30h\) at cfa\+11896
> > DW_CFA_offset_extended_sf: r7071 \(mhpmcounter31h\) at cfa\+11900
> > + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> > DW_CFA_offset_extended_sf: r4899 \(mhpmevent3\) at cfa\+3212
> > DW_CFA_offset_extended_sf: r4900 \(mhpmevent4\) at cfa\+3216
> > DW_CFA_offset_extended_sf: r4901 \(mhpmevent5\) at cfa\+3220
> > @@ -237,7 +238,8 @@ Contents of the .* section:
> > DW_CFA_offset_extended_sf: r6051 \(tdata3\) at cfa\+7820
> > DW_CFA_offset_extended_sf: r6064 \(dcsr\) at cfa\+7872
> > DW_CFA_offset_extended_sf: r6065 \(dpc\) at cfa\+7876
> > - DW_CFA_offset_extended_sf: r6066 \(dscratch\) at cfa\+7880
> > + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> > + DW_CFA_offset_extended_sf: r6067 \(dscratch1\) at cfa\+7884
> > DW_CFA_offset_extended_sf: r4608 \(hstatus\) at cfa\+2048
> > DW_CFA_offset_extended_sf: r4610 \(hedeleg\) at cfa\+2056
> > DW_CFA_offset_extended_sf: r4611 \(hideleg\) at cfa\+2060
> > @@ -254,12 +256,13 @@ Contents of the .* section:
> > DW_CFA_offset_extended_sf: r4995 \(mibound\) at cfa\+3596
> > DW_CFA_offset_extended_sf: r4996 \(mdbase\) at cfa\+3600
> > DW_CFA_offset_extended_sf: r4997 \(mdbound\) at cfa\+3604
> > - DW_CFA_offset_extended_sf: r4896 \(mucounteren\) at cfa\+3200
> > DW_CFA_offset_extended_sf: r4897 \(mscounteren\) at cfa\+3204
> > DW_CFA_offset_extended_sf: r4898 \(mhcounteren\) at cfa\+3208
> > DW_CFA_offset_extended_sf: r4163 \(utval\) at cfa\+268
> > DW_CFA_offset_extended_sf: r4419 \(stval\) at cfa\+1292
> > DW_CFA_offset_extended_sf: r4480 \(satp\) at cfa\+1536
> > DW_CFA_offset_extended_sf: r4931 \(mtval\) at cfa\+3340
> > + DW_CFA_offset_extended_sf: r4896 \(mcountinhibit\) at cfa\+3200
> > + DW_CFA_offset_extended_sf: r6066 \(dscratch0\) at cfa\+7880
> > DW_CFA_nop
> > #...
> > diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> > index b29e9da..4101a41 100644
> > --- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
> > +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
> > @@ -192,6 +192,7 @@ _start:
> > .cfi_offset mhpmcounter29h, 11892
> > .cfi_offset mhpmcounter30h, 11896
> > .cfi_offset mhpmcounter31h, 11900
> > + .cfi_offset mcountinhibit, 3200
> > .cfi_offset mhpmevent3, 3212
> > .cfi_offset mhpmevent4, 3216
> > .cfi_offset mhpmevent5, 3220
> > @@ -227,7 +228,10 @@ _start:
> > .cfi_offset tdata3, 7820
> > .cfi_offset dcsr, 7872
> > .cfi_offset dpc, 7876
> > - .cfi_offset dscratch, 7880
> > + .cfi_offset dscratch0, 7880
> > + .cfi_offset dscratch1, 7884
> > +
> > + # dropped in the current 1.11 priv spec.
> > .cfi_offset hstatus, 2048
> > .cfi_offset hedeleg, 2056
> > .cfi_offset hideleg, 2060
> > @@ -244,12 +248,13 @@ _start:
> > .cfi_offset mibound, 3596
> > .cfi_offset mdbase, 3600
> > .cfi_offset mdbound, 3604
> > - .cfi_offset mucounteren, 3200
> > .cfi_offset mscounteren, 3204
> > .cfi_offset mhcounteren, 3208
> > .cfi_offset ubadaddr, 268
> > .cfi_offset sbadaddr, 1292
> > .cfi_offset sptbr, 1536
> > .cfi_offset mbadaddr, 3340
> > + .cfi_offset mucounteren, 3200
> > + .cfi_offset dscratch, 7880
> > nop
> > .cfi_endproc
> > diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
> > deleted file mode 100644
> > index 2275330..0000000
> > --- a/gas/testsuite/gas/riscv/no-aliases-csr.d
> > +++ /dev/null
> > @@ -1,23 +0,0 @@
> > -#source: alias-csr.s
> > -#as: -march=rv64if
> > -#objdump: -dr -Mno-aliases
> > -
> > -.*:[ ]+file format .*
> > -
> > -
> > -Disassembly of section .text:
> > -
> > -0+000 <alias_csr>:
> > -[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> > -[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> > -[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> > -[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> > -[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> > -[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> > -[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> > -[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> > -[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> > -[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> > -[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> > -[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> > -[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> > new file mode 100644
> > index 0000000..9bb3f82
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d
> > @@ -0,0 +1,3 @@
> > +#as:
> > +#source: priv-reg-fail-nonexistent.s
> > +#error_output: priv-reg-fail-nonexistent.l
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> > new file mode 100644
> > index 0000000..a0bb8a6
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.l
> > @@ -0,0 +1,2 @@
> > +.*: Assembler messages:
> > +.*: Error: unknown CSR `nonexistent'
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> > new file mode 100644
> > index 0000000..6e6d27e
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.s
> > @@ -0,0 +1 @@
> > + csrr a0, nonexistent
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> > index 9123672..fa5a1b4 100644
> > --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> > +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l
> > @@ -31,6 +31,8 @@
> > .*Warning: Invalid CSR `hpmcounter29h' for the current ISA
> > .*Warning: Invalid CSR `hpmcounter30h' for the current ISA
> > .*Warning: Invalid CSR `hpmcounter31h' for the current ISA
> > +.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> > +.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> > .*Warning: Invalid CSR `mcycleh' for the current ISA
> > .*Warning: Invalid CSR `minstreth' for the current ISA
> > .*Warning: Invalid CSR `mhpmcounter3h' for the current ISA
> > @@ -62,5 +64,3 @@
> > .*Warning: Invalid CSR `mhpmcounter29h' for the current ISA
> > .*Warning: Invalid CSR `mhpmcounter30h' for the current ISA
> > .*Warning: Invalid CSR `mhpmcounter31h' for the current ISA
> > -.*Warning: Invalid CSR `pmpcfg1' for the current ISA
> > -.*Warning: Invalid CSR `pmpcfg3' for the current ISA
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> > new file mode 100644
> > index 0000000..e0acb18
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo-noalias.d
> > @@ -0,0 +1,36 @@
> > +#source: priv-reg-pseudo.s
> > +#as: -march=rv32if
> > +#objdump: -dr -Mno-aliases
> > +
> > +.*:[ ]+file format .*
> > +
> > +
> > +Disassembly of section .text:
> > +
> > +0+000 <pseudo_csr_insn>:
> > +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrrs[ ]+t0,ustatus,zero
> > +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrrw[ ]+zero,ustatus,t0
> > +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrrs[ ]+zero,ustatus,t0
> > +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrrc[ ]+zero,ustatus,t0
> > +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrrwi[ ]+zero,ustatus,31
> > +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrrsi[ ]+zero,ustatus,31
> > +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrrci[ ]+zero,ustatus,31
> > +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+csrrs[ ]+t0,cycle,zero
> > +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+csrrs[ ]+t0,time,zero
> > +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+csrrs[ ]+t0,instret,zero
> > +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+csrrs[ ]+t0,cycleh,zero
> > +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+csrrs[ ]+t0,timeh,zero
> > +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+csrrs[ ]+t0,instreth,zero
> > +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
> > +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
> > +[ ]+[0-9a-f]+:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
> > +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
> > +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
> > +[ ]+[0-9a-f]+:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
> > +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
> > +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
> > +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
> > +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
> > +[ ]+[0-9a-f]+:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
> > +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
> > +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.d b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> > new file mode 100644
> > index 0000000..4243510
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.d
> > @@ -0,0 +1,36 @@
> > +#source: priv-reg-pseudo.s
> > +#as: -march=rv32if
> > +#objdump: -dr
> > +
> > +.*:[ ]+file format .*
> > +
> > +
> > +Disassembly of section .text:
> > +
> > +0+000 <pseudo_csr_insn>:
> > +[ ]+[0-9a-f]+:[ ]+000022f3[ ]+csrr[ ]+t0,ustatus
> > +[ ]+[0-9a-f]+:[ ]+00029073[ ]+csrw[ ]+ustatus,t0
> > +[ ]+[0-9a-f]+:[ ]+0002a073[ ]+csrs[ ]+ustatus,t0
> > +[ ]+[0-9a-f]+:[ ]+0002b073[ ]+csrc[ ]+ustatus,t0
> > +[ ]+[0-9a-f]+:[ ]+000fd073[ ]+csrwi[ ]+ustatus,31
> > +[ ]+[0-9a-f]+:[ ]+000fe073[ ]+csrsi[ ]+ustatus,31
> > +[ ]+[0-9a-f]+:[ ]+000ff073[ ]+csrci[ ]+ustatus,31
> > +[ ]+[0-9a-f]+:[ ]+c00022f3[ ]+rdcycle[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+c01022f3[ ]+rdtime[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+c02022f3[ ]+rdinstret[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+c80022f3[ ]+rdcycleh[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+c81022f3[ ]+rdtimeh[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+c82022f3[ ]+rdinstreth[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+003022f3[ ]+frcsr[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
> > +[ ]+[0-9a-f]+:[ ]+00339073[ ]+fscsr[ ]+t2
> > +[ ]+[0-9a-f]+:[ ]+002022f3[ ]+frrm[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
> > +[ ]+[0-9a-f]+:[ ]+00231073[ ]+fsrm[ ]+t1
> > +[ ]+[0-9a-f]+:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
> > +[ ]+[0-9a-f]+:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
> > +[ ]+[0-9a-f]+:[ ]+001022f3[ ]+frflags[ ]+t0
> > +[ ]+[0-9a-f]+:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
> > +[ ]+[0-9a-f]+:[ ]+00131073[ ]+fsflags[ ]+t1
> > +[ ]+[0-9a-f]+:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
> > +[ ]+[0-9a-f]+:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
> > diff --git a/gas/testsuite/gas/riscv/priv-reg-pseudo.s b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> > new file mode 100644
> > index 0000000..8efaa4e
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/priv-reg-pseudo.s
> > @@ -0,0 +1,33 @@
> > +pseudo_csr_insn:
> > + # i-ext
> > + csrr t0, 0x0
> > + csrw 0x0, t0
> > + csrs 0x0, t0
> > + csrc 0x0, t0
> > + csrwi 0x0, 31
> > + csrsi 0x0, 31
> > + csrci 0x0, 31
> > +
> > + rdcycle t0
> > + rdtime t0
> > + rdinstret t0
> > +
> > + # rv32i-ext
> > + rdcycleh t0
> > + rdtimeh t0
> > + rdinstreth t0
> > +
> > + # f-ext
> > + frcsr t0 # frsr
> > + fscsr t0, t2 # fssr
> > + fscsr t2 # fssr
> > + frrm t0
> > + fsrm t0, t1
> > + fsrm t1
> > + fsrmi t0, 31
> > + fsrmi 31
> > + frflags t0
> > + fsflags t0, t1
> > + fsflags t1
> > + fsflagsi t0, 31
> > + fsflagsi 31
> > diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
> > index 8b7a7bf..8fc41d2 100644
> > --- a/gas/testsuite/gas/riscv/priv-reg.d
> > +++ b/gas/testsuite/gas/riscv/priv-reg.d
> > @@ -7,247 +7,250 @@
> > Disassembly of section .text:
> >
> > 0+000 <.text>:
> > -[ ]+0:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> > -[ ]+4:[ ]+00402573[ ]+csrr[ ]+a0,uie
> > -[ ]+8:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> > -[ ]+c:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> > -[ ]+10:[ ]+04102573[ ]+csrr[ ]+a0,uepc
> > -[ ]+14:[ ]+04202573[ ]+csrr[ ]+a0,ucause
> > -[ ]+18:[ ]+04302573[ ]+csrr[ ]+a0,utval
> > -[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
> > -[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
> > -[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
> > -[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
> > -[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
> > -[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
> > -[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
> > -[ ]+38:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> > -[ ]+3c:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> > -[ ]+40:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> > -[ ]+44:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> > -[ ]+48:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> > -[ ]+4c:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> > -[ ]+50:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> > -[ ]+54:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> > -[ ]+58:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> > -[ ]+5c:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> > -[ ]+60:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> > -[ ]+64:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> > -[ ]+68:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> > -[ ]+6c:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> > -[ ]+70:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> > -[ ]+74:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> > -[ ]+78:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> > -[ ]+7c:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> > -[ ]+80:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> > -[ ]+84:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> > -[ ]+88:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> > -[ ]+8c:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> > -[ ]+90:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> > -[ ]+94:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> > -[ ]+98:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> > -[ ]+9c:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> > -[ ]+a0:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> > -[ ]+a4:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> > -[ ]+a8:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> > -[ ]+ac:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> > -[ ]+b0:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> > -[ ]+b4:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> > -[ ]+b8:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> > -[ ]+bc:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> > -[ ]+c0:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> > -[ ]+c4:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> > -[ ]+c8:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> > -[ ]+cc:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> > -[ ]+d0:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> > -[ ]+d4:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> > -[ ]+d8:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
> > -[ ]+dc:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
> > -[ ]+e0:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
> > -[ ]+e4:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
> > -[ ]+e8:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
> > -[ ]+ec:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
> > -[ ]+f0:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
> > -[ ]+f4:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> > -[ ]+f8:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> > -[ ]+fc:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> > -[ ]+100:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> > -[ ]+104:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> > -[ ]+108:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> > -[ ]+10c:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> > -[ ]+110:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> > -[ ]+114:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> > -[ ]+118:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> > -[ ]+11c:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> > -[ ]+120:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> > -[ ]+124:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> > -[ ]+128:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> > -[ ]+12c:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> > -[ ]+130:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> > -[ ]+134:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> > -[ ]+138:[ ]+10402573[ ]+csrr[ ]+a0,sie
> > -[ ]+13c:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> > -[ ]+140:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> > -[ ]+144:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> > -[ ]+148:[ ]+14202573[ ]+csrr[ ]+a0,scause
> > -[ ]+14c:[ ]+14302573[ ]+csrr[ ]+a0,stval
> > -[ ]+150:[ ]+14402573[ ]+csrr[ ]+a0,sip
> > -[ ]+154:[ ]+18002573[ ]+csrr[ ]+a0,satp
> > -[ ]+158:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> > -[ ]+15c:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> > -[ ]+160:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> > -[ ]+164:[ ]+20402573[ ]+csrr[ ]+a0,hie
> > -[ ]+168:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> > -[ ]+16c:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> > -[ ]+170:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> > -[ ]+174:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> > -[ ]+178:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> > -[ ]+17c:[ ]+24402573[ ]+csrr[ ]+a0,hip
> > -[ ]+180:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
> > -[ ]+184:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
> > -[ ]+188:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
> > -[ ]+18c:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
> > -[ ]+190:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
> > -[ ]+194:[ ]+30102573[ ]+csrr[ ]+a0,misa
> > -[ ]+198:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> > -[ ]+19c:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> > -[ ]+1a0:[ ]+30402573[ ]+csrr[ ]+a0,mie
> > -[ ]+1a4:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> > -[ ]+1a8:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> > -[ ]+1ac:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> > -[ ]+1b0:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> > -[ ]+1b4:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> > -[ ]+1b8:[ ]+34402573[ ]+csrr[ ]+a0,mip
> > -[ ]+1bc:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> > -[ ]+1c0:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> > -[ ]+1c4:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> > -[ ]+1c8:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> > -[ ]+1cc:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> > -[ ]+1d0:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> > -[ ]+1d4:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> > -[ ]+1d8:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> > -[ ]+1dc:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> > -[ ]+1e0:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> > -[ ]+1e4:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> > -[ ]+1e8:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> > -[ ]+1ec:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> > -[ ]+1f0:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> > -[ ]+1f4:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> > -[ ]+1f8:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> > -[ ]+1fc:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> > -[ ]+200:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> > -[ ]+204:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> > -[ ]+208:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> > -[ ]+20c:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> > -[ ]+210:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> > -[ ]+214:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> > -[ ]+218:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> > -[ ]+21c:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> > -[ ]+220:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> > -[ ]+224:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> > -[ ]+228:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> > -[ ]+22c:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> > -[ ]+230:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> > -[ ]+234:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> > -[ ]+238:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> > -[ ]+23c:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> > -[ ]+240:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> > -[ ]+244:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> > -[ ]+248:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> > -[ ]+24c:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> > -[ ]+250:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> > -[ ]+254:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> > -[ ]+258:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> > -[ ]+25c:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> > -[ ]+260:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> > -[ ]+264:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> > -[ ]+268:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> > -[ ]+26c:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> > -[ ]+270:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> > -[ ]+274:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> > -[ ]+278:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> > -[ ]+27c:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> > -[ ]+280:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> > -[ ]+284:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> > -[ ]+288:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> > -[ ]+28c:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> > -[ ]+290:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> > -[ ]+294:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> > -[ ]+298:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> > -[ ]+29c:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> > -[ ]+2a0:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> > -[ ]+2a4:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> > -[ ]+2a8:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> > -[ ]+2ac:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> > -[ ]+2b0:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> > -[ ]+2b4:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> > -[ ]+2b8:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> > -[ ]+2bc:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> > -[ ]+2c0:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> > -[ ]+2c4:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> > -[ ]+2c8:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> > -[ ]+2cc:[ ]+32002573[ ]+csrr[ ]+a0,mucounteren
> > -[ ]+2d0:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> > -[ ]+2d4:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> > -[ ]+2d8:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> > -[ ]+2dc:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> > -[ ]+2e0:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> > -[ ]+2e4:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> > -[ ]+2e8:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> > -[ ]+2ec:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> > -[ ]+2f0:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> > -[ ]+2f4:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> > -[ ]+2f8:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> > -[ ]+2fc:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> > -[ ]+300:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> > -[ ]+304:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> > -[ ]+308:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> > -[ ]+30c:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> > -[ ]+310:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> > -[ ]+314:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> > -[ ]+318:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> > -[ ]+31c:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> > -[ ]+320:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> > -[ ]+324:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> > -[ ]+328:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> > -[ ]+32c:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> > -[ ]+330:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> > -[ ]+334:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> > -[ ]+338:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> > -[ ]+33c:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> > -[ ]+340:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> > -[ ]+344:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> > -[ ]+348:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> > -[ ]+34c:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> > -[ ]+350:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> > -[ ]+354:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> > -[ ]+358:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> > -[ ]+35c:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> > -[ ]+360:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> > -[ ]+364:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch
> > -[ ]+368:[ ]+04302573[ ]+csrr[ ]+a0,utval
> > -[ ]+36c:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
> > -[ ]+370:[ ]+14302573[ ]+csrr[ ]+a0,stval
> > -[ ]+374:[ ]+18002573[ ]+csrr[ ]+a0,satp
> > -[ ]+378:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> > -[ ]+37c:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> > -[ ]+380:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> > -[ ]+384:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> > -[ ]+388:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> > -[ ]+38c:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> > -[ ]+390:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> > -[ ]+394:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> > -[ ]+398:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> > -[ ]+39c:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> > -[ ]+3a0:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> > -[ ]+3a4:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> > -[ ]+3a8:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> > -[ ]+3ac:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> > -[ ]+3b0:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> > -[ ]+3b4:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> > -[ ]+3b8:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> > -[ ]+3bc:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> > -[ ]+3c0:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> > -[ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> > -[ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> > -[ ]+3cc:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> > +[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
> > +[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
> > +[ ]+[0-9a-f]+:[ ]+00502573[ ]+csrr[ ]+a0,utvec
> > +[ ]+[0-9a-f]+:[ ]+04002573[ ]+csrr[ ]+a0,uscratch
> > +[ ]+[0-9a-f]+:[ ]+04102573[ ]+csrr[ ]+a0,uepc
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> > +[ ]+[0-9a-f]+:[ ]+04402573[ ]+csrr[ ]+a0,uip
> > +[ ]+[0-9a-f]+:[ ]+00102573[ ]+frflags[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+00202573[ ]+frrm[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+00302573[ ]+frcsr[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c0002573[ ]+rdcycle[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c0102573[ ]+rdtime[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c0202573[ ]+rdinstret[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c0302573[ ]+csrr[ ]+a0,hpmcounter3
> > +[ ]+[0-9a-f]+:[ ]+c0402573[ ]+csrr[ ]+a0,hpmcounter4
> > +[ ]+[0-9a-f]+:[ ]+c0502573[ ]+csrr[ ]+a0,hpmcounter5
> > +[ ]+[0-9a-f]+:[ ]+c0602573[ ]+csrr[ ]+a0,hpmcounter6
> > +[ ]+[0-9a-f]+:[ ]+c0702573[ ]+csrr[ ]+a0,hpmcounter7
> > +[ ]+[0-9a-f]+:[ ]+c0802573[ ]+csrr[ ]+a0,hpmcounter8
> > +[ ]+[0-9a-f]+:[ ]+c0902573[ ]+csrr[ ]+a0,hpmcounter9
> > +[ ]+[0-9a-f]+:[ ]+c0a02573[ ]+csrr[ ]+a0,hpmcounter10
> > +[ ]+[0-9a-f]+:[ ]+c0b02573[ ]+csrr[ ]+a0,hpmcounter11
> > +[ ]+[0-9a-f]+:[ ]+c0c02573[ ]+csrr[ ]+a0,hpmcounter12
> > +[ ]+[0-9a-f]+:[ ]+c0d02573[ ]+csrr[ ]+a0,hpmcounter13
> > +[ ]+[0-9a-f]+:[ ]+c0e02573[ ]+csrr[ ]+a0,hpmcounter14
> > +[ ]+[0-9a-f]+:[ ]+c0f02573[ ]+csrr[ ]+a0,hpmcounter15
> > +[ ]+[0-9a-f]+:[ ]+c1002573[ ]+csrr[ ]+a0,hpmcounter16
> > +[ ]+[0-9a-f]+:[ ]+c1102573[ ]+csrr[ ]+a0,hpmcounter17
> > +[ ]+[0-9a-f]+:[ ]+c1202573[ ]+csrr[ ]+a0,hpmcounter18
> > +[ ]+[0-9a-f]+:[ ]+c1302573[ ]+csrr[ ]+a0,hpmcounter19
> > +[ ]+[0-9a-f]+:[ ]+c1402573[ ]+csrr[ ]+a0,hpmcounter20
> > +[ ]+[0-9a-f]+:[ ]+c1502573[ ]+csrr[ ]+a0,hpmcounter21
> > +[ ]+[0-9a-f]+:[ ]+c1602573[ ]+csrr[ ]+a0,hpmcounter22
> > +[ ]+[0-9a-f]+:[ ]+c1702573[ ]+csrr[ ]+a0,hpmcounter23
> > +[ ]+[0-9a-f]+:[ ]+c1802573[ ]+csrr[ ]+a0,hpmcounter24
> > +[ ]+[0-9a-f]+:[ ]+c1902573[ ]+csrr[ ]+a0,hpmcounter25
> > +[ ]+[0-9a-f]+:[ ]+c1a02573[ ]+csrr[ ]+a0,hpmcounter26
> > +[ ]+[0-9a-f]+:[ ]+c1b02573[ ]+csrr[ ]+a0,hpmcounter27
> > +[ ]+[0-9a-f]+:[ ]+c1c02573[ ]+csrr[ ]+a0,hpmcounter28
> > +[ ]+[0-9a-f]+:[ ]+c1d02573[ ]+csrr[ ]+a0,hpmcounter29
> > +[ ]+[0-9a-f]+:[ ]+c1e02573[ ]+csrr[ ]+a0,hpmcounter30
> > +[ ]+[0-9a-f]+:[ ]+c1f02573[ ]+csrr[ ]+a0,hpmcounter31
> > +[ ]+[0-9a-f]+:[ ]+c8002573[ ]+rdcycleh[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c8102573[ ]+rdtimeh[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c8202573[ ]+rdinstreth[ ]+a0
> > +[ ]+[0-9a-f]+:[ ]+c8302573[ ]+csrr[ ]+a0,hpmcounter3h
> > +[ ]+[0-9a-f]+:[ ]+c8402573[ ]+csrr[ ]+a0,hpmcounter4h
> > +[ ]+[0-9a-f]+:[ ]+c8502573[ ]+csrr[ ]+a0,hpmcounter5h
> > +[ ]+[0-9a-f]+:[ ]+c8602573[ ]+csrr[ ]+a0,hpmcounter6h
> > +[ ]+[0-9a-f]+:[ ]+c8702573[ ]+csrr[ ]+a0,hpmcounter7h
> > +[ ]+[0-9a-f]+:[ ]+c8802573[ ]+csrr[ ]+a0,hpmcounter8h
> > +[ ]+[0-9a-f]+:[ ]+c8902573[ ]+csrr[ ]+a0,hpmcounter9h
> > +[ ]+[0-9a-f]+:[ ]+c8a02573[ ]+csrr[ ]+a0,hpmcounter10h
> > +[ ]+[0-9a-f]+:[ ]+c8b02573[ ]+csrr[ ]+a0,hpmcounter11h
> > +[ ]+[0-9a-f]+:[ ]+c8c02573[ ]+csrr[ ]+a0,hpmcounter12h
> > +[ ]+[0-9a-f]+:[ ]+c8d02573[ ]+csrr[ ]+a0,hpmcounter13h
> > +[ ]+[0-9a-f]+:[ ]+c8e02573[ ]+csrr[ ]+a0,hpmcounter14h
> > +[ ]+[0-9a-f]+:[ ]+c8f02573[ ]+csrr[ ]+a0,hpmcounter15h
> > +[ ]+[0-9a-f]+:[ ]+c9002573[ ]+csrr[ ]+a0,hpmcounter16h
> > +[ ]+[0-9a-f]+:[ ]+c9102573[ ]+csrr[ ]+a0,hpmcounter17h
> > +[ ]+[0-9a-f]+:[ ]+c9202573[ ]+csrr[ ]+a0,hpmcounter18h
> > +[ ]+[0-9a-f]+:[ ]+c9302573[ ]+csrr[ ]+a0,hpmcounter19h
> > +[ ]+[0-9a-f]+:[ ]+c9402573[ ]+csrr[ ]+a0,hpmcounter20h
> > +[ ]+[0-9a-f]+:[ ]+c9502573[ ]+csrr[ ]+a0,hpmcounter21h
> > +[ ]+[0-9a-f]+:[ ]+c9602573[ ]+csrr[ ]+a0,hpmcounter22h
> > +[ ]+[0-9a-f]+:[ ]+c9702573[ ]+csrr[ ]+a0,hpmcounter23h
> > +[ ]+[0-9a-f]+:[ ]+c9802573[ ]+csrr[ ]+a0,hpmcounter24h
> > +[ ]+[0-9a-f]+:[ ]+c9902573[ ]+csrr[ ]+a0,hpmcounter25h
> > +[ ]+[0-9a-f]+:[ ]+c9a02573[ ]+csrr[ ]+a0,hpmcounter26h
> > +[ ]+[0-9a-f]+:[ ]+c9b02573[ ]+csrr[ ]+a0,hpmcounter27h
> > +[ ]+[0-9a-f]+:[ ]+c9c02573[ ]+csrr[ ]+a0,hpmcounter28h
> > +[ ]+[0-9a-f]+:[ ]+c9d02573[ ]+csrr[ ]+a0,hpmcounter29h
> > +[ ]+[0-9a-f]+:[ ]+c9e02573[ ]+csrr[ ]+a0,hpmcounter30h
> > +[ ]+[0-9a-f]+:[ ]+c9f02573[ ]+csrr[ ]+a0,hpmcounter31h
> > +[ ]+[0-9a-f]+:[ ]+10002573[ ]+csrr[ ]+a0,sstatus
> > +[ ]+[0-9a-f]+:[ ]+10202573[ ]+csrr[ ]+a0,sedeleg
> > +[ ]+[0-9a-f]+:[ ]+10302573[ ]+csrr[ ]+a0,sideleg
> > +[ ]+[0-9a-f]+:[ ]+10402573[ ]+csrr[ ]+a0,sie
> > +[ ]+[0-9a-f]+:[ ]+10502573[ ]+csrr[ ]+a0,stvec
> > +[ ]+[0-9a-f]+:[ ]+10602573[ ]+csrr[ ]+a0,scounteren
> > +[ ]+[0-9a-f]+:[ ]+14002573[ ]+csrr[ ]+a0,sscratch
> > +[ ]+[0-9a-f]+:[ ]+14102573[ ]+csrr[ ]+a0,sepc
> > +[ ]+[0-9a-f]+:[ ]+14202573[ ]+csrr[ ]+a0,scause
> > +[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> > +[ ]+[0-9a-f]+:[ ]+14402573[ ]+csrr[ ]+a0,sip
> > +[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> > +[ ]+[0-9a-f]+:[ ]+f1102573[ ]+csrr[ ]+a0,mvendorid
> > +[ ]+[0-9a-f]+:[ ]+f1202573[ ]+csrr[ ]+a0,marchid
> > +[ ]+[0-9a-f]+:[ ]+f1302573[ ]+csrr[ ]+a0,mimpid
> > +[ ]+[0-9a-f]+:[ ]+f1402573[ ]+csrr[ ]+a0,mhartid
> > +[ ]+[0-9a-f]+:[ ]+30002573[ ]+csrr[ ]+a0,mstatus
> > +[ ]+[0-9a-f]+:[ ]+30102573[ ]+csrr[ ]+a0,misa
> > +[ ]+[0-9a-f]+:[ ]+30202573[ ]+csrr[ ]+a0,medeleg
> > +[ ]+[0-9a-f]+:[ ]+30302573[ ]+csrr[ ]+a0,mideleg
> > +[ ]+[0-9a-f]+:[ ]+30402573[ ]+csrr[ ]+a0,mie
> > +[ ]+[0-9a-f]+:[ ]+30502573[ ]+csrr[ ]+a0,mtvec
> > +[ ]+[0-9a-f]+:[ ]+30602573[ ]+csrr[ ]+a0,mcounteren
> > +[ ]+[0-9a-f]+:[ ]+34002573[ ]+csrr[ ]+a0,mscratch
> > +[ ]+[0-9a-f]+:[ ]+34102573[ ]+csrr[ ]+a0,mepc
> > +[ ]+[0-9a-f]+:[ ]+34202573[ ]+csrr[ ]+a0,mcause
> > +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> > +[ ]+[0-9a-f]+:[ ]+34402573[ ]+csrr[ ]+a0,mip
> > +[ ]+[0-9a-f]+:[ ]+3a002573[ ]+csrr[ ]+a0,pmpcfg0
> > +[ ]+[0-9a-f]+:[ ]+3a102573[ ]+csrr[ ]+a0,pmpcfg1
> > +[ ]+[0-9a-f]+:[ ]+3a202573[ ]+csrr[ ]+a0,pmpcfg2
> > +[ ]+[0-9a-f]+:[ ]+3a302573[ ]+csrr[ ]+a0,pmpcfg3
> > +[ ]+[0-9a-f]+:[ ]+3b002573[ ]+csrr[ ]+a0,pmpaddr0
> > +[ ]+[0-9a-f]+:[ ]+3b102573[ ]+csrr[ ]+a0,pmpaddr1
> > +[ ]+[0-9a-f]+:[ ]+3b202573[ ]+csrr[ ]+a0,pmpaddr2
> > +[ ]+[0-9a-f]+:[ ]+3b302573[ ]+csrr[ ]+a0,pmpaddr3
> > +[ ]+[0-9a-f]+:[ ]+3b402573[ ]+csrr[ ]+a0,pmpaddr4
> > +[ ]+[0-9a-f]+:[ ]+3b502573[ ]+csrr[ ]+a0,pmpaddr5
> > +[ ]+[0-9a-f]+:[ ]+3b602573[ ]+csrr[ ]+a0,pmpaddr6
> > +[ ]+[0-9a-f]+:[ ]+3b702573[ ]+csrr[ ]+a0,pmpaddr7
> > +[ ]+[0-9a-f]+:[ ]+3b802573[ ]+csrr[ ]+a0,pmpaddr8
> > +[ ]+[0-9a-f]+:[ ]+3b902573[ ]+csrr[ ]+a0,pmpaddr9
> > +[ ]+[0-9a-f]+:[ ]+3ba02573[ ]+csrr[ ]+a0,pmpaddr10
> > +[ ]+[0-9a-f]+:[ ]+3bb02573[ ]+csrr[ ]+a0,pmpaddr11
> > +[ ]+[0-9a-f]+:[ ]+3bc02573[ ]+csrr[ ]+a0,pmpaddr12
> > +[ ]+[0-9a-f]+:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
> > +[ ]+[0-9a-f]+:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
> > +[ ]+[0-9a-f]+:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
> > +[ ]+[0-9a-f]+:[ ]+b0002573[ ]+csrr[ ]+a0,mcycle
> > +[ ]+[0-9a-f]+:[ ]+b0202573[ ]+csrr[ ]+a0,minstret
> > +[ ]+[0-9a-f]+:[ ]+b0302573[ ]+csrr[ ]+a0,mhpmcounter3
> > +[ ]+[0-9a-f]+:[ ]+b0402573[ ]+csrr[ ]+a0,mhpmcounter4
> > +[ ]+[0-9a-f]+:[ ]+b0502573[ ]+csrr[ ]+a0,mhpmcounter5
> > +[ ]+[0-9a-f]+:[ ]+b0602573[ ]+csrr[ ]+a0,mhpmcounter6
> > +[ ]+[0-9a-f]+:[ ]+b0702573[ ]+csrr[ ]+a0,mhpmcounter7
> > +[ ]+[0-9a-f]+:[ ]+b0802573[ ]+csrr[ ]+a0,mhpmcounter8
> > +[ ]+[0-9a-f]+:[ ]+b0902573[ ]+csrr[ ]+a0,mhpmcounter9
> > +[ ]+[0-9a-f]+:[ ]+b0a02573[ ]+csrr[ ]+a0,mhpmcounter10
> > +[ ]+[0-9a-f]+:[ ]+b0b02573[ ]+csrr[ ]+a0,mhpmcounter11
> > +[ ]+[0-9a-f]+:[ ]+b0c02573[ ]+csrr[ ]+a0,mhpmcounter12
> > +[ ]+[0-9a-f]+:[ ]+b0d02573[ ]+csrr[ ]+a0,mhpmcounter13
> > +[ ]+[0-9a-f]+:[ ]+b0e02573[ ]+csrr[ ]+a0,mhpmcounter14
> > +[ ]+[0-9a-f]+:[ ]+b0f02573[ ]+csrr[ ]+a0,mhpmcounter15
> > +[ ]+[0-9a-f]+:[ ]+b1002573[ ]+csrr[ ]+a0,mhpmcounter16
> > +[ ]+[0-9a-f]+:[ ]+b1102573[ ]+csrr[ ]+a0,mhpmcounter17
> > +[ ]+[0-9a-f]+:[ ]+b1202573[ ]+csrr[ ]+a0,mhpmcounter18
> > +[ ]+[0-9a-f]+:[ ]+b1302573[ ]+csrr[ ]+a0,mhpmcounter19
> > +[ ]+[0-9a-f]+:[ ]+b1402573[ ]+csrr[ ]+a0,mhpmcounter20
> > +[ ]+[0-9a-f]+:[ ]+b1502573[ ]+csrr[ ]+a0,mhpmcounter21
> > +[ ]+[0-9a-f]+:[ ]+b1602573[ ]+csrr[ ]+a0,mhpmcounter22
> > +[ ]+[0-9a-f]+:[ ]+b1702573[ ]+csrr[ ]+a0,mhpmcounter23
> > +[ ]+[0-9a-f]+:[ ]+b1802573[ ]+csrr[ ]+a0,mhpmcounter24
> > +[ ]+[0-9a-f]+:[ ]+b1902573[ ]+csrr[ ]+a0,mhpmcounter25
> > +[ ]+[0-9a-f]+:[ ]+b1a02573[ ]+csrr[ ]+a0,mhpmcounter26
> > +[ ]+[0-9a-f]+:[ ]+b1b02573[ ]+csrr[ ]+a0,mhpmcounter27
> > +[ ]+[0-9a-f]+:[ ]+b1c02573[ ]+csrr[ ]+a0,mhpmcounter28
> > +[ ]+[0-9a-f]+:[ ]+b1d02573[ ]+csrr[ ]+a0,mhpmcounter29
> > +[ ]+[0-9a-f]+:[ ]+b1e02573[ ]+csrr[ ]+a0,mhpmcounter30
> > +[ ]+[0-9a-f]+:[ ]+b1f02573[ ]+csrr[ ]+a0,mhpmcounter31
> > +[ ]+[0-9a-f]+:[ ]+b8002573[ ]+csrr[ ]+a0,mcycleh
> > +[ ]+[0-9a-f]+:[ ]+b8202573[ ]+csrr[ ]+a0,minstreth
> > +[ ]+[0-9a-f]+:[ ]+b8302573[ ]+csrr[ ]+a0,mhpmcounter3h
> > +[ ]+[0-9a-f]+:[ ]+b8402573[ ]+csrr[ ]+a0,mhpmcounter4h
> > +[ ]+[0-9a-f]+:[ ]+b8502573[ ]+csrr[ ]+a0,mhpmcounter5h
> > +[ ]+[0-9a-f]+:[ ]+b8602573[ ]+csrr[ ]+a0,mhpmcounter6h
> > +[ ]+[0-9a-f]+:[ ]+b8702573[ ]+csrr[ ]+a0,mhpmcounter7h
> > +[ ]+[0-9a-f]+:[ ]+b8802573[ ]+csrr[ ]+a0,mhpmcounter8h
> > +[ ]+[0-9a-f]+:[ ]+b8902573[ ]+csrr[ ]+a0,mhpmcounter9h
> > +[ ]+[0-9a-f]+:[ ]+b8a02573[ ]+csrr[ ]+a0,mhpmcounter10h
> > +[ ]+[0-9a-f]+:[ ]+b8b02573[ ]+csrr[ ]+a0,mhpmcounter11h
> > +[ ]+[0-9a-f]+:[ ]+b8c02573[ ]+csrr[ ]+a0,mhpmcounter12h
> > +[ ]+[0-9a-f]+:[ ]+b8d02573[ ]+csrr[ ]+a0,mhpmcounter13h
> > +[ ]+[0-9a-f]+:[ ]+b8e02573[ ]+csrr[ ]+a0,mhpmcounter14h
> > +[ ]+[0-9a-f]+:[ ]+b8f02573[ ]+csrr[ ]+a0,mhpmcounter15h
> > +[ ]+[0-9a-f]+:[ ]+b9002573[ ]+csrr[ ]+a0,mhpmcounter16h
> > +[ ]+[0-9a-f]+:[ ]+b9102573[ ]+csrr[ ]+a0,mhpmcounter17h
> > +[ ]+[0-9a-f]+:[ ]+b9202573[ ]+csrr[ ]+a0,mhpmcounter18h
> > +[ ]+[0-9a-f]+:[ ]+b9302573[ ]+csrr[ ]+a0,mhpmcounter19h
> > +[ ]+[0-9a-f]+:[ ]+b9402573[ ]+csrr[ ]+a0,mhpmcounter20h
> > +[ ]+[0-9a-f]+:[ ]+b9502573[ ]+csrr[ ]+a0,mhpmcounter21h
> > +[ ]+[0-9a-f]+:[ ]+b9602573[ ]+csrr[ ]+a0,mhpmcounter22h
> > +[ ]+[0-9a-f]+:[ ]+b9702573[ ]+csrr[ ]+a0,mhpmcounter23h
> > +[ ]+[0-9a-f]+:[ ]+b9802573[ ]+csrr[ ]+a0,mhpmcounter24h
> > +[ ]+[0-9a-f]+:[ ]+b9902573[ ]+csrr[ ]+a0,mhpmcounter25h
> > +[ ]+[0-9a-f]+:[ ]+b9a02573[ ]+csrr[ ]+a0,mhpmcounter26h
> > +[ ]+[0-9a-f]+:[ ]+b9b02573[ ]+csrr[ ]+a0,mhpmcounter27h
> > +[ ]+[0-9a-f]+:[ ]+b9c02573[ ]+csrr[ ]+a0,mhpmcounter28h
> > +[ ]+[0-9a-f]+:[ ]+b9d02573[ ]+csrr[ ]+a0,mhpmcounter29h
> > +[ ]+[0-9a-f]+:[ ]+b9e02573[ ]+csrr[ ]+a0,mhpmcounter30h
> > +[ ]+[0-9a-f]+:[ ]+b9f02573[ ]+csrr[ ]+a0,mhpmcounter31h
> > +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> > +[ ]+[0-9a-f]+:[ ]+32302573[ ]+csrr[ ]+a0,mhpmevent3
> > +[ ]+[0-9a-f]+:[ ]+32402573[ ]+csrr[ ]+a0,mhpmevent4
> > +[ ]+[0-9a-f]+:[ ]+32502573[ ]+csrr[ ]+a0,mhpmevent5
> > +[ ]+[0-9a-f]+:[ ]+32602573[ ]+csrr[ ]+a0,mhpmevent6
> > +[ ]+[0-9a-f]+:[ ]+32702573[ ]+csrr[ ]+a0,mhpmevent7
> > +[ ]+[0-9a-f]+:[ ]+32802573[ ]+csrr[ ]+a0,mhpmevent8
> > +[ ]+[0-9a-f]+:[ ]+32902573[ ]+csrr[ ]+a0,mhpmevent9
> > +[ ]+[0-9a-f]+:[ ]+32a02573[ ]+csrr[ ]+a0,mhpmevent10
> > +[ ]+[0-9a-f]+:[ ]+32b02573[ ]+csrr[ ]+a0,mhpmevent11
> > +[ ]+[0-9a-f]+:[ ]+32c02573[ ]+csrr[ ]+a0,mhpmevent12
> > +[ ]+[0-9a-f]+:[ ]+32d02573[ ]+csrr[ ]+a0,mhpmevent13
> > +[ ]+[0-9a-f]+:[ ]+32e02573[ ]+csrr[ ]+a0,mhpmevent14
> > +[ ]+[0-9a-f]+:[ ]+32f02573[ ]+csrr[ ]+a0,mhpmevent15
> > +[ ]+[0-9a-f]+:[ ]+33002573[ ]+csrr[ ]+a0,mhpmevent16
> > +[ ]+[0-9a-f]+:[ ]+33102573[ ]+csrr[ ]+a0,mhpmevent17
> > +[ ]+[0-9a-f]+:[ ]+33202573[ ]+csrr[ ]+a0,mhpmevent18
> > +[ ]+[0-9a-f]+:[ ]+33302573[ ]+csrr[ ]+a0,mhpmevent19
> > +[ ]+[0-9a-f]+:[ ]+33402573[ ]+csrr[ ]+a0,mhpmevent20
> > +[ ]+[0-9a-f]+:[ ]+33502573[ ]+csrr[ ]+a0,mhpmevent21
> > +[ ]+[0-9a-f]+:[ ]+33602573[ ]+csrr[ ]+a0,mhpmevent22
> > +[ ]+[0-9a-f]+:[ ]+33702573[ ]+csrr[ ]+a0,mhpmevent23
> > +[ ]+[0-9a-f]+:[ ]+33802573[ ]+csrr[ ]+a0,mhpmevent24
> > +[ ]+[0-9a-f]+:[ ]+33902573[ ]+csrr[ ]+a0,mhpmevent25
> > +[ ]+[0-9a-f]+:[ ]+33a02573[ ]+csrr[ ]+a0,mhpmevent26
> > +[ ]+[0-9a-f]+:[ ]+33b02573[ ]+csrr[ ]+a0,mhpmevent27
> > +[ ]+[0-9a-f]+:[ ]+33c02573[ ]+csrr[ ]+a0,mhpmevent28
> > +[ ]+[0-9a-f]+:[ ]+33d02573[ ]+csrr[ ]+a0,mhpmevent29
> > +[ ]+[0-9a-f]+:[ ]+33e02573[ ]+csrr[ ]+a0,mhpmevent30
> > +[ ]+[0-9a-f]+:[ ]+33f02573[ ]+csrr[ ]+a0,mhpmevent31
> > +[ ]+[0-9a-f]+:[ ]+7a002573[ ]+csrr[ ]+a0,tselect
> > +[ ]+[0-9a-f]+:[ ]+7a102573[ ]+csrr[ ]+a0,tdata1
> > +[ ]+[0-9a-f]+:[ ]+7a202573[ ]+csrr[ ]+a0,tdata2
> > +[ ]+[0-9a-f]+:[ ]+7a302573[ ]+csrr[ ]+a0,tdata3
> > +[ ]+[0-9a-f]+:[ ]+7b002573[ ]+csrr[ ]+a0,dcsr
> > +[ ]+[0-9a-f]+:[ ]+7b102573[ ]+csrr[ ]+a0,dpc
> > +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> > +[ ]+[0-9a-f]+:[ ]+7b302573[ ]+csrr[ ]+a0,dscratch1
> > +[ ]+[0-9a-f]+:[ ]+04302573[ ]+csrr[ ]+a0,utval
> > +[ ]+[0-9a-f]+:[ ]+14302573[ ]+csrr[ ]+a0,stval
> > +[ ]+[0-9a-f]+:[ ]+18002573[ ]+csrr[ ]+a0,satp
> > +[ ]+[0-9a-f]+:[ ]+34302573[ ]+csrr[ ]+a0,mtval
> > +[ ]+[0-9a-f]+:[ ]+32002573[ ]+csrr[ ]+a0,mcountinhibit
> > +[ ]+[0-9a-f]+:[ ]+7b202573[ ]+csrr[ ]+a0,dscratch0
> > +[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,hstatus
> > +[ ]+[0-9a-f]+:[ ]+20202573[ ]+csrr[ ]+a0,hedeleg
> > +[ ]+[0-9a-f]+:[ ]+20302573[ ]+csrr[ ]+a0,hideleg
> > +[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,hie
> > +[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,htvec
> > +[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,hscratch
> > +[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,hepc
> > +[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,hcause
> > +[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,hbadaddr
> > +[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,hip
> > +[ ]+[0-9a-f]+:[ ]+38002573[ ]+csrr[ ]+a0,mbase
> > +[ ]+[0-9a-f]+:[ ]+38102573[ ]+csrr[ ]+a0,mbound
> > +[ ]+[0-9a-f]+:[ ]+38202573[ ]+csrr[ ]+a0,mibase
> > +[ ]+[0-9a-f]+:[ ]+38302573[ ]+csrr[ ]+a0,mibound
> > +[ ]+[0-9a-f]+:[ ]+38402573[ ]+csrr[ ]+a0,mdbase
> > +[ ]+[0-9a-f]+:[ ]+38502573[ ]+csrr[ ]+a0,mdbound
> > +[ ]+[0-9a-f]+:[ ]+32102573[ ]+csrr[ ]+a0,mscounteren
> > +[ ]+[0-9a-f]+:[ ]+32202573[ ]+csrr[ ]+a0,mhcounteren
> > diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
> > index 72d97f9..8353f70 100644
> > --- a/gas/testsuite/gas/riscv/priv-reg.s
> > +++ b/gas/testsuite/gas/riscv/priv-reg.s
> > @@ -1,7 +1,8 @@
> > .macro csr val
> > csrr a0,\val
> > .endm
> > -# 1.9.1 registers
> > +
> > + # Supported the current priv spec 1.11.
> > csr ustatus
> > csr uie
> > csr utvec
> > @@ -9,7 +10,7 @@
> > csr uscratch
> > csr uepc
> > csr ucause
> > - csr ubadaddr
> > + csr utval # Added in 1.10
> > csr uip
> >
> > csr fflags
> > @@ -86,26 +87,15 @@
> > csr sideleg
> > csr sie
> > csr stvec
> > + csr scounteren # Added in 1.10
> >
> > csr sscratch
> > csr sepc
> > csr scause
> > - csr sbadaddr
> > + csr stval # Added in 1.10
> > csr sip
> >
> > - csr sptbr
> > -
> > - csr hstatus
> > - csr hedeleg
> > - csr hideleg
> > - csr hie
> > - csr htvec
> > -
> > - csr hscratch
> > - csr hepc
> > - csr hcause
> > - csr hbadaddr
> > - csr hip
> > + csr satp # Added in 1.10
> >
> > csr mvendorid
> > csr marchid
> > @@ -113,24 +103,39 @@
> > csr mhartid
> >
> > csr mstatus
> > - csr misa
> > + csr misa # 0xf10 in 1.9, but changed to 0x301 since 1.9.1.
> > csr medeleg
> > csr mideleg
> > csr mie
> > csr mtvec
> > + csr mcounteren # Added in 1.10
> >
> > csr mscratch
> > csr mepc
> > csr mcause
> > - csr mbadaddr
> > + csr mtval # Added in 1.10
> > csr mip
> >
> > - csr mbase
> > - csr mbound
> > - csr mibase
> > - csr mibound
> > - csr mdbase
> > - csr mdbound
> > + csr pmpcfg0 # Added in 1.10
> > + csr pmpcfg1 # Added in 1.10
> > + csr pmpcfg2 # Added in 1.10
> > + csr pmpcfg3 # Added in 1.10
> > + csr pmpaddr0 # Added in 1.10
> > + csr pmpaddr1 # Added in 1.10
> > + csr pmpaddr2 # Added in 1.10
> > + csr pmpaddr3 # Added in 1.10
> > + csr pmpaddr4 # Added in 1.10
> > + csr pmpaddr5 # Added in 1.10
> > + csr pmpaddr6 # Added in 1.10
> > + csr pmpaddr7 # Added in 1.10
> > + csr pmpaddr8 # Added in 1.10
> > + csr pmpaddr9 # Added in 1.10
> > + csr pmpaddr10 # Added in 1.10
> > + csr pmpaddr11 # Added in 1.10
> > + csr pmpaddr12 # Added in 1.10
> > + csr pmpaddr13 # Added in 1.10
> > + csr pmpaddr14 # Added in 1.10
> > + csr pmpaddr15 # Added in 1.10
> >
> > csr mcycle
> > csr minstret
> > @@ -195,10 +200,7 @@
> > csr mhpmcounter30h
> > csr mhpmcounter31h
> >
> > - csr mucounteren
> > - csr mscounteren
> > - csr mhcounteren
> > -
> > + csr mcountinhibit # Added in 1.11
> > csr mhpmevent3
> > csr mhpmevent4
> > csr mhpmevent5
> > @@ -236,34 +238,32 @@
> >
> > csr dcsr
> > csr dpc
> > - csr dscratch
> > -# 1.10 registers
> > - csr utval
> > -
> > - csr scounteren
> > - csr stval
> > - csr satp
> > + csr dscratch0 # Added in 1.11
> > + csr dscratch1 # Added in 1.11
> >
> > - csr mcounteren
> > - csr mtval
> > + # Supported in previous priv spec, but dropped now.
> > + csr ubadaddr # 0x043 in 1.9.1, but the value is utval since 1.10
> > + csr sbadaddr # 0x143 in 1.9.1, but the value is stval since 1.10
> > + csr sptbr # 0x180 in 1.9.1, but the value is satp since 1.10
> > + csr mbadaddr # 0x343 in 1.9.1, but the value is mtval since 1.10
> > + csr mucounteren # 0x320 in 1.9.1, dropped in 1.10, but the value is mcountinhibit since 1.11
> > + csr dscratch # 0x7b2 in 1.10, but the value is dscratch0 since 1.11
> >
> > - csr pmpcfg0
> > - csr pmpcfg1
> > - csr pmpcfg2
> > - csr pmpcfg3
> > - csr pmpaddr0
> > - csr pmpaddr1
> > - csr pmpaddr2
> > - csr pmpaddr3
> > - csr pmpaddr4
> > - csr pmpaddr5
> > - csr pmpaddr6
> > - csr pmpaddr7
> > - csr pmpaddr8
> > - csr pmpaddr9
> > - csr pmpaddr10
> > - csr pmpaddr11
> > - csr pmpaddr12
> > - csr pmpaddr13
> > - csr pmpaddr14
> > - csr pmpaddr15
> > + csr hstatus # 0x200, dropped in 1.10
> > + csr hedeleg # 0x202, dropped in 1.10
> > + csr hideleg # 0x203, dropped in 1.10
> > + csr hie # 0x204, dropped in 1.10
> > + csr htvec # 0x205, dropped in 1.10
> > + csr hscratch # 0x240, dropped in 1.10
> > + csr hepc # 0x241, dropped in 1.10
> > + csr hcause # 0x242, dropped in 1.10
> > + csr hbadaddr # 0x243, dropped in 1.10
> > + csr hip # 0x244, dropped in 1.10
> > + csr mbase # 0x380, dropped in 1.10
> > + csr mbound # 0x381, dropped in 1.10
> > + csr mibase # 0x382, dropped in 1.10
> > + csr mibound # 0x383, dropped in 1.10
> > + csr mdbase # 0x384, dropped in 1.10
> > + csr mdbound # 0x385, dropped in 1.10
> > + csr mscounteren # 0x321, dropped in 1.10
> > + csr mhcounteren # 0x322, dropped in 1.10
> > diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d
> > deleted file mode 100644
> > index 823601c..0000000
> > --- a/gas/testsuite/gas/riscv/satp.d
> > +++ /dev/null
> > @@ -1,11 +0,0 @@
> > -#as:
> > -#objdump: -dr
> > -
> > -.*:[ ]+file format .*
> > -
> > -
> > -Disassembly of section .text:
> > -
> > -0+000 <target>:
> > -[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> > -[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp
> > diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s
> > deleted file mode 100644
> > index f8aa766..0000000
> > --- a/gas/testsuite/gas/riscv/satp.s
> > +++ /dev/null
> > @@ -1,3 +0,0 @@
> > -target:
> > - csrr t0, satp
> > - csrr t0, sptbr
> > diff --git a/gdb/features/riscv/32bit-csr.xml b/gdb/features/riscv/32bit-csr.xml
> > index 5b79499..8173eeb 100644
> > --- a/gdb/features/riscv/32bit-csr.xml
> > +++ b/gdb/features/riscv/32bit-csr.xml
> > @@ -192,6 +192,7 @@
> > <reg name="mhpmcounter29h" bitsize="32"/>
> > <reg name="mhpmcounter30h" bitsize="32"/>
> > <reg name="mhpmcounter31h" bitsize="32"/>
> > + <reg name="mcountinhibit" bitsize="32"/>
> > <reg name="mhpmevent3" bitsize="32"/>
> > <reg name="mhpmevent4" bitsize="32"/>
> > <reg name="mhpmevent5" bitsize="32"/>
> > @@ -227,7 +228,8 @@
> > <reg name="tdata3" bitsize="32"/>
> > <reg name="dcsr" bitsize="32"/>
> > <reg name="dpc" bitsize="32"/>
> > - <reg name="dscratch" bitsize="32"/>
> > + <reg name="dscratch0" bitsize="32"/>
> > + <reg name="dscratch1" bitsize="32"/>
> > <reg name="hstatus" bitsize="32"/>
> > <reg name="hedeleg" bitsize="32"/>
> > <reg name="hideleg" bitsize="32"/>
> > @@ -244,7 +246,6 @@
> > <reg name="mibound" bitsize="32"/>
> > <reg name="mdbase" bitsize="32"/>
> > <reg name="mdbound" bitsize="32"/>
> > - <reg name="mucounteren" bitsize="32"/>
> > <reg name="mscounteren" bitsize="32"/>
> > <reg name="mhcounteren" bitsize="32"/>
> > </feature>
> > diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml
> > index 8ec0ffe..ed28964 100644
> > --- a/gdb/features/riscv/64bit-csr.xml
> > +++ b/gdb/features/riscv/64bit-csr.xml
> > @@ -127,6 +127,7 @@
> > <reg name="mhpmcounter29" bitsize="64"/>
> > <reg name="mhpmcounter30" bitsize="64"/>
> > <reg name="mhpmcounter31" bitsize="64"/>
> > + <reg name="mcountinhibit" bitsize="64"/>
> > <reg name="mhpmevent3" bitsize="64"/>
> > <reg name="mhpmevent4" bitsize="64"/>
> > <reg name="mhpmevent5" bitsize="64"/>
> > @@ -162,7 +163,8 @@
> > <reg name="tdata3" bitsize="64"/>
> > <reg name="dcsr" bitsize="64"/>
> > <reg name="dpc" bitsize="64"/>
> > - <reg name="dscratch" bitsize="64"/>
> > + <reg name="dscratch0" bitsize="64"/>
> > + <reg name="dscratch1" bitsize="64"/>
> > <reg name="hstatus" bitsize="64"/>
> > <reg name="hedeleg" bitsize="64"/>
> > <reg name="hideleg" bitsize="64"/>
> > @@ -179,7 +181,6 @@
> > <reg name="mibound" bitsize="64"/>
> > <reg name="mdbase" bitsize="64"/>
> > <reg name="mdbound" bitsize="64"/>
> > - <reg name="mucounteren" bitsize="64"/>
> > <reg name="mscounteren" bitsize="64"/>
> > <reg name="mhcounteren" bitsize="64"/>
> > </feature>
> > diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> > index 18d0b15..fe00bb6 100644
> > --- a/include/opcode/riscv-opc.h
> > +++ b/include/opcode/riscv-opc.h
> > @@ -575,6 +575,7 @@
> > #define MASK_CUSTOM3_RD_RS1 0x707f
> > #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
> > #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
> > +/* Support CSR to priv spec 1.11. */
> > #define CSR_USTATUS 0x0
> > #define CSR_UIE 0x4
> > #define CSR_UTVEC 0x5
> > @@ -655,6 +656,7 @@
> > #define CSR_SIDELEG 0x103
> > #define CSR_SIE 0x104
> > #define CSR_STVEC 0x105
> > +/* scounteren is present int priv spec 1.10. */
> > #define CSR_SCOUNTEREN 0x106
> > #define CSR_SSCRATCH 0x140
> > #define CSR_SEPC 0x141
> > @@ -667,17 +669,20 @@
> > #define CSR_MIMPID 0xf13
> > #define CSR_MHARTID 0xf14
> > #define CSR_MSTATUS 0x300
> > +/* misa is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> > #define CSR_MISA 0x301
> > #define CSR_MEDELEG 0x302
> > #define CSR_MIDELEG 0x303
> > #define CSR_MIE 0x304
> > #define CSR_MTVEC 0x305
> > +/* mcounteren is present in priv spec 1.10. */
> > #define CSR_MCOUNTEREN 0x306
> > #define CSR_MSCRATCH 0x340
> > #define CSR_MEPC 0x341
> > #define CSR_MCAUSE 0x342
> > #define CSR_MTVAL 0x343
> > #define CSR_MIP 0x344
> > +/* pmpcfg0 to pmpcfg3, pmpaddr0 to pmpaddr15 are present in priv spec 1.10. */
> > #define CSR_PMPCFG0 0x3a0
> > #define CSR_PMPCFG1 0x3a1
> > #define CSR_PMPCFG2 0x3a2
> > @@ -760,6 +765,8 @@
> > #define CSR_MHPMCOUNTER29H 0xb9d
> > #define CSR_MHPMCOUNTER30H 0xb9e
> > #define CSR_MHPMCOUNTER31H 0xb9f
> > +/* mcountinhibit is present in priv spec 1.11. */
> > +#define CSR_MCOUNTINHIBIT 0x320
> > #define CSR_MHPMEVENT3 0x323
> > #define CSR_MHPMEVENT4 0x324
> > #define CSR_MHPMEVENT5 0x325
> > @@ -795,8 +802,10 @@
> > #define CSR_TDATA3 0x7a3
> > #define CSR_DCSR 0x7b0
> > #define CSR_DPC 0x7b1
> > -#define CSR_DSCRATCH 0x7b2
> > -/* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> > +/* dscratch0 and dscratch1 are present in priv spec 1.11. */
> > +#define CSR_DSCRATCH0 0x7b2
> > +#define CSR_DSCRATCH1 0x7b3
> > +/* These registers are present in priv spec 1.9.1, but are dropped in 1.10. */
> > #define CSR_HSTATUS 0x200
> > #define CSR_HEDELEG 0x202
> > #define CSR_HIDELEG 0x203
> > @@ -807,16 +816,15 @@
> > #define CSR_HCAUSE 0x242
> > #define CSR_HBADADDR 0x243
> > #define CSR_HIP 0x244
> > -/* CSR_MISA is 0xf10 in 1.9, but 0x301 in 1.9.1. */
> > #define CSR_MBASE 0x380
> > #define CSR_MBOUND 0x381
> > #define CSR_MIBASE 0x382
> > #define CSR_MIBOUND 0x383
> > #define CSR_MDBASE 0x384
> > #define CSR_MDBOUND 0x385
> > -#define CSR_MUCOUNTEREN 0x320
> > #define CSR_MSCOUNTEREN 0x321
> > #define CSR_MHCOUNTEREN 0x322
> > +
> > #define CAUSE_MISALIGNED_FETCH 0x0
> > #define CAUSE_FAULT_FETCH 0x1
> > #define CAUSE_ILLEGAL_INSTRUCTION 0x2
> > @@ -1301,6 +1309,7 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32)
> > DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32)
> > DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32)
> > DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32)
> > +DECLARE_CSR(mcountinhibit, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> > DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I)
> > DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I)
> > DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I)
> > @@ -1336,7 +1345,8 @@ DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I)
> > DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I)
> > DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I)
> > DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I)
> > -DECLARE_CSR(dscratch, CSR_DSCRATCH, CSR_CLASS_I)
> > +DECLARE_CSR(dscratch0, CSR_DSCRATCH0, CSR_CLASS_I)
> > +DECLARE_CSR(dscratch1, CSR_DSCRATCH1, CSR_CLASS_I)
> > /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
> > DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I)
> > DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I)
> > @@ -1354,7 +1364,6 @@ DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I)
> > DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I)
> > DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I)
> > DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I)
> > -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN, CSR_CLASS_I)
> > DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I)
> > DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I)
> > #endif
> > @@ -1367,6 +1376,10 @@ DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I)
> > DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I)
> > /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
> > DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I)
> > +/* Mucounteren is 0x320 in 1.10, but 0x320 is mcountinhibit in 1.11. */
> > +DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I)
> > +/* Dscratch is 0x7b2 in 1.10, but 0x7b2 is dscratch0 in 1.11. */
> > +DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I)
> > #endif
> > #ifdef DECLARE_CAUSE
> > DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [0/1] RISC-V: Update CSR to priv 1.11.
2020-03-12 10:00 [0/1] RISC-V: Update CSR to priv 1.11 Nelson Chu
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
@ 2020-06-08 15:37 ` Tom Tromey
2020-06-08 21:39 ` Andrew Burgess
2020-06-09 17:30 ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
1 sibling, 2 replies; 34+ messages in thread
From: Tom Tromey @ 2020-06-08 15:37 UTC (permalink / raw)
To: Nelson Chu; +Cc: gdb-patches, andrew.burgess
>>>>> ">" == Nelson Chu <nelson.chu@sifive.com> writes:
>> Since RISCV priv spec 1.11 has been officially released, it would be good if
>> binutils, gdb, qemu and OpenOCD can support the new CSR. Therfore, I update
>> the CSR to 1.11 in binutils, and the gdm xml files and gas/testsuite/gas/riscv/csr-dw-regnums
>> also need to be updated. There are two difference between 1.10 and 1.11,
>> 1. 0x320 is mcountinhibit rather than mucounteren. You can still use the
>> mucounteren, but objdump will show mcountinhibit for it.
>> 2. 0x7b2 is dscratch0 rather than dscratch, and 0x7b3 is dscratch1. You
>> can still use the old naming, but objdump will show the new one.
I noticed that this patch broke compatibility between gdb and some
versions of qemu.
We're using qemu 4.0.0. Our internal test suite has many failures if I
run an unpatched gdb against this version -- locally I've backed out all
RISC-V patches since this one, but that's getting cumbersome, and I
belated realized I should probably just bring this up.
A typical failure looks like:
(gdb) info registers dscratch
dscratch Could not fetch register "dscratch"; remote failure reply 'E14'
It seems to me that the best thing to do would be to have gdb adapt to
the registers that are reported by the remote. Is there a reason this
was not done?
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [0/1] RISC-V: Update CSR to priv 1.11.
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
@ 2020-06-08 21:39 ` Andrew Burgess
2020-06-09 1:19 ` Jim Wilson
2020-06-09 20:12 ` Tom Tromey
2020-06-09 17:30 ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
1 sibling, 2 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-08 21:39 UTC (permalink / raw)
To: Tom Tromey; +Cc: Nelson Chu, gdb-patches
* Tom Tromey <tom@tromey.com> [2020-06-08 09:37:43 -0600]:
> >>>>> ">" == Nelson Chu <nelson.chu@sifive.com> writes:
>
> >> Since RISCV priv spec 1.11 has been officially released, it would be good if
> >> binutils, gdb, qemu and OpenOCD can support the new CSR. Therfore, I update
> >> the CSR to 1.11 in binutils, and the gdm xml files and gas/testsuite/gas/riscv/csr-dw-regnums
> >> also need to be updated. There are two difference between 1.10 and 1.11,
>
> >> 1. 0x320 is mcountinhibit rather than mucounteren. You can still use the
> >> mucounteren, but objdump will show mcountinhibit for it.
>
> >> 2. 0x7b2 is dscratch0 rather than dscratch, and 0x7b3 is dscratch1. You
> >> can still use the old naming, but objdump will show the new one.
>
> I noticed that this patch broke compatibility between gdb and some
> versions of qemu.
>
> We're using qemu 4.0.0. Our internal test suite has many failures if I
> run an unpatched gdb against this version -- locally I've backed out all
> RISC-V patches since this one, but that's getting cumbersome, and I
> belated realized I should probably just bring this up.
>
> A typical failure looks like:
>
> (gdb) info registers dscratch
> dscratch Could not fetch register "dscratch"; remote failure reply 'E14'
>
> It seems to me that the best thing to do would be to have gdb adapt to
> the registers that are reported by the remote. Is there a reason this
> was not done?
Unless I misunderstand here, you asking why we don't use the xml
target descriptions? We do. Or we _should_ do. Maybe it's not
working? Is your target definitely sending back a description? And
it definitely includes register "dscratch" ?
This patch (the only you replied too) is only changing the default xml
description, the one that gets picked up if the target doesn't supply
a description.
I'll try to get QEMU built and running tomorrow and see if I can give
you a better answer, however, the patch below might help. It adds an
alias from 'dscratch' to 'dscratch0', so your 'info registers
dscratch' should start working again.
Let me know if this helps at all.
Thanks,
Andrew
---
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 6edf77a0ce0..42ca6440756 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3380,6 +3380,10 @@ riscv_gdbarch_init (struct gdbarch_info info,
riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
+ static int dscratch_regnum = RISCV_CSR_DSCRATCH0_REGNUM;
+ user_reg_add (gdbarch, "dscratch", value_of_riscv_user_reg,
+ &dscratch_regnum);
+
/* Compile command hooks. */
set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options);
set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp);
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [0/1] RISC-V: Update CSR to priv 1.11.
2020-06-08 21:39 ` Andrew Burgess
@ 2020-06-09 1:19 ` Jim Wilson
2020-06-09 10:27 ` Andrew Burgess
2020-06-09 20:12 ` Tom Tromey
1 sibling, 1 reply; 34+ messages in thread
From: Jim Wilson @ 2020-06-09 1:19 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, gdb-patches
On Mon, Jun 8, 2020 at 2:39 PM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> Unless I misunderstand here, you asking why we don't use the xml
> target descriptions? We do. Or we _should_ do. Maybe it's not
> working? Is your target definitely sending back a description? And
> it definitely includes register "dscratch" ?
qemu does have xml support; I added it. The xml register files were
copied straight from the gdb xml files at the time I wrote the
patches. Unfortunately, no one is actively maintaining this code, or
actively testing it, unless maybe you count Tom who is apparently
testing it, so the xml files no longer match the gdb ones. The old
qemu version of the files does have a dscratch register because gdb
had it at the time. qemu does have a concept of priv spec version,
but I doubt anyone has given any thought about how to match the xml
files to the priv spec version. Currently, there is a single set of
xml files, and that isn't going to work long term. The list of csr
registers needs to depend on the priv spec version. descratch was
added in priv spec 1.9, and was dropped in 1.11. qemu 4.0 has 1.9.1
and 1.10 support, so dscratch is a valid register name for priv spec
versions supported by qemu (though qemu is dropping 1.9.1 from the
development tree). Anyways, dscratch needs to work in gdb, adding an
alias sounds like a reasonable solution. There is a DECLARE_CSR_ALIAS
in include/opcode/riscv-opc.h for dscratch and other affected csrs,
but I guess gdb isn't handling those at the moment
Jim
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [0/1] RISC-V: Update CSR to priv 1.11.
2020-06-09 1:19 ` Jim Wilson
@ 2020-06-09 10:27 ` Andrew Burgess
0 siblings, 0 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-09 10:27 UTC (permalink / raw)
To: Jim Wilson; +Cc: Tom Tromey, gdb-patches
* Jim Wilson <jimw@sifive.com> [2020-06-08 18:19:17 -0700]:
> On Mon, Jun 8, 2020 at 2:39 PM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > Unless I misunderstand here, you asking why we don't use the xml
> > target descriptions? We do. Or we _should_ do. Maybe it's not
> > working? Is your target definitely sending back a description? And
> > it definitely includes register "dscratch" ?
>
> qemu does have xml support; I added it. The xml register files were
> copied straight from the gdb xml files at the time I wrote the
> patches. Unfortunately, no one is actively maintaining this code, or
> actively testing it, unless maybe you count Tom who is apparently
> testing it, so the xml files no longer match the gdb ones.
That's absolutely fine. There's no requirement for QEMU to match
GDB[1], GDB's builtin XML files are only looked at in the case where
the target doesn't provide one[2].
> The old
> qemu version of the files does have a dscratch register because gdb
> had it at the time. qemu does have a concept of priv spec version,
> but I doubt anyone has given any thought about how to match the xml
> files to the priv spec version. Currently, there is a single set of
> xml files, and that isn't going to work long term. The list of csr
> registers needs to depend on the priv spec version.
Absolutely and right now this is totally a qemu issue, it needs to
dynamically build the xml based on the type of target that's being
emulated.
We already do some of this in riscv_create_target_description, when we
build the default target description, we select 32 or 64 bit x-regs,
and optionally add 32 or 64 bit f-regs based on the features we think
the target has (which is based on the file being debugged).
In the future we might want to extend this if we do more native RISC-V
debugging, this could query the priv level and adjust the csr regs as
needed, but I don't have any targets where I could test this.
> descratch was
> added in priv spec 1.9, and was dropped in 1.11. qemu 4.0 has 1.9.1
> and 1.10 support, so dscratch is a valid register name for priv spec
> versions supported by qemu (though qemu is dropping 1.9.1 from the
> development tree). Anyways, dscratch needs to work in gdb, adding an
> alias sounds like a reasonable solution.
I would suggest that if the target provides a description then we
should be pretty conservative with which aliases we add. I don't know
if adding a dscratch to dscratch0 alias would be something I'm in
favour of or not. Though I'm conflicted, because it seems obvious
that GDB should create aliases for things like ra/x1 sp/x2, etc, so
maybe I'm just x-reg elitist...
> There is a DECLARE_CSR_ALIAS
> in include/opcode/riscv-opc.h for dscratch and other affected csrs,
> but I guess gdb isn't handling those at the moment
No but we probably should. I took a quick look at this but ran into
some issues. I'm going to try and see if I can get this all figured
out.
Thanks,
Andrew
[1] There are some requirements like the target must announce the full
set of integer registers, but there's no requirement for an exact
match, and as far as CSRs, pretty much anything goes.
[2] I'm willing to be convinced that I messed up, but I'm describing
what _should_ be happening.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [RFC] gdb/riscv: Improved register alias name creation
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
2020-06-08 21:39 ` Andrew Burgess
@ 2020-06-09 17:30 ` Andrew Burgess
2020-06-09 20:14 ` Jim Wilson
2020-06-09 20:54 ` Tom Tromey
1 sibling, 2 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-09 17:30 UTC (permalink / raw)
To: Tom Tromey; +Cc: Nelson Chu, gdb-patches
The patch below has had only minimal testing so far, but I'm sharing
it here so it can be discussed while I also get it tested.
This changes how the 'csr%d' aliases are created, and adds the
dscratch to dscratch0 alias.
Feedback and comments welcome.
Thanks,
Andrew
---
This commit does two things:
1. Makes use of the DECLARE_CSR_ALIAS definitions in riscv-opc.h to
add additional aliases for CSRs.
2. Only creates aliases for registers that are actually present on
the target (as announced in the target XML description).
This means that the 'csr%d' aliases that exist will only be created
for those CSRs the target actually has, which is a nice improvement,
as accessing one of the CSRs that didn't exist would cause GDB to
crash with this error:
valprint.c:1560: internal-error: bool maybe_negate_by_bytes(const gdb_byte*, unsigned int, bfd_endian, gdb::byte_vector*): Assertion `len > 0' failed.
When we look at the DECLARE_CSR_ALIAS lines in riscv-opc.h, these can
be split into three groups:
DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1)
The 'misa' register used to exist of offset 0xf10, but was moved to
its current offset (0x301) in with privilege spec 1.9.1. We don't
want GDB to create an alias called 'misa' as we will already have a
'misa' register created by the DECLARE_CSR(misa ....) call earlier in
riscv-opc.h
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
These aliases are all CSRs that were removed in privilege spec 1.10,
and whose addresses were reused by new CSRs. The names meaning of the
old names is totally different to the new CSRs that have taken their
place. I don't believe we should add these as aliases into GDB. If
the new CSR exists in the target then that should be enough.
DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11)
In privilege spec 1.11 the 'dscratch' register was renamed to
'dscratch0', however the meaning of the register didn't change.
Adding the 'dscratch' alias makes sense I think.
Looking then at the final PRIV_SPEC_CLASS_* field for each alias then
we can see that currently we only want to take the alias from
PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter
the aliases within GDB.
In the future there's no telling how DECLARE_CSR_ALIAS will be used.
I've heard it said that future RISC-V privilege specs will not reuse
CSR offsets again. But it could happen. We just don't know.
If / when it does we may need to revisit how aliases are created for
GDB, but for now this seems to be OK.
gdb/ChangeLog:
* riscv-tdep.c (riscv_create_csr_aliases): Handle csr aliases from
riscv-opc.h.
(class riscv_pending_register_alias): New class.
(riscv_check_tdesc_feature): Take vector of pending aliases and
populate it as appropriate.
(riscv_setup_register_aliases): Delete.
(riscv_gdbarch_init): Create vector of pending aliases and pass it
to riscv_check_tdesc_feature in all cases. Use the vector to
create the register aliases.
---
gdb/ChangeLog | 12 ++++++
gdb/riscv-tdep.c | 97 +++++++++++++++++++++++++++++++++---------------
2 files changed, 80 insertions(+), 29 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 0842dcbcb23..d1c8949290a 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -258,6 +258,16 @@ riscv_create_csr_aliases ()
int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
const char *alias = xstrprintf ("csr%d", csr_num);
reg.names.push_back (alias);
+
+ /* Setup the other csr aliases. We don't use a switch table here in
+ case there are multiple aliases with the same value. Also filter
+ based on ABRT_VER in order to avoid a very old alias for misa that
+ duplicates the name "misa" but at a different CSR address. */
+#define DECLARE_CSR_ALIAS(NAME,VALUE,CLASS,DEF_VER,ABRT_VER) \
+ if (csr_num == VALUE && ABRT_VER >= PRIV_SPEC_CLASS_1P11) \
+ reg.names.push_back ( # NAME );
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR_ALIAS
}
}
@@ -2945,6 +2955,37 @@ riscv_find_default_target_description (const struct gdbarch_info info)
return riscv_lookup_target_description (features);
}
+/* Information about a register alias that needs to be set up for this
+ target. These are collected when the target's XML description is
+ analysed, and then processed later, once the gdbarch has been created. */
+
+class riscv_pending_register_alias
+{
+public:
+ /* Constructor. */
+
+ riscv_pending_register_alias (const char *name, const void *baton)
+ : m_name (name),
+ m_baton (baton)
+ { /* Nothing. */ }
+
+ /* Convert this into a user register for GDBARCH. */
+
+ void create (struct gdbarch *gdbarch) const
+ {
+ user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton);
+ }
+
+private:
+ /* The name for this alias. */
+ const char *m_name;
+
+ /* The baton value for passing to user_reg_add. This must point to some
+ data that will live for at least as long as the gdbarch object to
+ which the user register is attached. */
+ const void *m_baton;
+};
+
/* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
is updated with the register numbers for each register as listed in
REG_SET. If any register marked as required in REG_SET is not found in
@@ -2953,7 +2994,8 @@ riscv_find_default_target_description (const struct gdbarch_info info)
static bool
riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
const struct tdesc_feature *feature,
- const struct riscv_register_feature *reg_set)
+ const struct riscv_register_feature *reg_set,
+ std::vector<riscv_pending_register_alias> *aliases)
{
for (const auto ® : reg_set->registers)
{
@@ -2965,7 +3007,17 @@ riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
if (found)
- break;
+ {
+ /* We know that the target description mentions this
+ register. Add any aliases for this register onto the list
+ of pending aliases. */
+ for (const char *alias : reg.names)
+ {
+ if (alias != name)
+ aliases->emplace_back (alias, (void *)®.regnum);
+ }
+ break;
+ }
}
if (!found && reg.required_p)
@@ -2993,24 +3045,6 @@ riscv_add_reggroups (struct gdbarch *gdbarch)
reggroup_add (gdbarch, csr_reggroup);
}
-/* Create register aliases for all the alternative names that exist for
- registers in REG_SET. */
-
-static void
-riscv_setup_register_aliases (struct gdbarch *gdbarch,
- const struct riscv_register_feature *reg_set)
-{
- for (auto ® : reg_set->registers)
- {
- /* The first item in the names list is the preferred name for the
- register, this is what RISCV_REGISTER_NAME returns, and so we
- don't need to create an alias with that name here. */
- for (int i = 1; i < reg.names.size (); ++i)
- user_reg_add (gdbarch, reg.names[i], value_of_riscv_user_reg,
- ®.regnum);
- }
-}
-
/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
static int
@@ -3114,10 +3148,12 @@ riscv_gdbarch_init (struct gdbarch_info info,
return NULL;
struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
+ std::vector<riscv_pending_register_alias> pending_aliases;
bool valid_p = riscv_check_tdesc_feature (tdesc_data,
feature_cpu,
- &riscv_xreg_feature);
+ &riscv_xreg_feature,
+ &pending_aliases);
if (valid_p)
{
/* Check that all of the core cpu registers have the same bitsize. */
@@ -3137,7 +3173,8 @@ riscv_gdbarch_init (struct gdbarch_info info,
if (feature_fpu != NULL)
{
valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
- &riscv_freg_feature);
+ &riscv_freg_feature,
+ &pending_aliases);
/* Search for the first floating point register (by any alias), to
determine the bitsize. */
@@ -3173,11 +3210,13 @@ riscv_gdbarch_init (struct gdbarch_info info,
if (feature_virtual)
riscv_check_tdesc_feature (tdesc_data, feature_virtual,
- &riscv_virtual_feature);
+ &riscv_virtual_feature,
+ &pending_aliases);
if (feature_csr)
riscv_check_tdesc_feature (tdesc_data, feature_csr,
- &riscv_csr_feature);
+ &riscv_csr_feature,
+ &pending_aliases);
if (!valid_p)
{
@@ -3315,11 +3354,11 @@ riscv_gdbarch_init (struct gdbarch_info info,
want, ignoring what the target tells us. */
set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
- /* Create register aliases for alternative register names. */
- riscv_setup_register_aliases (gdbarch, &riscv_xreg_feature);
- if (riscv_has_fp_regs (gdbarch))
- riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
- riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
+ /* Create register aliases for alternative register names. We only
+ create aliases for registers which were mentioned in the target
+ description. */
+ for (const auto &alias : pending_aliases)
+ alias.create (gdbarch);
/* Compile command hooks. */
set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options);
--
2.25.4
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [0/1] RISC-V: Update CSR to priv 1.11.
2020-06-08 21:39 ` Andrew Burgess
2020-06-09 1:19 ` Jim Wilson
@ 2020-06-09 20:12 ` Tom Tromey
1 sibling, 0 replies; 34+ messages in thread
From: Tom Tromey @ 2020-06-09 20:12 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, Nelson Chu, gdb-patches
Andrew> Unless I misunderstand here, you asking why we don't use the xml
Andrew> target descriptions? We do. Or we _should_ do. Maybe it's not
Andrew> working? Is your target definitely sending back a description? And
Andrew> it definitely includes register "dscratch" ?
It's definitely sending back a description, and it definitely includes
dscratch. I did "set remotefilelog ..."; I've appended the relevant
lines.
Andrew> I'll try to get QEMU built and running tomorrow and see if I can give
Andrew> you a better answer, however, the patch below might help. It adds an
Andrew> alias from 'dscratch' to 'dscratch0', so your 'info registers
Andrew> dscratch' should start working again.
Andrew> Let me know if this helps at all.
It doesn't seem to make a difference.
Tom
w +$qXfer:features:read:target.xml:0,ffb#79
r +$l<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><xi:include href="riscv-64bit-cpu.xml"/><xi:include href="riscv-64bit-fpu.xml"/><xi:include href="riscv-64bit-csr.xml"/></target>#ca
w +$qXfer:features:read:riscv-64bit-cpu.xml:0,ffb#64
r +$l<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n Copying and distribution of this file, with or without modification,\n are permitted in any medium without royalty provided the copyright\n notice and this notice are preserved. -->\n\n<!-- Register numbers are hard-coded in order to maintain backward\n compatibility with older versions of tools that didn't use xml\n register descriptions. -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.cpu">\n <reg name="zero" bitsize="64" type="int" regnum="0"/>\n <reg name="ra" bitsize="64" type="code_ptr"/>\n <reg name="sp" bitsize="64" type="data_ptr"/>\n <reg name="gp" bitsize="64" type="data_ptr"/>\n <reg name="tp" bitsize="64" type="data_ptr"/>\n <reg name="t0" bitsize="64" type="int"/>\n <reg name="t1" bitsize="64" type="int"/>\n <reg name="t2" bitsize="64" type="int"/>\n <reg name="fp" bitsize="64" type="data_ptr"/>\n <reg name="s1" bitsize="64" type="int"/>\n <reg name="a0" bitsize="64" type="int"/>\n <reg name="a1" bitsize="64" type="int"/>\n <reg name="a2" bitsize="64" type="int"/>\n <reg name="a3" bitsize="64" type="int"/>\n <reg name="a4" bitsize="64" type="int"/>\n <reg name="a5" bitsize="64" type="int"/>\n <reg name="a6" bitsize="64" type="int"/>\n <reg name="a7" bitsize="64" type="int"/>\n <reg name="s2" bitsize="64" type="int"/>\n <reg name="s3" bitsize="64" type="int"/>\n <reg name="s4" bitsize="64" type="int"/>\n <reg name="s5" bitsize="64" type="int"/>\n <reg name="s6" bitsize="64" type="int"/>\n <reg name="s7" bitsize="64" type="int"/>\n <reg name="s8" bitsize="64" type="int"/>\n <reg name="s9" bitsize="64" type="int"/>\n <reg name="s10" bitsize="64" type="int"/>\n <reg name="s11" bitsize="64" type="int"/>\n <reg name="t3" bitsize="64" type="int"/>\n <reg name="t4" bitsize="64" type="int"/>\n <reg name="t5" bitsize="64" type="int"/>\n <reg name="t6" bitsize="64" type="int"/>\n <reg name="pc" bitsize="64" type="code_ptr"/>\n</feature>\n#3d
w +$qXfer:features:read:riscv-64bit-fpu.xml:0,ffb#67
r +$m<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n Copying and distribution of this file, with or without modification,\n are permitted in any medium without royalty provided the copyright\n notice and this notice are preserved. -->\n\n<!-- Register numbers are hard-coded in order to maintain backward\n compatibility with older versions of tools that didn't use xml\n register descriptions. -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.fpu">\n\n <union id="riscv_double">\n <field name="float" type="ieee_single"/>\n <field name="double" type="ieee_double"/>\n </union>\n\n <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>\n <reg name="ft1" bitsize="64" type="riscv_double"/>\n <reg name="ft2" bitsize="64" type="riscv_double"/>\n <reg name="ft3" bitsize="64" type="riscv_double"/>\n <reg name="ft4" bitsize="64" type="riscv_double"/>\n <reg name="ft5" bitsize="64" type="riscv_double"/>\n <reg name="ft6" bitsize="64" type="riscv_double"/>\n <reg name="ft7" bitsize="64" type="riscv_double"/>\n <reg name="fs0" bitsize="64" type="riscv_double"/>\n <reg name="fs1" bitsize="64" type="riscv_double"/>\n <reg name="fa0" bitsize="64" type="riscv_double"/>\n <reg name="fa1" bitsize="64" type="riscv_double"/>\n <reg name="fa2" bitsize="64" type="riscv_double"/>\n <reg name="fa3" bitsize="64" type="riscv_double"/>\n <reg name="fa4" bitsize="64" type="riscv_double"/>\n <reg name="fa5" bitsize="64" type="riscv_double"/>\n <reg name="fa6" bitsize="64" type="riscv_double"/>\n <reg name="fa7" bitsize="64" type="riscv_double"/>\n <reg name="fs2" bitsize="64" type="riscv_double"/>\n <reg name="fs3" bitsize="64" type="riscv_double"/>\n <reg name="fs4" bitsize="64" type="riscv_double"/>\n <reg name="fs5" bitsize="64" type="riscv_double"/>\n <reg name="fs6" bitsize="64" type="riscv_double"/>\n <reg name="fs7" bitsize="64" type="riscv_double"/>\n <reg name="fs8" bitsize="64" type="riscv_double"/>\n <reg name="fs9" bitsize="64" type="riscv_doub#ad
w +$qXfer:features:read:riscv-64bit-fpu.xml:7fd,ffb#38
r +$lle"/>\n <reg name="fs10" bitsize="64" type="riscv_double"/>\n <reg name="fs11" bitsize="64" type="riscv_double"/>\n <reg name="ft8" bitsize="64" type="riscv_double"/>\n <reg name="ft9" bitsize="64" type="riscv_double"/>\n <reg name="ft10" bitsize="64" type="riscv_double"/>\n <reg name="ft11" bitsize="64" type="riscv_double"/>\n\n <reg name="fflags" bitsize="32" type="int" regnum="66"/>\n <reg name="frm" bitsize="32" type="int" regnum="67"/>\n <reg name="fcsr" bitsize="32" type="int" regnum="68"/>\n</feature>\n#55
w +$qXfer:features:read:riscv-64bit-csr.xml:0,ffb#64
r +$m<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n Copying and distribution of this file, with or without modification,\n are permitted in any medium without royalty provided the copyright\n notice and this notice are preserved. -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.csr">\n <reg name="ustatus" bitsize="64"/>\n <reg name="uie" bitsize="64"/>\n <reg name="utvec" bitsize="64"/>\n <reg name="uscratch" bitsize="64"/>\n <reg name="uepc" bitsize="64"/>\n <reg name="ucause" bitsize="64"/>\n <reg name="utval" bitsize="64"/>\n <reg name="uip" bitsize="64"/>\n <reg name="fflags" bitsize="64"/>\n <reg name="frm" bitsize="64"/>\n <reg name="fcsr" bitsize="64"/>\n <reg name="cycle" bitsize="64"/>\n <reg name="time" bitsize="64"/>\n <reg name="instret" bitsize="64"/>\n <reg name="hpmcounter3" bitsize="64"/>\n <reg name="hpmcounter4" bitsize="64"/>\n <reg name="hpmcounter5" bitsize="64"/>\n <reg name="hpmcounter6" bitsize="64"/>\n <reg name="hpmcounter7" bitsize="64"/>\n <reg name="hpmcounter8" bitsize="64"/>\n <reg name="hpmcounter9" bitsize="64"/>\n <reg name="hpmcounter10" bitsize="64"/>\n <reg name="hpmcounter11" bitsize="64"/>\n <reg name="hpmcounter12" bitsize="64"/>\n <reg name="hpmcounter13" bitsize="64"/>\n <reg name="hpmcounter14" bitsize="64"/>\n <reg name="hpmcounter15" bitsize="64"/>\n <reg name="hpmcounter16" bitsize="64"/>\n <reg name="hpmcounter17" bitsize="64"/>\n <reg name="hpmcounter18" bitsize="64"/>\n <reg name="hpmcounter19" bitsize="64"/>\n <reg name="hpmcounter20" bitsize="64"/>\n <reg name="hpmcounter21" bitsize="64"/>\n <reg name="hpmcounter22" bitsize="64"/>\n <reg name="hpmcounter23" bitsize="64"/>\n <reg name="hpmcounter24" bitsize="64"/>\n <reg name="hpmcounter25" bitsize="64"/>\n <reg name="hpmcounter26" bitsize="64"/>\n <reg name="hpmcounter27" bitsize="64"/>\n <reg name="hpmcounter28" bitsize="64"/>\n <reg name="hpmcounter29" bitsize="64"/>\n <reg name="hpmcounter30" bitsize="64"/>\n <reg name="hpmcounter31"#12
w +$qXfer:features:read:riscv-64bit-csr.xml:7fd,ffb#35
r +$m bitsize="64"/>\n <reg name="cycleh" bitsize="64"/>\n <reg name="timeh" bitsize="64"/>\n <reg name="instreth" bitsize="64"/>\n <reg name="hpmcounter3h" bitsize="64"/>\n <reg name="hpmcounter4h" bitsize="64"/>\n <reg name="hpmcounter5h" bitsize="64"/>\n <reg name="hpmcounter6h" bitsize="64"/>\n <reg name="hpmcounter7h" bitsize="64"/>\n <reg name="hpmcounter8h" bitsize="64"/>\n <reg name="hpmcounter9h" bitsize="64"/>\n <reg name="hpmcounter10h" bitsize="64"/>\n <reg name="hpmcounter11h" bitsize="64"/>\n <reg name="hpmcounter12h" bitsize="64"/>\n <reg name="hpmcounter13h" bitsize="64"/>\n <reg name="hpmcounter14h" bitsize="64"/>\n <reg name="hpmcounter15h" bitsize="64"/>\n <reg name="hpmcounter16h" bitsize="64"/>\n <reg name="hpmcounter17h" bitsize="64"/>\n <reg name="hpmcounter18h" bitsize="64"/>\n <reg name="hpmcounter19h" bitsize="64"/>\n <reg name="hpmcounter20h" bitsize="64"/>\n <reg name="hpmcounter21h" bitsize="64"/>\n <reg name="hpmcounter22h" bitsize="64"/>\n <reg name="hpmcounter23h" bitsize="64"/>\n <reg name="hpmcounter24h" bitsize="64"/>\n <reg name="hpmcounter25h" bitsize="64"/>\n <reg name="hpmcounter26h" bitsize="64"/>\n <reg name="hpmcounter27h" bitsize="64"/>\n <reg name="hpmcounter28h" bitsize="64"/>\n <reg name="hpmcounter29h" bitsize="64"/>\n <reg name="hpmcounter30h" bitsize="64"/>\n <reg name="hpmcounter31h" bitsize="64"/>\n <reg name="sstatus" bitsize="64"/>\n <reg name="sedeleg" bitsize="64"/>\n <reg name="sideleg" bitsize="64"/>\n <reg name="sie" bitsize="64"/>\n <reg name="stvec" bitsize="64"/>\n <reg name="scounteren" bitsize="64"/>\n <reg name="sscratch" bitsize="64"/>\n <reg name="sepc" bitsize="64"/>\n <reg name="scause" bitsize="64"/>\n <reg name="stval" bitsize="64"/>\n <reg name="sip" bitsize="64"/>\n <reg name="satp" bitsize="64"/>\n <reg name="mvendorid" bitsize="64"/>\n <reg name="marchid" bitsize="64"/>\n <reg name="mimpid" bitsize="64"/>\n <reg name="mhartid" bitsize="64"/>\n <reg name="mstatus" bitsize="64"/>\n <reg name="misa" bitsize="64"/>\n <reg name="medeleg" bitsize="#68
w +$qXfer:features:read:riscv-64bit-csr.xml:ffa,ffb#61
r +$m64"/>\n <reg name="mideleg" bitsize="64"/>\n <reg name="mie" bitsize="64"/>\n <reg name="mtvec" bitsize="64"/>\n <reg name="mcounteren" bitsize="64"/>\n <reg name="mscratch" bitsize="64"/>\n <reg name="mepc" bitsize="64"/>\n <reg name="mcause" bitsize="64"/>\n <reg name="mtval" bitsize="64"/>\n <reg name="mip" bitsize="64"/>\n <reg name="pmpcfg0" bitsize="64"/>\n <reg name="pmpcfg1" bitsize="64"/>\n <reg name="pmpcfg2" bitsize="64"/>\n <reg name="pmpcfg3" bitsize="64"/>\n <reg name="pmpaddr0" bitsize="64"/>\n <reg name="pmpaddr1" bitsize="64"/>\n <reg name="pmpaddr2" bitsize="64"/>\n <reg name="pmpaddr3" bitsize="64"/>\n <reg name="pmpaddr4" bitsize="64"/>\n <reg name="pmpaddr5" bitsize="64"/>\n <reg name="pmpaddr6" bitsize="64"/>\n <reg name="pmpaddr7" bitsize="64"/>\n <reg name="pmpaddr8" bitsize="64"/>\n <reg name="pmpaddr9" bitsize="64"/>\n <reg name="pmpaddr10" bitsize="64"/>\n <reg name="pmpaddr11" bitsize="64"/>\n <reg name="pmpaddr12" bitsize="64"/>\n <reg name="pmpaddr13" bitsize="64"/>\n <reg name="pmpaddr14" bitsize="64"/>\n <reg name="pmpaddr15" bitsize="64"/>\n <reg name="mcycle" bitsize="64"/>\n <reg name="minstret" bitsize="64"/>\n <reg name="mhpmcounter3" bitsize="64"/>\n <reg name="mhpmcounter4" bitsize="64"/>\n <reg name="mhpmcounter5" bitsize="64"/>\n <reg name="mhpmcounter6" bitsize="64"/>\n <reg name="mhpmcounter7" bitsize="64"/>\n <reg name="mhpmcounter8" bitsize="64"/>\n <reg name="mhpmcounter9" bitsize="64"/>\n <reg name="mhpmcounter10" bitsize="64"/>\n <reg name="mhpmcounter11" bitsize="64"/>\n <reg name="mhpmcounter12" bitsize="64"/>\n <reg name="mhpmcounter13" bitsize="64"/>\n <reg name="mhpmcounter14" bitsize="64"/>\n <reg name="mhpmcounter15" bitsize="64"/>\n <reg name="mhpmcounter16" bitsize="64"/>\n <reg name="mhpmcounter17" bitsize="64"/>\n <reg name="mhpmcounter18" bitsize="64"/>\n <reg name="mhpmcounter19" bitsize="64"/>\n <reg name="mhpmcounter20" bitsize="64"/>\n <reg name="mhpmcounter21" bitsize="64"/>\n <reg name="mhpmcounter22" bitsize="64"/>\n <reg name="mhpmcounter23" b#51
w +$qXfer:features:read:riscv-64bit-csr.xml:17f7,ffb#39
r +$mitsize="64"/>\n <reg name="mhpmcounter24" bitsize="64"/>\n <reg name="mhpmcounter25" bitsize="64"/>\n <reg name="mhpmcounter26" bitsize="64"/>\n <reg name="mhpmcounter27" bitsize="64"/>\n <reg name="mhpmcounter28" bitsize="64"/>\n <reg name="mhpmcounter29" bitsize="64"/>\n <reg name="mhpmcounter30" bitsize="64"/>\n <reg name="mhpmcounter31" bitsize="64"/>\n <reg name="mcycleh" bitsize="64"/>\n <reg name="minstreth" bitsize="64"/>\n <reg name="mhpmcounter3h" bitsize="64"/>\n <reg name="mhpmcounter4h" bitsize="64"/>\n <reg name="mhpmcounter5h" bitsize="64"/>\n <reg name="mhpmcounter6h" bitsize="64"/>\n <reg name="mhpmcounter7h" bitsize="64"/>\n <reg name="mhpmcounter8h" bitsize="64"/>\n <reg name="mhpmcounter9h" bitsize="64"/>\n <reg name="mhpmcounter10h" bitsize="64"/>\n <reg name="mhpmcounter11h" bitsize="64"/>\n <reg name="mhpmcounter12h" bitsize="64"/>\n <reg name="mhpmcounter13h" bitsize="64"/>\n <reg name="mhpmcounter14h" bitsize="64"/>\n <reg name="mhpmcounter15h" bitsize="64"/>\n <reg name="mhpmcounter16h" bitsize="64"/>\n <reg name="mhpmcounter17h" bitsize="64"/>\n <reg name="mhpmcounter18h" bitsize="64"/>\n <reg name="mhpmcounter19h" bitsize="64"/>\n <reg name="mhpmcounter20h" bitsize="64"/>\n <reg name="mhpmcounter21h" bitsize="64"/>\n <reg name="mhpmcounter22h" bitsize="64"/>\n <reg name="mhpmcounter23h" bitsize="64"/>\n <reg name="mhpmcounter24h" bitsize="64"/>\n <reg name="mhpmcounter25h" bitsize="64"/>\n <reg name="mhpmcounter26h" bitsize="64"/>\n <reg name="mhpmcounter27h" bitsize="64"/>\n <reg name="mhpmcounter28h" bitsize="64"/>\n <reg name="mhpmcounter29h" bitsize="64"/>\n <reg name="mhpmcounter30h" bitsize="64"/>\n <reg name="mhpmcounter31h" bitsize="64"/>\n <reg name="mhpmevent3" bitsize="64"/>\n <reg name="mhpmevent4" bitsize="64"/>\n <reg name="mhpmevent5" bitsize="64"/>\n <reg name="mhpmevent6" bitsize="64"/>\n <reg name="mhpmevent7" bitsize="64"/>\n <reg name="mhpmevent8" bitsize="64"/>\n <reg name="mhpmevent9" bitsize="64"/>\n <reg name="mhpmevent10" bitsize="64"/>\n <reg name="mhpmeven#dc
w +$qXfer:features:read:riscv-64bit-csr.xml:1ff4,ffb#65
r +$lt11" bitsize="64"/>\n <reg name="mhpmevent12" bitsize="64"/>\n <reg name="mhpmevent13" bitsize="64"/>\n <reg name="mhpmevent14" bitsize="64"/>\n <reg name="mhpmevent15" bitsize="64"/>\n <reg name="mhpmevent16" bitsize="64"/>\n <reg name="mhpmevent17" bitsize="64"/>\n <reg name="mhpmevent18" bitsize="64"/>\n <reg name="mhpmevent19" bitsize="64"/>\n <reg name="mhpmevent20" bitsize="64"/>\n <reg name="mhpmevent21" bitsize="64"/>\n <reg name="mhpmevent22" bitsize="64"/>\n <reg name="mhpmevent23" bitsize="64"/>\n <reg name="mhpmevent24" bitsize="64"/>\n <reg name="mhpmevent25" bitsize="64"/>\n <reg name="mhpmevent26" bitsize="64"/>\n <reg name="mhpmevent27" bitsize="64"/>\n <reg name="mhpmevent28" bitsize="64"/>\n <reg name="mhpmevent29" bitsize="64"/>\n <reg name="mhpmevent30" bitsize="64"/>\n <reg name="mhpmevent31" bitsize="64"/>\n <reg name="tselect" bitsize="64"/>\n <reg name="tdata1" bitsize="64"/>\n <reg name="tdata2" bitsize="64"/>\n <reg name="tdata3" bitsize="64"/>\n <reg name="dcsr" bitsize="64"/>\n <reg name="dpc" bitsize="64"/>\n <reg name="dscratch" bitsize="64"/>\n <reg name="hstatus" bitsize="64"/>\n <reg name="hedeleg" bitsize="64"/>\n <reg name="hideleg" bitsize="64"/>\n <reg name="hie" bitsize="64"/>\n <reg name="htvec" bitsize="64"/>\n <reg name="hscratch" bitsize="64"/>\n <reg name="hepc" bitsize="64"/>\n <reg name="hcause" bitsize="64"/>\n <reg name="hbadaddr" bitsize="64"/>\n <reg name="hip" bitsize="64"/>\n <reg name="mbase" bitsize="64"/>\n <reg name="mbound" bitsize="64"/>\n <reg name="mibase" bitsize="64"/>\n <reg name="mibound" bitsize="64"/>\n <reg name="mdbase" bitsize="64"/>\n <reg name="mdbound" bitsize="64"/>\n <reg name="mucounteren" bitsize="64"/>\n <reg name="mscounteren" bitsize="64"/>\n <reg name="mhcounteren" bitsize="64"/>\n</feature>\n#9f
w +$qTStatus#49
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 17:30 ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
@ 2020-06-09 20:14 ` Jim Wilson
2020-06-09 22:47 ` Andrew Burgess
2020-06-09 20:54 ` Tom Tromey
1 sibling, 1 reply; 34+ messages in thread
From: Jim Wilson @ 2020-06-09 20:14 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, gdb-patches
On Tue, Jun 9, 2020 at 10:30 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> Looking then at the final PRIV_SPEC_CLASS_* field for each alias then
> we can see that currently we only want to take the alias from
> PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter
> the aliases within GDB.
This will do the right thing, but looks a little funny. It isn't
quite the right way to express what we want. I do think it is OK for
now, but we will have to be careful when maintaining binutils that we
don't break this assumption, or remember to update it when necessary.
Otherwise this look OK to me.
Jim
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 17:30 ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
2020-06-09 20:14 ` Jim Wilson
@ 2020-06-09 20:54 ` Tom Tromey
2020-06-09 22:30 ` Andrew Burgess
` (2 more replies)
1 sibling, 3 replies; 34+ messages in thread
From: Tom Tromey @ 2020-06-09 20:54 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, Nelson Chu, gdb-patches
>>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
Andrew> The patch below has had only minimal testing so far, but I'm sharing
Andrew> it here so it can be discussed while I also get it tested.
Andrew> This changes how the 'csr%d' aliases are created, and adds the
Andrew> dscratch to dscratch0 alias.
I backed out the reversion here; then I did a new merge; then I applied
this patch and re-ran our internal test suite.
It still fails -- though it does change the failures I see. Now it
complains about a different register:
(gdb) call debug.trace (me, "You")
Could not fetch register "mucounteren"; remote failure reply 'E14'
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 20:54 ` Tom Tromey
@ 2020-06-09 22:30 ` Andrew Burgess
[not found] ` <8736735bjx.fsf@tromey.com>
2020-06-10 20:37 ` Jim Wilson
2020-06-09 22:58 ` Andrew Burgess
2020-06-10 20:34 ` [RFC] " Jim Wilson
2 siblings, 2 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-09 22:30 UTC (permalink / raw)
To: Tom Tromey; +Cc: Nelson Chu, gdb-patches
* Tom Tromey <tom@tromey.com> [2020-06-09 14:54:23 -0600]:
> >>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
>
> Andrew> The patch below has had only minimal testing so far, but I'm sharing
> Andrew> it here so it can be discussed while I also get it tested.
>
> Andrew> This changes how the 'csr%d' aliases are created, and adds the
> Andrew> dscratch to dscratch0 alias.
>
> I backed out the reversion here; then I did a new merge; then I applied
> this patch and re-ran our internal test suite.
>
> It still fails -- though it does change the failures I see. Now it
> complains about a different register:
>
> (gdb) call debug.trace (me, "You")
> Could not fetch register "mucounteren"; remote failure reply 'E14'
That is so weird! Based on the dump you included in the other email I
would have expected that to work.
Please would it be possible for you to gather two logs using "set
remotefilelog ..." as before. For each log I'd like to see:
1. Connect to the target,
2. Print $dscratch,
3. print $mucounteren
Could you do this with current whatever GDB you were using above, and
then again with whatever patches you need to back out in order to get
it working again.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 20:14 ` Jim Wilson
@ 2020-06-09 22:47 ` Andrew Burgess
2020-06-10 9:31 ` Nelson Chu
0 siblings, 1 reply; 34+ messages in thread
From: Andrew Burgess @ 2020-06-09 22:47 UTC (permalink / raw)
To: Jim Wilson; +Cc: Tom Tromey, gdb-patches
* Jim Wilson <jimw@sifive.com> [2020-06-09 13:14:58 -0700]:
> On Tue, Jun 9, 2020 at 10:30 AM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > Looking then at the final PRIV_SPEC_CLASS_* field for each alias then
> > we can see that currently we only want to take the alias from
> > PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter
> > the aliases within GDB.
>
> This will do the right thing, but looks a little funny. It isn't
> quite the right way to express what we want. I do think it is OK for
> now, but we will have to be careful when maintaining binutils that we
> don't break this assumption, or remember to update it when necessary.
I agree. I certainly open to any other ideas.
Without making changes to the DECLARE_CSR_ALIAS macro (and I don't
know what changes I would make) I saw my options as either:
- Ignore DECLARE_CSR_ALIAS, and hard code the "approved" aliases into
GDB. Then it'll never break, we just need to remember to update
the hard coded list when riscv-opc.h changes, or
- Filter the alias list from riscv-opc.h.
I went with the second option, partly because, if, from now on RISC-V
doesn't reuse old CSR offsets for new CSRs, then any new aliases
should be compatible.... I hope.
Anyway, always happy to take suggestions.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 20:54 ` Tom Tromey
2020-06-09 22:30 ` Andrew Burgess
@ 2020-06-09 22:58 ` Andrew Burgess
2020-06-10 12:53 ` Tom Tromey
2020-06-10 20:34 ` [RFC] " Jim Wilson
2 siblings, 1 reply; 34+ messages in thread
From: Andrew Burgess @ 2020-06-09 22:58 UTC (permalink / raw)
To: Tom Tromey; +Cc: Nelson Chu, gdb-patches
* Tom Tromey <tom@tromey.com> [2020-06-09 14:54:23 -0600]:
> >>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
>
> Andrew> The patch below has had only minimal testing so far, but I'm sharing
> Andrew> it here so it can be discussed while I also get it tested.
>
> Andrew> This changes how the 'csr%d' aliases are created, and adds the
> Andrew> dscratch to dscratch0 alias.
>
> I backed out the reversion here; then I did a new merge; then I applied
> this patch and re-ran our internal test suite.
>
> It still fails -- though it does change the failures I see. Now it
> complains about a different register:
>
> (gdb) call debug.trace (me, "You")
> Could not fetch register "mucounteren"; remote failure reply 'E14'
So I forgot to say, the reason I'm so confused by this is that getting
the 'remote failure reply ...' message indicates that GDB does know
about the register, is correctly asking for it, but the remote is not
providing the register.
I rolled GDB back to commit d8af906814bd69dad694e475288401b1dee6ac3a,
which is just before commit the 'RISC-V: Update CSR to privileged spec
1.11.', so based on your original email I was expecting this to work -
unfortunately I'm still seeing the same error here.
Can you confirm which version of GDB you see this passing with.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 22:47 ` Andrew Burgess
@ 2020-06-10 9:31 ` Nelson Chu
2020-06-10 10:55 ` Andrew Burgess
0 siblings, 1 reply; 34+ messages in thread
From: Nelson Chu @ 2020-06-10 9:31 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Jim Wilson, Tom Tromey, gdb-patches
Hi Andrew,
The patch is pretty good to me. Thanks for your quick reply and fix.
I have some ideas and minor things when I try to support debug csr for
now.
On Wed, Jun 10, 2020 at 6:47 AM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> * Jim Wilson <jimw@sifive.com> [2020-06-09 13:14:58 -0700]:
> > On Tue, Jun 9, 2020 at 10:30 AM Andrew Burgess
> > <andrew.burgess@embecosm.com> wrote:
> > > Looking then at the final PRIV_SPEC_CLASS_* field for each alias then
> > > we can see that currently we only want to take the alias from
> > > PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter
> > > the aliases within GDB.
> >
> > This will do the right thing, but looks a little funny. It isn't
> > quite the right way to express what we want. I do think it is OK for
> > now, but we will have to be careful when maintaining binutils that we
> > don't break this assumption, or remember to update it when necessary.
>
> I agree. I certainly open to any other ideas.
>
> Without making changes to the DECLARE_CSR_ALIAS macro (and I don't
> know what changes I would make) I saw my options as either:
>
> - Ignore DECLARE_CSR_ALIAS, and hard code the "approved" aliases into
> GDB. Then it'll never break, we just need to remember to update
> the hard coded list when riscv-opc.h changes, or
>
> - Filter the alias list from riscv-opc.h.
>
> I went with the second option, partly because, if, from now on RISC-V
> doesn't reuse old CSR offsets for new CSRs, then any new aliases
> should be compatible.... I hope.
I think we already have a consensus - It would be great if we only
support an alias with a new name, points at an existing CSR offset,
and the new name is a synonym for the existing CSR at that offset.
For the current FSF tree, there is only one CSR dscratch is an alias.
But I'm going to add the missing debug CSR to upstream, so there
should be more aliases in the future, and I think all of them follow
our consensus.
DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG,
PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
I think mcontrol, icount, itrigger and etrigger are the aliases to
tdata1. They all use 0x7a1 offset, and use type [top 5 bits] to
determine which one is used, so I believe they are similar to dscrach
and textra[32|64], and it's fine to define them by DECLARE_CSR_ALIAS.
The problem is that the debug csr and float csr actually belong to the
"unprivileged" CSR rather than privileged ones. That means, they
should be controlled by the debug specs and float specs rather than
the privileged specs. And in the future, vector CSR are also the
unprivileged ones controlled by the vector specs. But for now we
don't have a conclusion on how to let users choose the unprivileged
specs they want. Therefore, I plan to set their defined and aborted
versions to PRIV_SPEC_CLASS_NONE temporarily, including their aliases
(DECLARE_CSR_ALIAS). And the PRIV_SPEC_CLASS_NONE will be changed to
DEBUG_SPEC_CLASS_XXX and VECTOR_SPEC_CLASS_XXX in the future,
according to their CSR_CLASS_DEBUG and CSR_CLASS_V. This will affect
your current proposal, so I have an idea,
How about Gdb creates the aliases just according to the
DECLARE_CSR_ALIAS, and don't need to care about the spec versions for
now. Binutils have to make sure that the CSR, which is defined by
DECLARE_CSR_ALIAS, must be the case like dscrach and itrigger
mentioned above. For the ubadaddr, sbadaddr and others, I assume we
will drop them in the future and don't need to worry about them. So I
prefer to use another macro rather than DECLARE_CSR_ALIAS to define
them. Maybe DECLARE_CSR_ALIAS_TEMP or DECLARE_CSR_ALIAS_1p10?
I'm fine to use different ALIAS macros, since there are many meanings
for them, and Gdb can choose which ALIAS macros to support. Maybe
someday Gdb can recognize the PRIV_SPEC_CLASS_XXX, and what we worry
about, like misa and ubadaddr, may not be the troubles anymore. But
your current proposal is pretty good to me, so we can discuss this
later when we actually meet the problems. :)
Thanks
Nelson
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-10 9:31 ` Nelson Chu
@ 2020-06-10 10:55 ` Andrew Burgess
2020-06-10 13:26 ` Nelson Chu
0 siblings, 1 reply; 34+ messages in thread
From: Andrew Burgess @ 2020-06-10 10:55 UTC (permalink / raw)
To: Nelson Chu; +Cc: Jim Wilson, Tom Tromey, gdb-patches
* Nelson Chu <nelson.chu@sifive.com> [2020-06-10 17:31:00 +0800]:
> Hi Andrew,
>
> The patch is pretty good to me. Thanks for your quick reply and fix.
> I have some ideas and minor things when I try to support debug csr for
> now.
>
> On Wed, Jun 10, 2020 at 6:47 AM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > * Jim Wilson <jimw@sifive.com> [2020-06-09 13:14:58 -0700]:
> > > On Tue, Jun 9, 2020 at 10:30 AM Andrew Burgess
> > > <andrew.burgess@embecosm.com> wrote:
> > > > Looking then at the final PRIV_SPEC_CLASS_* field for each alias then
> > > > we can see that currently we only want to take the alias from
> > > > PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter
> > > > the aliases within GDB.
> > >
> > > This will do the right thing, but looks a little funny. It isn't
> > > quite the right way to express what we want. I do think it is OK for
> > > now, but we will have to be careful when maintaining binutils that we
> > > don't break this assumption, or remember to update it when necessary.
> >
> > I agree. I certainly open to any other ideas.
> >
> > Without making changes to the DECLARE_CSR_ALIAS macro (and I don't
> > know what changes I would make) I saw my options as either:
> >
> > - Ignore DECLARE_CSR_ALIAS, and hard code the "approved" aliases into
> > GDB. Then it'll never break, we just need to remember to update
> > the hard coded list when riscv-opc.h changes, or
> >
> > - Filter the alias list from riscv-opc.h.
> >
> > I went with the second option, partly because, if, from now on RISC-V
> > doesn't reuse old CSR offsets for new CSRs, then any new aliases
> > should be compatible.... I hope.
>
> I think we already have a consensus - It would be great if we only
> support an alias with a new name, points at an existing CSR offset,
> and the new name is a synonym for the existing CSR at that offset.
> For the current FSF tree, there is only one CSR dscratch is an alias.
> But I'm going to add the missing debug CSR to upstream, so there
> should be more aliases in the future, and I think all of them follow
> our consensus.
>
> DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR_ALIAS(mcontrol, CSR_TDATA1, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR_ALIAS(icount, CSR_TDATA1, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR_ALIAS(itrigger, CSR_TDATA1, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
> DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG,
> PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
>
> I think mcontrol, icount, itrigger and etrigger are the aliases to
> tdata1. They all use 0x7a1 offset, and use type [top 5 bits] to
> determine which one is used, so I believe they are similar to dscrach
> and textra[32|64], and it's fine to define them by DECLARE_CSR_ALIAS.
> The problem is that the debug csr and float csr actually belong to the
> "unprivileged" CSR rather than privileged ones. That means, they
> should be controlled by the debug specs and float specs rather than
> the privileged specs. And in the future, vector CSR are also the
> unprivileged ones controlled by the vector specs. But for now we
> don't have a conclusion on how to let users choose the unprivileged
> specs they want. Therefore, I plan to set their defined and aborted
> versions to PRIV_SPEC_CLASS_NONE temporarily, including their aliases
> (DECLARE_CSR_ALIAS). And the PRIV_SPEC_CLASS_NONE will be changed to
> DEBUG_SPEC_CLASS_XXX and VECTOR_SPEC_CLASS_XXX in the future,
> according to their CSR_CLASS_DEBUG and CSR_CLASS_V. This will affect
> your current proposal, so I have an idea,
>
> How about Gdb creates the aliases just according to the
> DECLARE_CSR_ALIAS, and don't need to care about the spec versions for
> now. Binutils have to make sure that the CSR, which is defined by
> DECLARE_CSR_ALIAS, must be the case like dscrach and itrigger
> mentioned above. For the ubadaddr, sbadaddr and others, I assume we
> will drop them in the future and don't need to worry about them. So I
> prefer to use another macro rather than DECLARE_CSR_ALIAS to define
> them. Maybe DECLARE_CSR_ALIAS_TEMP or DECLARE_CSR_ALIAS_1p10?
Nelson,
Thanks for your feedback. Do you plan to post a patch introducing the
DECLARE_CSR_ALIAS_* macros soon(ish) or should I go ahead with the
current version of my patch, and if/when you add the new macros you
can update GDB to only use the one we care about, and drop the version
check at that point?
Thanks,
Andrew
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 22:58 ` Andrew Burgess
@ 2020-06-10 12:53 ` Tom Tromey
[not found] ` <87mu5b3vm3.fsf@tromey.com>
0 siblings, 1 reply; 34+ messages in thread
From: Tom Tromey @ 2020-06-10 12:53 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, Nelson Chu, gdb-patches
>>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
Andrew> Can you confirm which version of GDB you see this passing with.
In both cases it's the result of a merge here, so it is gdb git, local
patches, and then either without the patches I originally replied to; or
with those, plus many patches after that (including the next RISC-V
series), plus your patch.
I can redo the experiment with gdb git. I'll do that shortly. I think
I can't run the whole internal test suite with that version though; but
a simple test should be enough to show if it's working.
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
[not found] ` <8736735bjx.fsf@tromey.com>
@ 2020-06-10 13:01 ` Tom Tromey
0 siblings, 0 replies; 34+ messages in thread
From: Tom Tromey @ 2020-06-10 13:01 UTC (permalink / raw)
To: Tom Tromey; +Cc: Andrew Burgess, Nelson Chu, gdb-patches
Andrew> 3. print $mucounteren
Tom> (gdb) print $mcounteren
I see now I typod the register name.
I'll redo the experiment in a bit.
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-10 10:55 ` Andrew Burgess
@ 2020-06-10 13:26 ` Nelson Chu
0 siblings, 0 replies; 34+ messages in thread
From: Nelson Chu @ 2020-06-10 13:26 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Jim Wilson, Tom Tromey, gdb-patches
>
> Hi Andrew,
Thanks for your feedback. Do you plan to post a patch introducing the
>
DECLARE_CSR_ALIAS_* macros soon(ish) or should I go ahead with the
> current version of my patch, and if/when you add the new macros you
> can update GDB to only use the one we care about, and drop the version
> check at that point?
I do plan to support the DECLARE_CSR_ALIAS_* recently if it is at least
good to you and Jim. I am glad to doing the changes that we are
discussing, that is, drop the version checking when we only need to care
about the DECLARE_CSR_ALIAS in gdb. So please feel free and go ahead.
Thank you very much, your fix in gdb is really helpful.
Thanks
Nelson
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
[not found] ` <87mu5b3vm3.fsf@tromey.com>
@ 2020-06-10 14:46 ` Tom Tromey
2020-06-11 13:16 ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
0 siblings, 1 reply; 34+ messages in thread
From: Tom Tromey @ 2020-06-10 14:46 UTC (permalink / raw)
To: Tom Tromey; +Cc: Andrew Burgess, Nelson Chu, gdb-patches
[-- Attachment #1: Type: text/plain, Size: 777 bytes --]
Tom> The first attachment is the log from git master.
Tom> Here's what I did:
Tom> (gdb) tar rem :7960
Tom> Remote debugging using :7960
Tom> 0x0000000000001000 in ?? ()
Tom> (gdb) print $dscratch
Tom> Could not fetch register "dscratch"; remote failure reply 'E14'
Tom> (gdb) print $dscratch0
Tom> $1 = void
Tom> (gdb) print $mucounteren
Tom> Could not fetch register "mucounteren"; remote failure reply 'E14'
I didn't apply your patch before that run.
Here's with your patch:
(gdb) tar rem :7960
Remote debugging using :7960
0x0000000000001000 in ?? ()
(gdb) print $dscratch
$1 = void
(gdb) print $dscratch0
Could not fetch register "dscratch0"; remote failure reply 'E14'
(gdb) print $mucounteren
Could not fetch register "mucounteren"; remote failure reply 'E14'
Tom
[-- Attachment #2: log with patch --]
[-- Type: text/plain, Size: 16957 bytes --]
w +$qSupported:multiprocess+;swbreak+;hwbreak+;qRelocInsn+;fork-events+;vfork-events+;exec-events+;vContSupported+;QThreadEvents+;no-resumed+;xmlRegisters=i386#6a
r +$PacketSize=1000;qXfer:features:read+;multiprocess+#5c
w +$vMustReplyEmpty#3a
r +$#00
w +$Hgp0.0#ad
r +$OK#9a
w +$qXfer:features:read:target.xml:0,ffb#79
r +$l<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><xi:include href="riscv-64bit-cpu.xml"/><xi:include href="riscv-64bit-fpu.xml"/><xi:include href="riscv-64bit-csr.xml"/></target>#ca
w +$qXfer:features:read:riscv-64bit-cpu.xml:0,ffb#64
r +$l<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n Copying and distribution of this file, with or without modification,\n are permitted in any medium without royalty provided the copyright\n notice and this notice are preserved. -->\n\n<!-- Register numbers are hard-coded in order to maintain backward\n compatibility with older versions of tools that didn't use xml\n register descriptions. -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.cpu">\n <reg name="zero" bitsize="64" type="int" regnum="0"/>\n <reg name="ra" bitsize="64" type="code_ptr"/>\n <reg name="sp" bitsize="64" type="data_ptr"/>\n <reg name="gp" bitsize="64" type="data_ptr"/>\n <reg name="tp" bitsize="64" type="data_ptr"/>\n <reg name="t0" bitsize="64" type="int"/>\n <reg name="t1" bitsize="64" type="int"/>\n <reg name="t2" bitsize="64" type="int"/>\n <reg name="fp" bitsize="64" type="data_ptr"/>\n <reg name="s1" bitsize="64" type="int"/>\n <reg name="a0" bitsize="64" type="int"/>\n <reg name="a1" bitsize="64" type="int"/>\n <reg name="a2" bitsize="64" type="int"/>\n <reg name="a3" bitsize="64" type="int"/>\n <reg name="a4" bitsize="64" type="int"/>\n <reg name="a5" bitsize="64" type="int"/>\n <reg name="a6" bitsize="64" type="int"/>\n <reg name="a7" bitsize="64" type="int"/>\n <reg name="s2" bitsize="64" type="int"/>\n <reg name="s3" bitsize="64" type="int"/>\n <reg name="s4" bitsize="64" type="int"/>\n <reg name="s5" bitsize="64" type="int"/>\n <reg name="s6" bitsize="64" type="int"/>\n <reg name="s7" bitsize="64" type="int"/>\n <reg name="s8" bitsize="64" type="int"/>\n <reg name="s9" bitsize="64" type="int"/>\n <reg name="s10" bitsize="64" type="int"/>\n <reg name="s11" bitsize="64" type="int"/>\n <reg name="t3" bitsize="64" type="int"/>\n <reg name="t4" bitsize="64" type="int"/>\n <reg name="t5" bitsize="64" type="int"/>\n <reg name="t6" bitsize="64" type="int"/>\n <reg name="pc" bitsize="64" type="code_ptr"/>\n</feature>\n#3d
w +$qXfer:features:read:riscv-64bit-fpu.xml:0,ffb#67
r +$m<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n Copying and distribution of this file, with or without modification,\n are permitted in any medium without royalty provided the copyright\n notice and this notice are preserved. -->\n\n<!-- Register numbers are hard-coded in order to maintain backward\n compatibility with older versions of tools that didn't use xml\n register descriptions. -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.fpu">\n\n <union id="riscv_double">\n <field name="float" type="ieee_single"/>\n <field name="double" type="ieee_double"/>\n </union>\n\n <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>\n <reg name="ft1" bitsize="64" type="riscv_double"/>\n <reg name="ft2" bitsize="64" type="riscv_double"/>\n <reg name="ft3" bitsize="64" type="riscv_double"/>\n <reg name="ft4" bitsize="64" type="riscv_double"/>\n <reg name="ft5" bitsize="64" type="riscv_double"/>\n <reg name="ft6" bitsize="64" type="riscv_double"/>\n <reg name="ft7" bitsize="64" type="riscv_double"/>\n <reg name="fs0" bitsize="64" type="riscv_double"/>\n <reg name="fs1" bitsize="64" type="riscv_double"/>\n <reg name="fa0" bitsize="64" type="riscv_double"/>\n <reg name="fa1" bitsize="64" type="riscv_double"/>\n <reg name="fa2" bitsize="64" type="riscv_double"/>\n <reg name="fa3" bitsize="64" type="riscv_double"/>\n <reg name="fa4" bitsize="64" type="riscv_double"/>\n <reg name="fa5" bitsize="64" type="riscv_double"/>\n <reg name="fa6" bitsize="64" type="riscv_double"/>\n <reg name="fa7" bitsize="64" type="riscv_double"/>\n <reg name="fs2" bitsize="64" type="riscv_double"/>\n <reg name="fs3" bitsize="64" type="riscv_double"/>\n <reg name="fs4" bitsize="64" type="riscv_double"/>\n <reg name="fs5" bitsize="64" type="riscv_double"/>\n <reg name="fs6" bitsize="64" type="riscv_double"/>\n <reg name="fs7" bitsize="64" type="riscv_double"/>\n <reg name="fs8" bitsize="64" type="riscv_double"/>\n <reg name="fs9" bitsize="64" type="riscv_doub#ad
w +$qXfer:features:read:riscv-64bit-fpu.xml:7fd,ffb#38
r +$lle"/>\n <reg name="fs10" bitsize="64" type="riscv_double"/>\n <reg name="fs11" bitsize="64" type="riscv_double"/>\n <reg name="ft8" bitsize="64" type="riscv_double"/>\n <reg name="ft9" bitsize="64" type="riscv_double"/>\n <reg name="ft10" bitsize="64" type="riscv_double"/>\n <reg name="ft11" bitsize="64" type="riscv_double"/>\n\n <reg name="fflags" bitsize="32" type="int" regnum="66"/>\n <reg name="frm" bitsize="32" type="int" regnum="67"/>\n <reg name="fcsr" bitsize="32" type="int" regnum="68"/>\n</feature>\n#55
w +$qXfer:features:read:riscv-64bit-csr.xml:0,ffb#64
r +$m<?xml version="1.0"?>\n<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.\n\n Copying and distribution of this file, with or without modification,\n are permitted in any medium without royalty provided the copyright\n notice and this notice are preserved. -->\n\n<!DOCTYPE feature SYSTEM "gdb-target.dtd">\n<feature name="org.gnu.gdb.riscv.csr">\n <reg name="ustatus" bitsize="64"/>\n <reg name="uie" bitsize="64"/>\n <reg name="utvec" bitsize="64"/>\n <reg name="uscratch" bitsize="64"/>\n <reg name="uepc" bitsize="64"/>\n <reg name="ucause" bitsize="64"/>\n <reg name="utval" bitsize="64"/>\n <reg name="uip" bitsize="64"/>\n <reg name="fflags" bitsize="64"/>\n <reg name="frm" bitsize="64"/>\n <reg name="fcsr" bitsize="64"/>\n <reg name="cycle" bitsize="64"/>\n <reg name="time" bitsize="64"/>\n <reg name="instret" bitsize="64"/>\n <reg name="hpmcounter3" bitsize="64"/>\n <reg name="hpmcounter4" bitsize="64"/>\n <reg name="hpmcounter5" bitsize="64"/>\n <reg name="hpmcounter6" bitsize="64"/>\n <reg name="hpmcounter7" bitsize="64"/>\n <reg name="hpmcounter8" bitsize="64"/>\n <reg name="hpmcounter9" bitsize="64"/>\n <reg name="hpmcounter10" bitsize="64"/>\n <reg name="hpmcounter11" bitsize="64"/>\n <reg name="hpmcounter12" bitsize="64"/>\n <reg name="hpmcounter13" bitsize="64"/>\n <reg name="hpmcounter14" bitsize="64"/>\n <reg name="hpmcounter15" bitsize="64"/>\n <reg name="hpmcounter16" bitsize="64"/>\n <reg name="hpmcounter17" bitsize="64"/>\n <reg name="hpmcounter18" bitsize="64"/>\n <reg name="hpmcounter19" bitsize="64"/>\n <reg name="hpmcounter20" bitsize="64"/>\n <reg name="hpmcounter21" bitsize="64"/>\n <reg name="hpmcounter22" bitsize="64"/>\n <reg name="hpmcounter23" bitsize="64"/>\n <reg name="hpmcounter24" bitsize="64"/>\n <reg name="hpmcounter25" bitsize="64"/>\n <reg name="hpmcounter26" bitsize="64"/>\n <reg name="hpmcounter27" bitsize="64"/>\n <reg name="hpmcounter28" bitsize="64"/>\n <reg name="hpmcounter29" bitsize="64"/>\n <reg name="hpmcounter30" bitsize="64"/>\n <reg name="hpmcounter31"#12
w +$qXfer:features:read:riscv-64bit-csr.xml:7fd,ffb#35
r +$m bitsize="64"/>\n <reg name="cycleh" bitsize="64"/>\n <reg name="timeh" bitsize="64"/>\n <reg name="instreth" bitsize="64"/>\n <reg name="hpmcounter3h" bitsize="64"/>\n <reg name="hpmcounter4h" bitsize="64"/>\n <reg name="hpmcounter5h" bitsize="64"/>\n <reg name="hpmcounter6h" bitsize="64"/>\n <reg name="hpmcounter7h" bitsize="64"/>\n <reg name="hpmcounter8h" bitsize="64"/>\n <reg name="hpmcounter9h" bitsize="64"/>\n <reg name="hpmcounter10h" bitsize="64"/>\n <reg name="hpmcounter11h" bitsize="64"/>\n <reg name="hpmcounter12h" bitsize="64"/>\n <reg name="hpmcounter13h" bitsize="64"/>\n <reg name="hpmcounter14h" bitsize="64"/>\n <reg name="hpmcounter15h" bitsize="64"/>\n <reg name="hpmcounter16h" bitsize="64"/>\n <reg name="hpmcounter17h" bitsize="64"/>\n <reg name="hpmcounter18h" bitsize="64"/>\n <reg name="hpmcounter19h" bitsize="64"/>\n <reg name="hpmcounter20h" bitsize="64"/>\n <reg name="hpmcounter21h" bitsize="64"/>\n <reg name="hpmcounter22h" bitsize="64"/>\n <reg name="hpmcounter23h" bitsize="64"/>\n <reg name="hpmcounter24h" bitsize="64"/>\n <reg name="hpmcounter25h" bitsize="64"/>\n <reg name="hpmcounter26h" bitsize="64"/>\n <reg name="hpmcounter27h" bitsize="64"/>\n <reg name="hpmcounter28h" bitsize="64"/>\n <reg name="hpmcounter29h" bitsize="64"/>\n <reg name="hpmcounter30h" bitsize="64"/>\n <reg name="hpmcounter31h" bitsize="64"/>\n <reg name="sstatus" bitsize="64"/>\n <reg name="sedeleg" bitsize="64"/>\n <reg name="sideleg" bitsize="64"/>\n <reg name="sie" bitsize="64"/>\n <reg name="stvec" bitsize="64"/>\n <reg name="scounteren" bitsize="64"/>\n <reg name="sscratch" bitsize="64"/>\n <reg name="sepc" bitsize="64"/>\n <reg name="scause" bitsize="64"/>\n <reg name="stval" bitsize="64"/>\n <reg name="sip" bitsize="64"/>\n <reg name="satp" bitsize="64"/>\n <reg name="mvendorid" bitsize="64"/>\n <reg name="marchid" bitsize="64"/>\n <reg name="mimpid" bitsize="64"/>\n <reg name="mhartid" bitsize="64"/>\n <reg name="mstatus" bitsize="64"/>\n <reg name="misa" bitsize="64"/>\n <reg name="medeleg" bitsize="#68
w +$qXfer:features:read:riscv-64bit-csr.xml:ffa,ffb#61
r +$m64"/>\n <reg name="mideleg" bitsize="64"/>\n <reg name="mie" bitsize="64"/>\n <reg name="mtvec" bitsize="64"/>\n <reg name="mcounteren" bitsize="64"/>\n <reg name="mscratch" bitsize="64"/>\n <reg name="mepc" bitsize="64"/>\n <reg name="mcause" bitsize="64"/>\n <reg name="mtval" bitsize="64"/>\n <reg name="mip" bitsize="64"/>\n <reg name="pmpcfg0" bitsize="64"/>\n <reg name="pmpcfg1" bitsize="64"/>\n <reg name="pmpcfg2" bitsize="64"/>\n <reg name="pmpcfg3" bitsize="64"/>\n <reg name="pmpaddr0" bitsize="64"/>\n <reg name="pmpaddr1" bitsize="64"/>\n <reg name="pmpaddr2" bitsize="64"/>\n <reg name="pmpaddr3" bitsize="64"/>\n <reg name="pmpaddr4" bitsize="64"/>\n <reg name="pmpaddr5" bitsize="64"/>\n <reg name="pmpaddr6" bitsize="64"/>\n <reg name="pmpaddr7" bitsize="64"/>\n <reg name="pmpaddr8" bitsize="64"/>\n <reg name="pmpaddr9" bitsize="64"/>\n <reg name="pmpaddr10" bitsize="64"/>\n <reg name="pmpaddr11" bitsize="64"/>\n <reg name="pmpaddr12" bitsize="64"/>\n <reg name="pmpaddr13" bitsize="64"/>\n <reg name="pmpaddr14" bitsize="64"/>\n <reg name="pmpaddr15" bitsize="64"/>\n <reg name="mcycle" bitsize="64"/>\n <reg name="minstret" bitsize="64"/>\n <reg name="mhpmcounter3" bitsize="64"/>\n <reg name="mhpmcounter4" bitsize="64"/>\n <reg name="mhpmcounter5" bitsize="64"/>\n <reg name="mhpmcounter6" bitsize="64"/>\n <reg name="mhpmcounter7" bitsize="64"/>\n <reg name="mhpmcounter8" bitsize="64"/>\n <reg name="mhpmcounter9" bitsize="64"/>\n <reg name="mhpmcounter10" bitsize="64"/>\n <reg name="mhpmcounter11" bitsize="64"/>\n <reg name="mhpmcounter12" bitsize="64"/>\n <reg name="mhpmcounter13" bitsize="64"/>\n <reg name="mhpmcounter14" bitsize="64"/>\n <reg name="mhpmcounter15" bitsize="64"/>\n <reg name="mhpmcounter16" bitsize="64"/>\n <reg name="mhpmcounter17" bitsize="64"/>\n <reg name="mhpmcounter18" bitsize="64"/>\n <reg name="mhpmcounter19" bitsize="64"/>\n <reg name="mhpmcounter20" bitsize="64"/>\n <reg name="mhpmcounter21" bitsize="64"/>\n <reg name="mhpmcounter22" bitsize="64"/>\n <reg name="mhpmcounter23" b#51
w +$qXfer:features:read:riscv-64bit-csr.xml:17f7,ffb#39
r +$mitsize="64"/>\n <reg name="mhpmcounter24" bitsize="64"/>\n <reg name="mhpmcounter25" bitsize="64"/>\n <reg name="mhpmcounter26" bitsize="64"/>\n <reg name="mhpmcounter27" bitsize="64"/>\n <reg name="mhpmcounter28" bitsize="64"/>\n <reg name="mhpmcounter29" bitsize="64"/>\n <reg name="mhpmcounter30" bitsize="64"/>\n <reg name="mhpmcounter31" bitsize="64"/>\n <reg name="mcycleh" bitsize="64"/>\n <reg name="minstreth" bitsize="64"/>\n <reg name="mhpmcounter3h" bitsize="64"/>\n <reg name="mhpmcounter4h" bitsize="64"/>\n <reg name="mhpmcounter5h" bitsize="64"/>\n <reg name="mhpmcounter6h" bitsize="64"/>\n <reg name="mhpmcounter7h" bitsize="64"/>\n <reg name="mhpmcounter8h" bitsize="64"/>\n <reg name="mhpmcounter9h" bitsize="64"/>\n <reg name="mhpmcounter10h" bitsize="64"/>\n <reg name="mhpmcounter11h" bitsize="64"/>\n <reg name="mhpmcounter12h" bitsize="64"/>\n <reg name="mhpmcounter13h" bitsize="64"/>\n <reg name="mhpmcounter14h" bitsize="64"/>\n <reg name="mhpmcounter15h" bitsize="64"/>\n <reg name="mhpmcounter16h" bitsize="64"/>\n <reg name="mhpmcounter17h" bitsize="64"/>\n <reg name="mhpmcounter18h" bitsize="64"/>\n <reg name="mhpmcounter19h" bitsize="64"/>\n <reg name="mhpmcounter20h" bitsize="64"/>\n <reg name="mhpmcounter21h" bitsize="64"/>\n <reg name="mhpmcounter22h" bitsize="64"/>\n <reg name="mhpmcounter23h" bitsize="64"/>\n <reg name="mhpmcounter24h" bitsize="64"/>\n <reg name="mhpmcounter25h" bitsize="64"/>\n <reg name="mhpmcounter26h" bitsize="64"/>\n <reg name="mhpmcounter27h" bitsize="64"/>\n <reg name="mhpmcounter28h" bitsize="64"/>\n <reg name="mhpmcounter29h" bitsize="64"/>\n <reg name="mhpmcounter30h" bitsize="64"/>\n <reg name="mhpmcounter31h" bitsize="64"/>\n <reg name="mhpmevent3" bitsize="64"/>\n <reg name="mhpmevent4" bitsize="64"/>\n <reg name="mhpmevent5" bitsize="64"/>\n <reg name="mhpmevent6" bitsize="64"/>\n <reg name="mhpmevent7" bitsize="64"/>\n <reg name="mhpmevent8" bitsize="64"/>\n <reg name="mhpmevent9" bitsize="64"/>\n <reg name="mhpmevent10" bitsize="64"/>\n <reg name="mhpmeven#dc
w +$qXfer:features:read:riscv-64bit-csr.xml:1ff4,ffb#65
r +$lt11" bitsize="64"/>\n <reg name="mhpmevent12" bitsize="64"/>\n <reg name="mhpmevent13" bitsize="64"/>\n <reg name="mhpmevent14" bitsize="64"/>\n <reg name="mhpmevent15" bitsize="64"/>\n <reg name="mhpmevent16" bitsize="64"/>\n <reg name="mhpmevent17" bitsize="64"/>\n <reg name="mhpmevent18" bitsize="64"/>\n <reg name="mhpmevent19" bitsize="64"/>\n <reg name="mhpmevent20" bitsize="64"/>\n <reg name="mhpmevent21" bitsize="64"/>\n <reg name="mhpmevent22" bitsize="64"/>\n <reg name="mhpmevent23" bitsize="64"/>\n <reg name="mhpmevent24" bitsize="64"/>\n <reg name="mhpmevent25" bitsize="64"/>\n <reg name="mhpmevent26" bitsize="64"/>\n <reg name="mhpmevent27" bitsize="64"/>\n <reg name="mhpmevent28" bitsize="64"/>\n <reg name="mhpmevent29" bitsize="64"/>\n <reg name="mhpmevent30" bitsize="64"/>\n <reg name="mhpmevent31" bitsize="64"/>\n <reg name="tselect" bitsize="64"/>\n <reg name="tdata1" bitsize="64"/>\n <reg name="tdata2" bitsize="64"/>\n <reg name="tdata3" bitsize="64"/>\n <reg name="dcsr" bitsize="64"/>\n <reg name="dpc" bitsize="64"/>\n <reg name="dscratch" bitsize="64"/>\n <reg name="hstatus" bitsize="64"/>\n <reg name="hedeleg" bitsize="64"/>\n <reg name="hideleg" bitsize="64"/>\n <reg name="hie" bitsize="64"/>\n <reg name="htvec" bitsize="64"/>\n <reg name="hscratch" bitsize="64"/>\n <reg name="hepc" bitsize="64"/>\n <reg name="hcause" bitsize="64"/>\n <reg name="hbadaddr" bitsize="64"/>\n <reg name="hip" bitsize="64"/>\n <reg name="mbase" bitsize="64"/>\n <reg name="mbound" bitsize="64"/>\n <reg name="mibase" bitsize="64"/>\n <reg name="mibound" bitsize="64"/>\n <reg name="mdbase" bitsize="64"/>\n <reg name="mdbound" bitsize="64"/>\n <reg name="mucounteren" bitsize="64"/>\n <reg name="mscounteren" bitsize="64"/>\n <reg name="mhcounteren" bitsize="64"/>\n</feature>\n#9f
w +$qTStatus#49
r +$#00
w +$?#3f
r +$T05thread:p01.01;#06
w +$qfThreadInfo#bb
r +$mp01.01#cd
w +$qsThreadInfo#c8
r +$l#6c
w +$qAttached:1#fa
r +$0#30
w +$Hc-1#09
r +$OK#9a
w +$qOffsets#4b
r +$#00
w +$g#67
r +$000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000#01
w +$qfThreadInfo#bb
r +$mp01.01#cd
w +$qsThreadInfo#c8
r +$l#6c
w +$m1000,4#8e
r +$97020000#92
w +$mffc,4#fc
r +$00000000#80
w +$qSymbol::#5b
r +$#00
w +
c print $dscratch
c print $dscratch0
w $p121#04
r +$E14#aa
w +
End of log
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 20:54 ` Tom Tromey
2020-06-09 22:30 ` Andrew Burgess
2020-06-09 22:58 ` Andrew Burgess
@ 2020-06-10 20:34 ` Jim Wilson
2 siblings, 0 replies; 34+ messages in thread
From: Jim Wilson @ 2020-06-10 20:34 UTC (permalink / raw)
To: Tom Tromey; +Cc: Andrew Burgess, gdb-patches
On Tue, Jun 9, 2020 at 1:54 PM Tom Tromey <tom@tromey.com> wrote:
> (gdb) call debug.trace (me, "You")
> Could not fetch register "mucounteren"; remote failure reply 'E14'
mucounteren is one of those inconvenient registers that got dropped,
and then its address got reused for a different unrelated register in
a later priv spec version. The easy solution is on the qemu side to
stop using this register, but that doesn't help anyone using a qemu
release. On the gdb side we would need to make gdb priv spec version
aware, or else lie to gdb and pretend that two unrelated registers in
different priv spec versions are the same register and hope that
doesn't cause trouble.
This priv spec version problem goes away once we drop all 1.9 and
1.9.1 support, because the compatibility problems only exist between
versions before 1.10 and versions 1.10 and later. I've been told that
there won't be any more compatibility breaks from 1.10 and later.
qemu never had 1.9 support, and has already proposed dropping 1.9.1
support on mainline, but of course older qemu releases have the 1.9.1
support. binutils still has 1.9 and 1.9.1 support, but I've suggested
to Nelson that he should drop the 1.9 support because I'm not aware of
anyone using it.
Jim
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-09 22:30 ` Andrew Burgess
[not found] ` <8736735bjx.fsf@tromey.com>
@ 2020-06-10 20:37 ` Jim Wilson
2020-06-11 8:28 ` Andrew Burgess
1 sibling, 1 reply; 34+ messages in thread
From: Jim Wilson @ 2020-06-10 20:37 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, gdb-patches
On Tue, Jun 9, 2020 at 3:31 PM Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> > (gdb) call debug.trace (me, "You")
> > Could not fetch register "mucounteren"; remote failure reply 'E14'
>
> That is so weird! Based on the dump you included in the other email I
> would have expected that to work.
Bu mucounteren is one of the registers that we chose not to make an
alias for because of the compatibility break. Apparently we will have
to make an alias for it anyways because qemu 4.0 wants it. And
someone should fix qemu to use the right register list depending on
the priv spec version.
Jim
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [RFC] gdb/riscv: Improved register alias name creation
2020-06-10 20:37 ` Jim Wilson
@ 2020-06-11 8:28 ` Andrew Burgess
0 siblings, 0 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-11 8:28 UTC (permalink / raw)
To: Jim Wilson; +Cc: Tom Tromey, gdb-patches
* Jim Wilson <jimw@sifive.com> [2020-06-10 13:37:03 -0700]:
> On Tue, Jun 9, 2020 at 3:31 PM Andrew Burgess
> <andrew.burgess@embecosm.com> wrote:
> > > (gdb) call debug.trace (me, "You")
> > > Could not fetch register "mucounteren"; remote failure reply 'E14'
> >
> > That is so weird! Based on the dump you included in the other email I
> > would have expected that to work.
>
> Bu mucounteren is one of the registers that we chose not to make an
> alias for because of the compatibility break. Apparently we will have
> to make an alias for it anyways because qemu 4.0 wants it.
No.
QEMU provides a register list that _includes_ mucounteren so GDB
doesn't need to know anything about this register or its aliases. The
XML built into GDB is used only for targets that don't provide a
target description. If a target provides a description, as in this
case, then the builtin description is not touched.
> And
> someone should fix qemu to use the right register list depending on
> the priv spec version.
Yes, this. Change the register description that QEMU sends based on
the machine its emulating and then GDB will "just work". GDB doesn't
need to know about privilege specs at all[1].
Thanks,
Andrew
[1] Native debugging is a slightly different case, but lets leave that
discussion for another day.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-10 14:46 ` Tom Tromey
@ 2020-06-11 13:16 ` Andrew Burgess
2020-06-11 13:16 ` [PATCH 1/2] " Andrew Burgess
` (2 more replies)
0 siblings, 3 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-11 13:16 UTC (permalink / raw)
To: gdb-patches
Tom,
Thanks for the logs, these set me in the right direction to find the
mistake in my patch.
I now have two patches. The first alone should be enough to get
things working for you now; it's basically the same patch as before
but with a small bug fix.
The second patch is a user experience improvement that seemed obvious
once I understood what was going wrong with the first patch.
After the first patch you should expect to be able to connect to the
remote and see this:
(gdb) p $dscratch
Could not fetch register "dscratch"; remote failure reply 'E14'
(gdb) p $dscratch0
Could not fetch register "dscratch"; remote failure reply 'E14'
However if you do 'info registers csr' you'll find this line:
dscratch0 Could not fetch register "dscratch"; remote failure reply 'E14'
Which is a little odd as your target description clearly says you have
'dscratch', not 'dscratch0'. After the second patch the same info
registers will now report:
dscratch Could not fetch register "dscratch"; remote failure reply 'E14'
This leaves just one question from me. I thought that your original
thread started by saying that once upon a time you could successfully
read the dscratch and/or the dscratch0 registers. The some patches
landed and you could no longer read the registers.
From what I'm seeing though, the _actual_ failure to read the register
is all QEMU. So my question, did I missunderstand the original
problem? Is there a build of GDB where you are able to read actual
values from these registers?
Either way, I think these patches should go in, so let me know if they
help at all.
Thanks,
Andrew
---
Andrew Burgess (2):
gdb/riscv: Improved register alias name creation
gdb/riscv: Take CSR names from target description
gdb/ChangeLog | 25 +++++++
gdb/riscv-tdep.c | 170 +++++++++++++++++++++++++++++++----------------
2 files changed, 137 insertions(+), 58 deletions(-)
--
2.25.4
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 1/2] gdb/riscv: Improved register alias name creation
2020-06-11 13:16 ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
@ 2020-06-11 13:16 ` Andrew Burgess
2020-06-11 13:16 ` [PATCH 2/2] gdb/riscv: Take CSR names from target description Andrew Burgess
2020-06-11 14:06 ` [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation Tom Tromey
2 siblings, 0 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-11 13:16 UTC (permalink / raw)
To: gdb-patches
This commit does two things:
1. Makes use of the DECLARE_CSR_ALIAS definitions in riscv-opc.h to
add additional aliases for CSRs.
2. Only creates aliases for registers that are actually present on
the target (as announced in the target XML description).
This means that the 'csr%d' aliases that exist will only be created
for those CSRs the target actually has, which is a nice improvement,
as accessing one of the CSRs that didn't exist would cause GDB to
crash with this error:
valprint.c:1560: internal-error: bool maybe_negate_by_bytes(const gdb_byte*, unsigned int, bfd_endian, gdb::byte_vector*): Assertion `len > 0' failed.
When we look at the DECLARE_CSR_ALIAS lines in riscv-opc.h, these can
be split into three groups:
DECLARE_CSR_ALIAS(misa, 0xf10, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P9P1)
The 'misa' register used to exist of offset 0xf10, but was moved to
its current offset (0x301) in with privilege spec 1.9.1. We don't
want GDB to create an alias called 'misa' as we will already have a
'misa' register created by the DECLARE_CSR(misa ....) call earlier in
riscv-opc.h
DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR_ALIAS(mucounteren, CSR_MCOUNTINHIBIT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P10)
These aliases are all CSRs that were removed in privilege spec 1.10,
and whose addresses were reused by new CSRs. The names meaning of the
old names is totally different to the new CSRs that have taken their
place. I don't believe we should add these as aliases into GDB. If
the new CSR exists in the target then that should be enough.
DECLARE_CSR_ALIAS(dscratch, CSR_DSCRATCH0, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9, PRIV_SPEC_CLASS_1P11)
In privilege spec 1.11 the 'dscratch' register was renamed to
'dscratch0', however the meaning of the register didn't change.
Adding the 'dscratch' alias makes sense I think.
Looking then at the final PRIV_SPEC_CLASS_* field for each alias then
we can see that currently we only want to take the alias from
PRIV_SPEC_CLASS_1P11. For now then this is what I'm using to filter
the aliases within GDB.
In the future there's no telling how DECLARE_CSR_ALIAS will be used.
I've heard it said that future RISC-V privilege specs will not reuse
CSR offsets again. But it could happen. We just don't know.
If / when it does we may need to revisit how aliases are created for
GDB, but for now this seems to be OK.
gdb/ChangeLog:
* riscv-tdep.c (riscv_create_csr_aliases): Handle csr aliases from
riscv-opc.h.
(class riscv_pending_register_alias): New class.
(riscv_check_tdesc_feature): Take vector of pending aliases and
populate it as appropriate.
(riscv_setup_register_aliases): Delete.
(riscv_gdbarch_init): Create vector of pending aliases and pass it
to riscv_check_tdesc_feature in all cases. Use the vector to
create the register aliases.
---
gdb/ChangeLog | 12 ++++++
gdb/riscv-tdep.c | 95 +++++++++++++++++++++++++++++++++---------------
2 files changed, 78 insertions(+), 29 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index fa43c8d02f2..64ec9b4a257 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -258,6 +258,16 @@ riscv_create_csr_aliases ()
int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
const char *alias = xstrprintf ("csr%d", csr_num);
reg.names.push_back (alias);
+
+ /* Setup the other csr aliases. We don't use a switch table here in
+ case there are multiple aliases with the same value. Also filter
+ based on ABRT_VER in order to avoid a very old alias for misa that
+ duplicates the name "misa" but at a different CSR address. */
+#define DECLARE_CSR_ALIAS(NAME,VALUE,CLASS,DEF_VER,ABRT_VER) \
+ if (csr_num == VALUE && ABRT_VER >= PRIV_SPEC_CLASS_1P11) \
+ reg.names.push_back ( # NAME );
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR_ALIAS
}
}
@@ -2945,6 +2955,37 @@ riscv_find_default_target_description (const struct gdbarch_info info)
return riscv_lookup_target_description (features);
}
+/* Information about a register alias that needs to be set up for this
+ target. These are collected when the target's XML description is
+ analysed, and then processed later, once the gdbarch has been created. */
+
+class riscv_pending_register_alias
+{
+public:
+ /* Constructor. */
+
+ riscv_pending_register_alias (const char *name, const void *baton)
+ : m_name (name),
+ m_baton (baton)
+ { /* Nothing. */ }
+
+ /* Convert this into a user register for GDBARCH. */
+
+ void create (struct gdbarch *gdbarch) const
+ {
+ user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton);
+ }
+
+private:
+ /* The name for this alias. */
+ const char *m_name;
+
+ /* The baton value for passing to user_reg_add. This must point to some
+ data that will live for at least as long as the gdbarch object to
+ which the user register is attached. */
+ const void *m_baton;
+};
+
/* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
is updated with the register numbers for each register as listed in
REG_SET. If any register marked as required in REG_SET is not found in
@@ -2953,7 +2994,8 @@ riscv_find_default_target_description (const struct gdbarch_info info)
static bool
riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
const struct tdesc_feature *feature,
- const struct riscv_register_feature *reg_set)
+ const struct riscv_register_feature *reg_set,
+ std::vector<riscv_pending_register_alias> *aliases)
{
for (const auto ® : reg_set->registers)
{
@@ -2965,7 +3007,15 @@ riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
if (found)
- break;
+ {
+ /* We know that the target description mentions this
+ register. In RISCV_REGISTER_NAME we ensure that GDB
+ always uses the first name for each register, so here we
+ add aliases for all of the remaining names. */
+ for (int i = 0; i < reg.names.size (); ++i)
+ aliases->emplace_back (reg.names[i], (void *)®.regnum);
+ break;
+ }
}
if (!found && reg.required_p)
@@ -2993,24 +3043,6 @@ riscv_add_reggroups (struct gdbarch *gdbarch)
reggroup_add (gdbarch, csr_reggroup);
}
-/* Create register aliases for all the alternative names that exist for
- registers in REG_SET. */
-
-static void
-riscv_setup_register_aliases (struct gdbarch *gdbarch,
- const struct riscv_register_feature *reg_set)
-{
- for (auto ® : reg_set->registers)
- {
- /* The first item in the names list is the preferred name for the
- register, this is what RISCV_REGISTER_NAME returns, and so we
- don't need to create an alias with that name here. */
- for (int i = 1; i < reg.names.size (); ++i)
- user_reg_add (gdbarch, reg.names[i], value_of_riscv_user_reg,
- ®.regnum);
- }
-}
-
/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
static int
@@ -3114,10 +3146,12 @@ riscv_gdbarch_init (struct gdbarch_info info,
return NULL;
struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
+ std::vector<riscv_pending_register_alias> pending_aliases;
bool valid_p = riscv_check_tdesc_feature (tdesc_data,
feature_cpu,
- &riscv_xreg_feature);
+ &riscv_xreg_feature,
+ &pending_aliases);
if (valid_p)
{
/* Check that all of the core cpu registers have the same bitsize. */
@@ -3137,7 +3171,8 @@ riscv_gdbarch_init (struct gdbarch_info info,
if (feature_fpu != NULL)
{
valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
- &riscv_freg_feature);
+ &riscv_freg_feature,
+ &pending_aliases);
/* Search for the first floating point register (by any alias), to
determine the bitsize. */
@@ -3173,11 +3208,13 @@ riscv_gdbarch_init (struct gdbarch_info info,
if (feature_virtual)
riscv_check_tdesc_feature (tdesc_data, feature_virtual,
- &riscv_virtual_feature);
+ &riscv_virtual_feature,
+ &pending_aliases);
if (feature_csr)
riscv_check_tdesc_feature (tdesc_data, feature_csr,
- &riscv_csr_feature);
+ &riscv_csr_feature,
+ &pending_aliases);
if (!valid_p)
{
@@ -3315,11 +3352,11 @@ riscv_gdbarch_init (struct gdbarch_info info,
want, ignoring what the target tells us. */
set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
- /* Create register aliases for alternative register names. */
- riscv_setup_register_aliases (gdbarch, &riscv_xreg_feature);
- if (riscv_has_fp_regs (gdbarch))
- riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
- riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
+ /* Create register aliases for alternative register names. We only
+ create aliases for registers which were mentioned in the target
+ description. */
+ for (const auto &alias : pending_aliases)
+ alias.create (gdbarch);
/* Compile command hooks. */
set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options);
--
2.25.4
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 2/2] gdb/riscv: Take CSR names from target description
2020-06-11 13:16 ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 1/2] " Andrew Burgess
@ 2020-06-11 13:16 ` Andrew Burgess
2020-06-11 14:06 ` [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation Tom Tromey
2 siblings, 0 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-11 13:16 UTC (permalink / raw)
To: gdb-patches
First, consider the RISC-V register $x1. This register has an alias
$ra. When GDB processes an incoming target description we allow the
target to use either register name to describe the target.
However, within GDB's UI we want to use the $ra alias in preference to
the $x1 architecture name.
To achieve this GDB overrides the tdesc_register_name callback with
riscv_register_name. In riscv_register_name we ensure that we always
return the preferred name, so in this case "ra".
To ensure the user can still access the register as $x1 if they want
to, when in riscv_check_tdesc_feature we spot that the target has
supplied the register, we add aliases for every name except the
preferred one, so in this case we add the alias "x1".
This scheme seems to work quite well, the targets have the flexibility
to be architecture focused if they wish (using x0 - x31) while GDB is
still using the ABI names ra, sp, gp, etc.
When this code was originally added there was an attempt made to
include the CSRs in the same scheme. At the time the CSRs only had
two names, one pulled from riscv-opc.h, and one generated in GDB that
had the pattern csr%d.
The idea was that if the remote targets description described the CSRs
as csr%d then GDB would rename these back to the real CSR name. This
code was only included because if followed the same pattern as the
x-regs and f-regs, not because I was actually aware of any target that
did this.
However, recent changes to add additional CSR aliases has made me
rethink the position here.
Lets consider the CSR $dscratch0. This register has an alias
'csr1970' (1970 is 0x7b2, which is the offset of the CSR register into
the CSR address space). However, this register was originally called
just 'dscratch', and so, after recent commits, this register also has
the alias 'dscratch'.
As the riscv-opc.h file calls this register 'dscratch0' GDB's
preferred name for this register is 'dscratch0'.
So, if the remote target description includes the register
'dscratch0', then GDB will add the aliases 'dscratch', and 'csr1970'.
In the UI GDB will describe the register as 'dscratch0', and all it
good.
The problem I see in this case is where the target describes the
register as 'dscratch'. In this case GDB will still spot the register
and add the aliases 'dscratch', and 'csr1970', GDB will then give the
register the preferred name 'dscratch0'.
I don't like this. For the CSRs I think that we should stick with the
naming scheme offered by the remote target description. As the RISC-V
specification evolves and CSR register names evolve, insisting on
referring to registers by the most up to date name makes it harder for
a target to provide a consistent target description for an older
version of the RISC-V architecture spec.
In this precise case the target offers 'dscratch', which is from an
older version of the RISC-V specification, the newer version of the
spec has two registers 'dscratch0' and 'dscratch1'. If we insist on
using 'dscratch0' it is then a little "weird" (or seems so to me) when
'dscratch1' is missing.
This patch makes a distinction between the x and f registers and the
other register sets. For x and f we still make use of the renaming
scheme, forcing GDB to prefer the ABI name. But after this patch the
CSR register group, and also the virtual register group, will always
prefer to use the name given in the target description, adding other
names as aliases, but not making any other name the preferred name.
gdb/ChangeLog:
* riscv-tdep.c (struct riscv_register_feature::register_info): Fix
whitespace error for declaration of names member variable.
(struct riscv_register_feature): Add new prefer_first_name member
variable, and fix whitespace error in declaration of registers.
(riscv_xreg_feature): Initialize prefer_first_name field.
(riscv_freg_feature): Likewise.
(riscv_virtual_feature): Likewise.
(riscv_csr_feature): Likewise.
(riscv_register_name): Expand on comments. Remove register name
modifications for CSR and virtual registers.
---
gdb/ChangeLog | 13 ++++++++
gdb/riscv-tdep.c | 79 +++++++++++++++++++++++++++++-------------------
2 files changed, 61 insertions(+), 31 deletions(-)
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 64ec9b4a257..b136cbdfbf4 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -115,7 +115,7 @@ struct riscv_register_feature
/* List of names for this register. The first name in this list is the
preferred name, the name GDB should use when describing this
register. */
- std::vector <const char *> names;
+ std::vector<const char *> names;
/* When true this register is required in this feature set. */
bool required_p;
@@ -125,16 +125,30 @@ struct riscv_register_feature
within the target description. */
const char *name;
+ /* For x-regs and f-regs we always force GDB to use the first name from
+ the REGISTERS.NAMES vector, it is therefore important that we create
+ user-register aliases for all of the remaining names at indexes 1+ in
+ the names vector.
+
+ For CSRs we take a different approach, we prefer whatever name the
+ target description uses, in this case we want to create user-register
+ aliases for any other names that aren't the target description
+ provided name.
+
+ When this flag is true we are dealing with the first case, and when
+ this is false we are dealing with the latter. */
+ bool prefer_first_name;
+
/* List of all the registers that we expect that we might find in this
register set. */
- std::vector <struct register_info> registers;
+ std::vector<struct register_info> registers;
};
/* The general x-registers feature set. */
static const struct riscv_register_feature riscv_xreg_feature =
{
- "org.gnu.gdb.riscv.cpu",
+ "org.gnu.gdb.riscv.cpu", true,
{
{ RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
{ RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
@@ -176,7 +190,7 @@ static const struct riscv_register_feature riscv_xreg_feature =
static const struct riscv_register_feature riscv_freg_feature =
{
- "org.gnu.gdb.riscv.fpu",
+ "org.gnu.gdb.riscv.fpu", true,
{
{ RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true },
{ RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true },
@@ -226,7 +240,7 @@ static const struct riscv_register_feature riscv_freg_feature =
static const struct riscv_register_feature riscv_virtual_feature =
{
- "org.gnu.gdb.riscv.virtual",
+ "org.gnu.gdb.riscv.virtual", false,
{
{ RISCV_PRIV_REGNUM, { "priv" }, false }
}
@@ -238,7 +252,7 @@ static const struct riscv_register_feature riscv_virtual_feature =
static struct riscv_register_feature riscv_csr_feature =
{
- "org.gnu.gdb.riscv.csr",
+ "org.gnu.gdb.riscv.csr", false,
{
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
{ RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
@@ -472,7 +486,7 @@ value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
/* Implement the register_name gdbarch method. This is used instead of
the function supplied by calling TDESC_USE_REGISTERS so that we can
- ensure the preferred names are offered. */
+ ensure the preferred names are offered for x-regs and f-regs. */
static const char *
riscv_register_name (struct gdbarch *gdbarch, int regnum)
@@ -484,12 +498,18 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
if (name == NULL || name[0] == '\0')
return NULL;
+ /* We want GDB to use the ABI names for registers even if the target
+ gives us a target description with the architectural name. For
+ example we want to see 'ra' instead of 'x1' whatever the target
+ description called it. */
if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
{
gdb_assert (regnum < riscv_xreg_feature.registers.size ());
return riscv_xreg_feature.registers[regnum].names[0];
}
+ /* Like with the x-regs we prefer the abi names for the floating point
+ registers. */
if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
{
if (riscv_has_fp_regs (gdbarch))
@@ -502,28 +522,18 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
return NULL;
}
- /* Check that there's no gap between the set of registers handled above,
- and the set of registers handled next. */
- gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
-
- if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
- {
-#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
- case RISCV_ ## VALUE ## _REGNUM: return # NAME;
-
- switch (regnum)
- {
-#include "opcode/riscv-opc.h"
- }
-#undef DECLARE_CSR
- }
+ /* The remaining registers are different. For all other registers on the
+ machine we prefer to see the names that the target description
+ provides. This is particularly important for CSRs which might be
+ renamed over time. If GDB keeps track of the "latest" name, but a
+ particular target provides an older name then we don't want to force
+ users to see the newer name in register output.
- if (regnum == RISCV_PRIV_REGNUM)
- return "priv";
+ The other case that reaches here are any registers that the target
+ provided that GDB is completely unaware of. For these we have no
+ choice but to accept the target description name.
- /* It is possible that that the target provides some registers that GDB
- is unaware of, in that case just return the NAME from the target
- description. */
+ Just accept whatever name TDESC_REGISTER_NAME returned. */
return name;
}
@@ -3003,8 +3013,8 @@ riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
for (const char *name : reg.names)
{
- found =
- tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
+ found = tdesc_numbered_register (feature, tdesc_data, reg.regnum,
+ name);
if (found)
{
@@ -3012,8 +3022,15 @@ riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
register. In RISCV_REGISTER_NAME we ensure that GDB
always uses the first name for each register, so here we
add aliases for all of the remaining names. */
- for (int i = 0; i < reg.names.size (); ++i)
- aliases->emplace_back (reg.names[i], (void *)®.regnum);
+ bool prefer_first_name = reg_set->prefer_first_name;
+ int start_index = prefer_first_name ? 1 : 0;
+ for (int i = start_index; i < reg.names.size (); ++i)
+ {
+ const char *alias = reg.names[i];
+ if (alias == name && !prefer_first_name)
+ continue;
+ aliases->emplace_back (alias, (void *)®.regnum);
+ }
break;
}
}
--
2.25.4
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-11 13:16 ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 1/2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 2/2] gdb/riscv: Take CSR names from target description Andrew Burgess
@ 2020-06-11 14:06 ` Tom Tromey
2020-06-12 22:34 ` Andrew Burgess
2 siblings, 1 reply; 34+ messages in thread
From: Tom Tromey @ 2020-06-11 14:06 UTC (permalink / raw)
To: Andrew Burgess; +Cc: gdb-patches
>>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
Andrew> I now have two patches. The first alone should be enough to get
Andrew> things working for you now; it's basically the same patch as before
Andrew> but with a small bug fix.
[...]
Andrew> This leaves just one question from me. I thought that your original
Andrew> thread started by saying that once upon a time you could successfully
Andrew> read the dscratch and/or the dscratch0 registers. The some patches
Andrew> landed and you could no longer read the registers.
Andrew> From what I'm seeing though, the _actual_ failure to read the register
Andrew> is all QEMU. So my question, did I missunderstand the original
Andrew> problem? Is there a build of GDB where you are able to read actual
Andrew> values from these registers?
We discussed this on irc a little. The tests where I would connect and
print various registers don't seem to reflect the failures I was
actually seeing. So, for example "print $dscratch" might say "= void"
... meaning this was an uninitialized convenience variable rather than a
register.
The actual failure is that some operation in gdb fails, saying a
register isn't available. For example, one test case fails when it
tries to do an inferior call.
I applied your patches to git master (no local patches at all) and it
fails like so:
(gdb) call debug.trace (me, "You")
Could not fetch register "mucounteren"; remote failure reply 'E14'
However, if I check out commit d8af906814b (the one before the first
round of RISC-V changes we're talking about), it works:
(gdb) call debug.trace (me, "You")
(gdb)
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-11 14:06 ` [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation Tom Tromey
@ 2020-06-12 22:34 ` Andrew Burgess
2020-06-15 20:27 ` Tom Tromey
0 siblings, 1 reply; 34+ messages in thread
From: Andrew Burgess @ 2020-06-12 22:34 UTC (permalink / raw)
To: Tom Tromey; +Cc: gdb-patches
* Tom Tromey <tom@tromey.com> [2020-06-11 08:06:09 -0600]:
> >>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
>
> Andrew> I now have two patches. The first alone should be enough to get
> Andrew> things working for you now; it's basically the same patch as before
> Andrew> but with a small bug fix.
>
> [...]
>
> Andrew> This leaves just one question from me. I thought that your original
> Andrew> thread started by saying that once upon a time you could successfully
> Andrew> read the dscratch and/or the dscratch0 registers. The some patches
> Andrew> landed and you could no longer read the registers.
>
> Andrew> From what I'm seeing though, the _actual_ failure to read the register
> Andrew> is all QEMU. So my question, did I missunderstand the original
> Andrew> problem? Is there a build of GDB where you are able to read actual
> Andrew> values from these registers?
>
> We discussed this on irc a little. The tests where I would connect and
> print various registers don't seem to reflect the failures I was
> actually seeing. So, for example "print $dscratch" might say "= void"
> ... meaning this was an uninitialized convenience variable rather than a
> register.
>
> The actual failure is that some operation in gdb fails, saying a
> register isn't available. For example, one test case fails when it
> tries to do an inferior call.
>
> I applied your patches to git master (no local patches at all) and it
> fails like so:
>
> (gdb) call debug.trace (me, "You")
> Could not fetch register "mucounteren"; remote failure reply 'E14'
>
> However, if I check out commit d8af906814b (the one before the first
> round of RISC-V changes we're talking about), it works:
>
> (gdb) call debug.trace (me, "You")
> (gdb)
So I finally figured out what's happening, and I feel like I opened a
(smallish) can of worms...
What happens is this. When we make an inferior call, any register
that is in the 'save' register group is, well, saved before the call,
and restored afterwards.
The default behaviour for a register in the target description is to
be in the save set.
The problem with this is that QEMU announces many registers, for
example, mucounteren, but then doesn't actually let GDB read it. If
any register fails to read before an inferior call then it can't be
backed up, so GDB aborts the inferior call.
The _ideal_ solution here would be either (a) QEMU doesn't announce
registers that GDB can't read, or (b) QEMU marks registers that can't
_always_ be read as no-save.
Still, we work with what we've got, right? In order to work around
this issue in the past the RISC-V target provides
riscv_register_reggroup_p, which overrides the usual target
description method for figuring out if a register is in a particular
group. This RISC-V method specifically says that the CSRs (except for
the floating point status CSRs) should not be included in the save
register set. Problem solved.
Except, in commit d8af906814b we changed the set of CSRs that GDB
knows about, removing mucounteren. Now this shouldn't be a problem.
QEMU still announces the register, GDB can still access it.
Everything is still good. But, internally, we no longer see this as
part of the CSRs, it's just "some other register that the target
offers", and as we don't know what to do with this, we just do what
the target tells us, which is the default, please save this registers.
Only we can't save that register, as we can't read it.
So, when I started working on this problem, I ran into another issue,
which isn't a show stopper, but is an annoyance. GDB's builtin XML
files, include the fflags, fcsr, and frm registers twice, once in the
FPU feature, and once in the CSR feature, and as QEMU copied its XML
files from GDB, QEMU also announces these regiters twice. If you
connect to QEMU and then do:
(gdb) info registers save
You'll see these three regiters appear twice. Which is pretty
annoying.
Anyway. The patch below attempts to tackle both of these issues, with
this your inferior call issue should be resolved. This is totally a
WIP right now, I'm just sharing it so you can test this. I don't know
if the final solution I go with should actually be this complex, or if
I should take a simpler approach.
I'm going to think this through for a couple of days, and play with a
few ideas, but I was hoping you might confirm this patch resolves the
issue you're seeing in the mean time.
Thanks,
Andrew
---
commit 3581151a580b5fb561ff088e6ac9e963cdb2ddd0
Author: Andrew Burgess <andrew.burgess@embecosm.com>
Date: Fri Jun 12 23:14:23 2020 +0100
WIP: Handle unknown target description registers
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index b136cbdfbf4..6c70a1526f3 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -522,6 +522,15 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum)
return NULL;
}
+ /* Hide these registers. */
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ if (tdep->duplicate_fflags == regnum)
+ return NULL;
+ if (tdep->duplicate_frm == regnum)
+ return NULL;
+ if (tdep->duplicate_fcsr == regnum)
+ return NULL;
+
/* The remaining registers are different. For all other registers on the
machine we prefer to see the names that the target description
provides. This is particularly important for CSRs which might be
@@ -873,6 +882,13 @@ riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
if (regnum > RISCV_LAST_REGNUM)
{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if ((reggroup == restore_reggroup || reggroup == save_reggroup)
+ && regnum >= tdep->first_extra_csr_regnum
+ && regnum < (tdep->first_extra_csr_regnum + tdep->extra_csr_count))
+ return 0;
+
int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
if (ret != -1)
return ret;
@@ -3015,7 +3031,6 @@ riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
{
found = tdesc_numbered_register (feature, tdesc_data, reg.regnum,
name);
-
if (found)
{
/* We know that the target description mentions this
@@ -3116,6 +3131,72 @@ riscv_gcc_target_options (struct gdbarch *gdbarch)
return target_options;
}
+/* ... */
+
+static int
+riscv_unknown_tdesc_reg (struct gdbarch *gdbarch, tdesc_feature *feature,
+ const char *reg_name, int possible_regnum)
+{
+ /* At one point in time GDB had an incorrect default target description
+ that duplicated the fflags, frm, and fcsr registers in both the FPU
+ and CSR register sets.
+
+ Some targets (QEMU) copied these target descriptions into their source
+ tree, and so we're currently stuck working with some targets that
+ declare the same registers twice.
+
+ There's not much we can do about this any more. Assuming the target
+ will direct a request for either register number to the correct
+ underlying hardware register then it doesn't matter which one GDB
+ uses, so long as we (GDB) are consistent (so that we don't end up with
+ invalid cache misses).
+
+ As we always scan the FPU registers first, then the CSRs, if the
+ target has included the offending registers in both sets then we will
+ always see the FPU copies here, as the CSR versions will replace them
+ in the register list.
+
+ To prevent these duplicates showing up in any of the register list,
+ record their register numbers here. */
+ if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name) == 0)
+ {
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ if (strcmp (reg_name, "fflags") == 0)
+ {
+ gdb_assert (tdep->duplicate_fflags == -1);
+ tdep->duplicate_fflags = possible_regnum;
+ return possible_regnum;
+ }
+
+ if (strcmp (reg_name, "frm") == 0)
+ {
+ gdb_assert (tdep->duplicate_frm == -1);
+ tdep->duplicate_frm = possible_regnum;
+ return possible_regnum;
+ }
+
+ if (strcmp (reg_name, "fcsr") == 0)
+ {
+ gdb_assert (tdep->duplicate_fcsr == -1);
+ tdep->duplicate_fcsr = possible_regnum;
+ return possible_regnum;
+ }
+ }
+
+ if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name) == 0)
+ {
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ if (tdep->first_extra_csr_regnum == -1)
+ tdep->first_extra_csr_regnum = possible_regnum;
+ gdb_assert (tdep->first_extra_csr_regnum
+ + tdep->extra_csr_count == possible_regnum);
+ tdep->extra_csr_count++;
+ return possible_regnum;
+ }
+ return -1;
+}
+
/* Implement the gnu_triplet_regexp method. A single compiler supports both
32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
recommended) riscv. */
@@ -3352,6 +3433,7 @@ riscv_gdbarch_init (struct gdbarch_info info,
set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
/* Finalise the target description registers. */
+ set_tdesc_unknown_register_handler (gdbarch, riscv_unknown_tdesc_reg);
tdesc_use_registers (gdbarch, tdesc, tdesc_data);
/* Override the register type callback setup by the target description
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index e415fb4a7a1..69f742f4333 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -79,6 +79,14 @@ struct gdbarch_tdep
/* ISA-specific data types. */
struct type *riscv_fpreg_d_type = nullptr;
+
+ int first_extra_csr_regnum = -1;
+ int extra_csr_count = 0;
+
+ int duplicate_fflags = -1;
+ int duplicate_frm = -1;
+ int duplicate_fcsr = -1;
+
};
diff --git a/gdb/target-descriptions.c b/gdb/target-descriptions.c
index 20a3a640f4f..351cd4ab166 100644
--- a/gdb/target-descriptions.c
+++ b/gdb/target-descriptions.c
@@ -407,6 +407,10 @@ struct tdesc_arch_data
gdbarch_register_name_ftype *pseudo_register_name = NULL;
gdbarch_register_type_ftype *pseudo_register_type = NULL;
gdbarch_register_reggroup_p_ftype *pseudo_register_reggroup_p = NULL;
+
+ /* Function to (possibly) assign register numbers for unknown
+ registers. */
+ tdesc_unknown_register_ftype *unknown_register_handler = NULL;
};
/* Info about an inferior's target description. There's one of these
@@ -1051,6 +1055,16 @@ set_tdesc_pseudo_register_reggroup_p
data->pseudo_register_reggroup_p = pseudo_reggroup_p;
}
+void set_tdesc_unknown_register_handler
+ (struct gdbarch *gdbarch,
+ tdesc_unknown_register_ftype *handler)
+{
+ struct tdesc_arch_data *data
+ = (struct tdesc_arch_data *) gdbarch_data (gdbarch, tdesc_data);
+
+ data->unknown_register_handler = handler;
+}
+
/* Update GDBARCH to use the target description for registers. */
void
@@ -1105,6 +1119,36 @@ tdesc_use_registers (struct gdbarch *gdbarch,
while (data->arch_regs.size () < num_regs)
data->arch_regs.emplace_back (nullptr, nullptr);
+ /* First we give the target a chance to number previously unknown
+ registers. This allows targets to record the numbers assigned based
+ on which feature the register was from. */
+ if (data->unknown_register_handler != NULL)
+ {
+ for (const tdesc_feature_up &feature : target_desc->features)
+ for (const tdesc_reg_up ® : feature->registers)
+ if (htab_find (reg_hash, reg.get ()) != NULL)
+ {
+ int regno
+ = data->unknown_register_handler (gdbarch, feature.get (),
+ reg->name.c_str (),
+ num_regs);
+ gdb_assert (regno == -1 || regno >= num_regs);
+ if (regno != -1)
+ {
+ while (regno >= data->arch_regs.size ())
+ data->arch_regs.emplace_back (nullptr, nullptr);
+ data->arch_regs[regno] = tdesc_arch_reg (reg.get (), NULL);
+ num_regs = regno + 1;
+ htab_remove_elt (reg_hash, reg.get ());
+ }
+ }
+ }
+
+ /* Ensure the array was sized correctly above. */
+ gdb_assert (data->arch_regs.size () == num_regs);
+
+ /* Now in a final pass we assign register numbers to any remaining
+ unnumbered registers. */
for (const tdesc_feature_up &feature : target_desc->features)
for (const tdesc_reg_up ® : feature->registers)
if (htab_find (reg_hash, reg.get ()) != NULL)
@@ -1680,7 +1724,7 @@ maint_print_c_tdesc_cmd (const char *args, int from_tty)
error (_("There is no target description to print."));
if (filename == NULL)
- error (_("The current target description did not come from an XML file."));
+ filename = "fetched from target";
std::string filename_after_features (filename);
auto loc = filename_after_features.rfind ("/features/");
diff --git a/gdb/target-descriptions.h b/gdb/target-descriptions.h
index 96d283fb379..fb6da4add4c 100644
--- a/gdb/target-descriptions.h
+++ b/gdb/target-descriptions.h
@@ -80,6 +80,14 @@ void set_tdesc_pseudo_register_reggroup_p
(struct gdbarch *gdbarch,
gdbarch_register_reggroup_p_ftype *pseudo_reggroup_p);
+typedef int (tdesc_unknown_register_ftype)
+ (struct gdbarch *gdbarch, tdesc_feature *feature,
+ const char *reg_name, int possible_regnum);
+
+void set_tdesc_unknown_register_handler
+ (struct gdbarch *gdbarch,
+ tdesc_unknown_register_ftype *handler);
+
/* Update GDBARCH to use the TARGET_DESC for registers. TARGET_DESC
may be GDBARCH's target description or (if GDBARCH does not have
one which describes registers) another target description
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-12 22:34 ` Andrew Burgess
@ 2020-06-15 20:27 ` Tom Tromey
2020-06-16 7:56 ` Andrew Burgess
0 siblings, 1 reply; 34+ messages in thread
From: Tom Tromey @ 2020-06-15 20:27 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, gdb-patches
>>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
Andrew> Anyway. The patch below attempts to tackle both of these issues, with
Andrew> this your inferior call issue should be resolved. This is totally a
Andrew> WIP right now, I'm just sharing it so you can test this. I don't know
Andrew> if the final solution I go with should actually be this complex, or if
Andrew> I should take a simpler approach.
I didn't read it deeply yet... I meant to look today but ran out of time.
Andrew> I'm going to think this through for a couple of days, and play with a
Andrew> few ideas, but I was hoping you might confirm this patch resolves the
Andrew> issue you're seeing in the mean time.
I did try it on my simple test case (the one I sent) and I can confirm
it works there.
I haven't run our internal test suite using it. That's somewhat more
involved, especially since today it took a little while to figure out
which patches to base this on.
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-15 20:27 ` Tom Tromey
@ 2020-06-16 7:56 ` Andrew Burgess
2020-06-16 12:03 ` Tom Tromey
0 siblings, 1 reply; 34+ messages in thread
From: Andrew Burgess @ 2020-06-16 7:56 UTC (permalink / raw)
To: Tom Tromey; +Cc: gdb-patches
* Tom Tromey <tom@tromey.com> [2020-06-15 14:27:44 -0600]:
> >>>>> "Andrew" == Andrew Burgess <andrew.burgess@embecosm.com> writes:
>
> Andrew> Anyway. The patch below attempts to tackle both of these issues, with
> Andrew> this your inferior call issue should be resolved. This is totally a
> Andrew> WIP right now, I'm just sharing it so you can test this. I don't know
> Andrew> if the final solution I go with should actually be this complex, or if
> Andrew> I should take a simpler approach.
>
> I didn't read it deeply yet... I meant to look today but ran out of time.
>
> Andrew> I'm going to think this through for a couple of days, and play with a
> Andrew> few ideas, but I was hoping you might confirm this patch resolves the
> Andrew> issue you're seeing in the mean time.
>
> I did try it on my simple test case (the one I sent) and I can confirm
> it works there.
Glad this fixed the issue.
>
> I haven't run our internal test suite using it. That's somewhat more
> involved, especially since today it took a little while to figure out
> which patches to base this on.
Sorry this didn't apply cleanly. I just continued working in my dev
branch so this last patch would have applied on top of the previous
two patches from this thread.
I'm still putting together a cleaned up version of all the patches in
this thread, along with a bunch of other RISC-V related improvements,
all around target description handling.
I'm hopeful that I might get something posted today.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-16 7:56 ` Andrew Burgess
@ 2020-06-16 12:03 ` Tom Tromey
2020-06-16 20:39 ` Andrew Burgess
0 siblings, 1 reply; 34+ messages in thread
From: Tom Tromey @ 2020-06-16 12:03 UTC (permalink / raw)
To: Andrew Burgess; +Cc: Tom Tromey, gdb-patches
>> I haven't run our internal test suite using it. That's somewhat more
>> involved, especially since today it took a little while to figure out
>> which patches to base this on.
Andrew> Sorry this didn't apply cleanly. I just continued working in my dev
Andrew> branch so this last patch would have applied on top of the previous
Andrew> two patches from this thread.
Yeah, I figured it out in the end -- no big deal.
This morning I applied it to the AdaCore tree and ran the AdaCore test
suite. I'm happy to report that this was a complete success.
Tom
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation
2020-06-16 12:03 ` Tom Tromey
@ 2020-06-16 20:39 ` Andrew Burgess
0 siblings, 0 replies; 34+ messages in thread
From: Andrew Burgess @ 2020-06-16 20:39 UTC (permalink / raw)
To: Tom Tromey; +Cc: gdb-patches
* Tom Tromey <tom@tromey.com> [2020-06-16 06:03:34 -0600]:
> >> I haven't run our internal test suite using it. That's somewhat more
> >> involved, especially since today it took a little while to figure out
> >> which patches to base this on.
>
> Andrew> Sorry this didn't apply cleanly. I just continued working in my dev
> Andrew> branch so this last patch would have applied on top of the previous
> Andrew> two patches from this thread.
>
> Yeah, I figured it out in the end -- no big deal.
> This morning I applied it to the AdaCore tree and ran the AdaCore test
> suite. I'm happy to report that this was a complete success.
Glad testing went well.
I've posted all the patches in this thread as a brand new series here:
https://sourceware.org/pipermail/gdb-patches/2020-June/169561.html
You will be most interested in patches #6 and #7 in that series, which
should provide the same fix you have already tested, though as you
discovered at least some of patches #1 -> #5 will be required in order
for the later to merge cleanly.
Thanks,
Andrew
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2020-06-16 20:39 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-12 10:00 [0/1] RISC-V: Update CSR to priv 1.11 Nelson Chu
2020-03-12 10:00 ` [PATCH] RISC-V: Update CSR to privileged spec 1.11 Nelson Chu
2020-03-24 5:05 ` [PING] " Nelson Chu
2020-03-24 8:51 ` Andrew Burgess
2020-03-24 9:11 ` Nelson Chu
2020-06-08 15:37 ` [0/1] RISC-V: Update CSR to priv 1.11 Tom Tromey
2020-06-08 21:39 ` Andrew Burgess
2020-06-09 1:19 ` Jim Wilson
2020-06-09 10:27 ` Andrew Burgess
2020-06-09 20:12 ` Tom Tromey
2020-06-09 17:30 ` [RFC] gdb/riscv: Improved register alias name creation Andrew Burgess
2020-06-09 20:14 ` Jim Wilson
2020-06-09 22:47 ` Andrew Burgess
2020-06-10 9:31 ` Nelson Chu
2020-06-10 10:55 ` Andrew Burgess
2020-06-10 13:26 ` Nelson Chu
2020-06-09 20:54 ` Tom Tromey
2020-06-09 22:30 ` Andrew Burgess
[not found] ` <8736735bjx.fsf@tromey.com>
2020-06-10 13:01 ` Tom Tromey
2020-06-10 20:37 ` Jim Wilson
2020-06-11 8:28 ` Andrew Burgess
2020-06-09 22:58 ` Andrew Burgess
2020-06-10 12:53 ` Tom Tromey
[not found] ` <87mu5b3vm3.fsf@tromey.com>
2020-06-10 14:46 ` Tom Tromey
2020-06-11 13:16 ` [PATCH 0/2] [PATCHv2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 1/2] " Andrew Burgess
2020-06-11 13:16 ` [PATCH 2/2] gdb/riscv: Take CSR names from target description Andrew Burgess
2020-06-11 14:06 ` [PATCH 0/2] [PATCHv2] gdb/riscv: Improved register alias name creation Tom Tromey
2020-06-12 22:34 ` Andrew Burgess
2020-06-15 20:27 ` Tom Tromey
2020-06-16 7:56 ` Andrew Burgess
2020-06-16 12:03 ` Tom Tromey
2020-06-16 20:39 ` Andrew Burgess
2020-06-10 20:34 ` [RFC] " Jim Wilson
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